1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 SiFive
8 #include <asm/cacheinfo.h>
10 static struct riscv_cacheinfo_ops *rv_cache_ops;
12 void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops)
16 EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops);
18 const struct attribute_group *
19 cache_get_priv_group(struct cacheinfo *this_leaf)
21 if (rv_cache_ops && rv_cache_ops->get_priv_group)
22 return rv_cache_ops->get_priv_group(this_leaf);
26 static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
29 * Using raw_smp_processor_id() elides a preemptability check, but this
30 * is really indicative of a larger problem: the cacheinfo UABI assumes
31 * that cores have a homonogenous view of the cache hierarchy. That
32 * happens to be the case for the current set of RISC-V systems, but
33 * likely won't be true in general. Since there's no way to provide
34 * correct information for these systems via the current UABI we're
35 * just eliding the check for now.
37 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id());
38 struct cacheinfo *this_leaf;
41 for (index = 0; index < this_cpu_ci->num_leaves; index++) {
42 this_leaf = this_cpu_ci->info_list + index;
43 if (this_leaf->level == level && this_leaf->type == type)
50 uintptr_t get_cache_size(u32 level, enum cache_type type)
52 struct cacheinfo *this_leaf = get_cacheinfo(level, type);
54 return this_leaf ? this_leaf->size : 0;
57 uintptr_t get_cache_geometry(u32 level, enum cache_type type)
59 struct cacheinfo *this_leaf = get_cacheinfo(level, type);
61 return this_leaf ? (this_leaf->ways_of_associativity << 16 |
62 this_leaf->coherency_line_size) :
66 static void ci_leaf_init(struct cacheinfo *this_leaf,
67 struct device_node *node,
68 enum cache_type type, unsigned int level)
70 this_leaf->level = level;
71 this_leaf->type = type;
74 int populate_cache_leaves(unsigned int cpu)
76 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
77 struct cacheinfo *this_leaf = this_cpu_ci->info_list;
78 struct device_node *np = of_cpu_device_node_get(cpu);
79 struct device_node *prev = NULL;
80 int levels = 1, level = 1;
82 if (of_property_read_bool(np, "cache-size"))
83 ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
84 if (of_property_read_bool(np, "i-cache-size"))
85 ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
86 if (of_property_read_bool(np, "d-cache-size"))
87 ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
90 while ((np = of_find_next_cache_node(np))) {
93 if (!of_device_is_compatible(np, "cache"))
95 if (of_property_read_u32(np, "cache-level", &level))
99 if (of_property_read_bool(np, "cache-size"))
100 ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
101 if (of_property_read_bool(np, "i-cache-size"))
102 ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
103 if (of_property_read_bool(np, "d-cache-size"))
104 ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);