1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2021 Sifive.
5 #ifndef ASM_ERRATA_LIST_H
6 #define ASM_ERRATA_LIST_H
8 #include <asm/alternative.h>
9 #include <asm/vendorid_list.h>
11 #ifdef CONFIG_ERRATA_SIFIVE
12 #define ERRATA_SIFIVE_CIP_453 0
13 #define ERRATA_SIFIVE_CIP_1200 1
14 #define ERRATA_SIFIVE_NUMBER 2
17 #ifdef CONFIG_ERRATA_THEAD
18 #define ERRATA_THEAD_PBMT 0
19 #define ERRATA_THEAD_NUMBER 1
22 #define CPUFEATURE_SVPBMT 0
23 #define CPUFEATURE_NUMBER 1
27 #define ALT_INSN_FAULT(x) \
28 ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
29 __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
30 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
31 CONFIG_ERRATA_SIFIVE_CIP_453)
33 #define ALT_PAGE_FAULT(x) \
34 ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
35 __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
36 SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
37 CONFIG_ERRATA_SIFIVE_CIP_453)
38 #else /* !__ASSEMBLY__ */
40 #define ALT_FLUSH_TLB_PAGE(x) \
41 asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
42 ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
43 : : "r" (addr) : "memory")
46 * _val is marked as "will be overwritten", so need to set it to 0
47 * in the default case.
49 #define ALT_SVPBMT_SHIFT 61
50 #define ALT_THEAD_PBMT_SHIFT 59
51 #define ALT_SVPBMT(_val, prot) \
52 asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
53 "li %0, %1\t\nslli %0,%0,%3", 0, \
54 CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
55 "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
56 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
58 : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
59 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
60 "I"(ALT_SVPBMT_SHIFT), \
61 "I"(ALT_THEAD_PBMT_SHIFT))
63 #ifdef CONFIG_ERRATA_THEAD_PBMT
65 * IO/NOCACHE memory types are handled together with svpbmt,
66 * so on T-Head chips, check if no other memory type is set,
67 * and set the non-0 PMA type if applicable.
69 #define ALT_THEAD_PMA(_val) \
70 asm volatile(ALTERNATIVE( \
79 "slli t3, t3, %3\n\t" \
80 "and t3, %0, t3\n\t" \
81 "bne t3, zero, 2f\n\t" \
83 "slli t3, t3, %3\n\t" \
85 "2:", THEAD_VENDOR_ID, \
86 ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
88 : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
89 "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \
90 "I"(ALT_THEAD_PBMT_SHIFT) \
93 #define ALT_THEAD_PMA(_val)
96 #endif /* __ASSEMBLY__ */