1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
6 #ifndef _ASM_RISCV_BITOPS_H
7 #define _ASM_RISCV_BITOPS_H
9 #ifndef _LINUX_BITOPS_H
10 #error "Only <linux/bitops.h> can be included directly"
11 #endif /* _LINUX_BITOPS_H */
13 #include <linux/compiler.h>
14 #include <linux/irqflags.h>
15 #include <asm/barrier.h>
16 #include <asm/bitsperlong.h>
18 #include <asm-generic/bitops/__ffs.h>
19 #include <asm-generic/bitops/ffz.h>
20 #include <asm-generic/bitops/fls.h>
21 #include <asm-generic/bitops/__fls.h>
22 #include <asm-generic/bitops/fls64.h>
23 #include <asm-generic/bitops/sched.h>
24 #include <asm-generic/bitops/ffs.h>
26 #include <asm-generic/bitops/hweight.h>
28 #if (BITS_PER_LONG == 64)
29 #define __AMO(op) "amo" #op ".d"
30 #elif (BITS_PER_LONG == 32)
31 #define __AMO(op) "amo" #op ".w"
33 #error "Unexpected BITS_PER_LONG"
36 #define __test_and_op_bit_ord(op, mod, nr, addr, ord) \
38 unsigned long __res, __mask; \
39 __mask = BIT_MASK(nr); \
40 __asm__ __volatile__ ( \
41 __AMO(op) #ord " %0, %2, %1" \
42 : "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \
45 ((__res & __mask) != 0); \
48 #define __op_bit_ord(op, mod, nr, addr, ord) \
49 __asm__ __volatile__ ( \
50 __AMO(op) #ord " zero, %1, %0" \
51 : "+A" (addr[BIT_WORD(nr)]) \
52 : "r" (mod(BIT_MASK(nr))) \
55 #define __test_and_op_bit(op, mod, nr, addr) \
56 __test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
57 #define __op_bit(op, mod, nr, addr) \
58 __op_bit_ord(op, mod, nr, addr, )
60 /* Bitmask modifiers */
62 #define __NOT(x) (~(x))
65 * test_and_set_bit - Set a bit and return its old value
67 * @addr: Address to count from
69 * This operation may be reordered on other architectures than x86.
71 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
73 return __test_and_op_bit(or, __NOP, nr, addr);
77 * test_and_clear_bit - Clear a bit and return its old value
79 * @addr: Address to count from
81 * This operation can be reordered on other architectures other than x86.
83 static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
85 return __test_and_op_bit(and, __NOT, nr, addr);
89 * test_and_change_bit - Change a bit and return its old value
91 * @addr: Address to count from
93 * This operation is atomic and cannot be reordered.
94 * It also implies a memory barrier.
96 static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
98 return __test_and_op_bit(xor, __NOP, nr, addr);
102 * set_bit - Atomically set a bit in memory
103 * @nr: the bit to set
104 * @addr: the address to start counting from
106 * Note: there are no guarantees that this function will not be reordered
107 * on non x86 architectures, so if you are writing portable code,
108 * make sure not to rely on its reordering guarantees.
110 * Note that @nr may be almost arbitrarily large; this function is not
111 * restricted to acting on a single-word quantity.
113 static inline void set_bit(int nr, volatile unsigned long *addr)
115 __op_bit(or, __NOP, nr, addr);
119 * clear_bit - Clears a bit in memory
121 * @addr: Address to start counting from
123 * Note: there are no guarantees that this function will not be reordered
124 * on non x86 architectures, so if you are writing portable code,
125 * make sure not to rely on its reordering guarantees.
127 static inline void clear_bit(int nr, volatile unsigned long *addr)
129 __op_bit(and, __NOT, nr, addr);
133 * change_bit - Toggle a bit in memory
135 * @addr: Address to start counting from
137 * change_bit() may be reordered on other architectures than x86.
138 * Note that @nr may be almost arbitrarily large; this function is not
139 * restricted to acting on a single-word quantity.
141 static inline void change_bit(int nr, volatile unsigned long *addr)
143 __op_bit(xor, __NOP, nr, addr);
147 * test_and_set_bit_lock - Set a bit and return its old value, for lock
149 * @addr: Address to count from
151 * This operation is atomic and provides acquire barrier semantics.
152 * It can be used to implement bit locks.
154 static inline int test_and_set_bit_lock(
155 unsigned long nr, volatile unsigned long *addr)
157 return __test_and_op_bit_ord(or, __NOP, nr, addr, .aq);
161 * clear_bit_unlock - Clear a bit in memory, for unlock
162 * @nr: the bit to set
163 * @addr: the address to start counting from
165 * This operation is atomic and provides release barrier semantics.
167 static inline void clear_bit_unlock(
168 unsigned long nr, volatile unsigned long *addr)
170 __op_bit_ord(and, __NOT, nr, addr, .rl);
174 * __clear_bit_unlock - Clear a bit in memory, for unlock
175 * @nr: the bit to set
176 * @addr: the address to start counting from
178 * This operation is like clear_bit_unlock, however it is not atomic.
179 * It does provide release barrier semantics so it can be used to unlock
180 * a bit lock, however it would only be used if no other CPU can modify
181 * any bits in the memory until the lock is released (a good example is
182 * if the bit lock itself protects access to the other bits in the word).
184 * On RISC-V systems there seems to be no benefit to taking advantage of the
185 * non-atomic property here: it's a lot more instructions and we still have to
186 * provide release semantics anyway.
188 static inline void __clear_bit_unlock(
189 unsigned long nr, volatile unsigned long *addr)
191 clear_bit_unlock(nr, addr);
194 #undef __test_and_op_bit
200 #include <asm-generic/bitops/non-atomic.h>
201 #include <asm-generic/bitops/le.h>
202 #include <asm-generic/bitops/ext2-atomic.h>
204 #endif /* _ASM_RISCV_BITOPS_H */