1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2016,2017 IBM Corporation.
6 #define pr_fmt(fmt) "xive: " fmt
8 #include <linux/types.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
25 #include <asm/errno.h>
27 #include <asm/xive-regs.h>
28 #include <asm/hvcall.h>
30 #include "xive-internal.h"
32 static u32 xive_queue_shift;
34 struct xive_irq_bitmap {
35 unsigned long *bitmap;
39 struct list_head list;
42 static LIST_HEAD(xive_irq_bitmaps);
44 static int xive_irq_bitmap_add(int base, int count)
46 struct xive_irq_bitmap *xibm;
48 xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
52 spin_lock_init(&xibm->lock);
55 xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
60 list_add(&xibm->list, &xive_irq_bitmaps);
62 pr_info("Using IRQ range [%x-%x]", xibm->base,
63 xibm->base + xibm->count - 1);
67 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
71 irq = find_first_zero_bit(xibm->bitmap, xibm->count);
72 if (irq != xibm->count) {
73 set_bit(irq, xibm->bitmap);
82 static int xive_irq_bitmap_alloc(void)
84 struct xive_irq_bitmap *xibm;
88 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
89 spin_lock_irqsave(&xibm->lock, flags);
90 irq = __xive_irq_bitmap_alloc(xibm);
91 spin_unlock_irqrestore(&xibm->lock, flags);
98 static void xive_irq_bitmap_free(int irq)
101 struct xive_irq_bitmap *xibm;
103 list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
104 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
105 spin_lock_irqsave(&xibm->lock, flags);
106 clear_bit(irq - xibm->base, xibm->bitmap);
107 spin_unlock_irqrestore(&xibm->lock, flags);
114 /* Based on the similar routines in RTAS */
115 static unsigned int plpar_busy_delay_time(long rc)
119 if (H_IS_LONG_BUSY(rc)) {
120 ms = get_longbusy_msecs(rc);
121 } else if (rc == H_BUSY) {
122 ms = 10; /* seems appropriate for XIVE hcalls */
128 static unsigned int plpar_busy_delay(int rc)
132 ms = plpar_busy_delay_time(rc);
140 * Note: this call has a partition wide scope and can take a while to
141 * complete. If it returns H_LONG_BUSY_* it should be retried
144 static long plpar_int_reset(unsigned long flags)
149 rc = plpar_hcall_norets(H_INT_RESET, flags);
150 } while (plpar_busy_delay(rc));
153 pr_err("H_INT_RESET failed %ld\n", rc);
158 static long plpar_int_get_source_info(unsigned long flags,
160 unsigned long *src_flags,
161 unsigned long *eoi_page,
162 unsigned long *trig_page,
163 unsigned long *esb_shift)
165 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
169 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
170 } while (plpar_busy_delay(rc));
173 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
177 *src_flags = retbuf[0];
178 *eoi_page = retbuf[1];
179 *trig_page = retbuf[2];
180 *esb_shift = retbuf[3];
182 pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
183 retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
188 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
189 #define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
191 static long plpar_int_set_source_config(unsigned long flags,
193 unsigned long target,
195 unsigned long sw_irq)
200 pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
201 flags, lisn, target, prio, sw_irq);
205 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
206 target, prio, sw_irq);
207 } while (plpar_busy_delay(rc));
210 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
211 lisn, target, prio, rc);
218 static long plpar_int_get_source_config(unsigned long flags,
220 unsigned long *target,
222 unsigned long *sw_irq)
224 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
227 pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
230 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
231 target, prio, sw_irq);
232 } while (plpar_busy_delay(rc));
235 pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
244 pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
245 retbuf[0], retbuf[1], retbuf[2]);
250 static long plpar_int_get_queue_info(unsigned long flags,
251 unsigned long target,
252 unsigned long priority,
253 unsigned long *esn_page,
254 unsigned long *esn_size)
256 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
260 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
262 } while (plpar_busy_delay(rc));
265 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
266 target, priority, rc);
270 *esn_page = retbuf[0];
271 *esn_size = retbuf[1];
273 pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
274 retbuf[0], retbuf[1]);
279 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
281 static long plpar_int_set_queue_config(unsigned long flags,
282 unsigned long target,
283 unsigned long priority,
289 pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
290 flags, target, priority, qpage, qsize);
293 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
294 priority, qpage, qsize);
295 } while (plpar_busy_delay(rc));
298 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
299 target, priority, qpage, rc);
306 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
311 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
312 } while (plpar_busy_delay(rc));
315 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
322 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
324 static long plpar_int_esb(unsigned long flags,
326 unsigned long offset,
327 unsigned long in_data,
328 unsigned long *out_data)
330 unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
333 pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
334 flags, lisn, offset, in_data);
337 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
339 } while (plpar_busy_delay(rc));
342 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
347 *out_data = retbuf[0];
352 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
354 unsigned long read_data;
357 rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
358 lisn, offset, data, &read_data);
362 return write ? 0 : read_data;
365 #define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
366 #define XIVE_SRC_LSI (1ull << (63 - 61))
367 #define XIVE_SRC_TRIGGER (1ull << (63 - 62))
368 #define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
370 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
374 unsigned long eoi_page;
375 unsigned long trig_page;
376 unsigned long esb_shift;
378 memset(data, 0, sizeof(*data));
380 rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
385 if (flags & XIVE_SRC_H_INT_ESB)
386 data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
387 if (flags & XIVE_SRC_STORE_EOI)
388 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
389 if (flags & XIVE_SRC_LSI)
390 data->flags |= XIVE_IRQ_FLAG_LSI;
391 data->eoi_page = eoi_page;
392 data->esb_shift = esb_shift;
393 data->trig_page = trig_page;
395 data->hw_irq = hw_irq;
398 * No chip-id for the sPAPR backend. This has an impact how we
399 * pick a target. See xive_pick_irq_target().
401 data->src_chip = XIVE_INVALID_CHIP_ID;
404 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
405 * be used for interrupt management. Skip the remapping of the
406 * ESB pages which are not available.
408 if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
411 data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
412 if (!data->eoi_mmio) {
413 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
417 /* Full function page supports trigger */
418 if (flags & XIVE_SRC_TRIGGER) {
419 data->trig_mmio = data->eoi_mmio;
423 data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
424 if (!data->trig_mmio) {
425 iounmap(data->eoi_mmio);
426 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
432 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
436 rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
439 return rc == 0 ? 0 : -ENXIO;
442 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
446 unsigned long h_target;
447 unsigned long h_prio;
448 unsigned long h_sw_irq;
450 rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
457 return rc == 0 ? 0 : -ENXIO;
460 /* This can be called multiple time to change a queue configuration */
461 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
462 __be32 *qpage, u32 order)
465 unsigned long esn_page;
466 unsigned long esn_size;
467 u64 flags, qpage_phys;
469 /* If there's an actual queue page, clean it */
473 qpage_phys = __pa(qpage);
478 /* Initialize the rest of the fields */
479 q->msk = order ? ((1u << (order - 2)) - 1) : 0;
483 rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
485 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
491 /* TODO: add support for the notification page */
492 q->eoi_phys = esn_page;
494 /* Default is to always notify */
495 flags = XIVE_EQ_ALWAYS_NOTIFY;
497 /* Configure and enable the queue in HW */
498 rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
500 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
510 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
513 struct xive_q *q = &xc->queue[prio];
516 qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
518 return PTR_ERR(qpage);
520 return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
521 q, prio, qpage, xive_queue_shift);
524 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
527 struct xive_q *q = &xc->queue[prio];
528 unsigned int alloc_order;
530 int hw_cpu = get_hard_smp_processor_id(cpu);
532 rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
534 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
537 alloc_order = xive_alloc_order(xive_queue_shift);
538 free_pages((unsigned long)q->qpage, alloc_order);
542 static bool xive_spapr_match(struct device_node *node)
544 /* Ignore cascaded controllers for the moment */
549 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
551 int irq = xive_irq_bitmap_alloc();
554 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
562 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
564 if (xc->hw_ipi == XIVE_BAD_IRQ)
567 xive_irq_bitmap_free(xc->hw_ipi);
568 xc->hw_ipi = XIVE_BAD_IRQ;
570 #endif /* CONFIG_SMP */
572 static void xive_spapr_shutdown(void)
578 * Perform an "ack" cycle on the current thread. Grab the pending
579 * active priorities and update the CPPR to the most favored one.
581 static void xive_spapr_update_pending(struct xive_cpu *xc)
587 * Perform the "Acknowledge O/S to Register" cycle.
589 * Let's speedup the access to the TIMA using the raw I/O
590 * accessor as we don't need the synchronisation routine of
591 * the higher level ones
593 ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
595 /* Synchronize subsequent queue accesses */
599 * Grab the CPPR and the "NSR" field which indicates the source
600 * of the interrupt (if any)
605 if (nsr & TM_QW1_NSR_EO) {
608 /* Mark the priority pending */
609 xc->pending_prio |= 1 << cppr;
612 * A new interrupt should never have a CPPR less favored
613 * than our current one.
615 if (cppr >= xc->cppr)
616 pr_err("CPU %d odd ack CPPR, got %d at %d\n",
617 smp_processor_id(), cppr, xc->cppr);
619 /* Update our idea of what the CPPR is */
624 static void xive_spapr_eoi(u32 hw_irq)
629 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
631 /* Only some debug on the TIMA settings */
632 pr_debug("(HW value: %08x %08x %08x)\n",
633 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
634 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
635 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
638 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
643 static void xive_spapr_sync_source(u32 hw_irq)
645 /* Specs are unclear on what this is doing */
646 plpar_int_sync(0, hw_irq);
649 static const struct xive_ops xive_spapr_ops = {
650 .populate_irq_data = xive_spapr_populate_irq_data,
651 .configure_irq = xive_spapr_configure_irq,
652 .get_irq_config = xive_spapr_get_irq_config,
653 .setup_queue = xive_spapr_setup_queue,
654 .cleanup_queue = xive_spapr_cleanup_queue,
655 .match = xive_spapr_match,
656 .shutdown = xive_spapr_shutdown,
657 .update_pending = xive_spapr_update_pending,
658 .eoi = xive_spapr_eoi,
659 .setup_cpu = xive_spapr_setup_cpu,
660 .teardown_cpu = xive_spapr_teardown_cpu,
661 .sync_source = xive_spapr_sync_source,
662 .esb_rw = xive_spapr_esb_rw,
664 .get_ipi = xive_spapr_get_ipi,
665 .put_ipi = xive_spapr_put_ipi,
666 #endif /* CONFIG_SMP */
671 * get max priority from "/ibm,plat-res-int-priorities"
673 static bool xive_get_max_prio(u8 *max_prio)
675 struct device_node *rootdn;
680 rootdn = of_find_node_by_path("/");
682 pr_err("not root node found !\n");
686 reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
689 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
693 if (len % (2 * sizeof(u32)) != 0) {
694 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
698 /* HW supports priorities in the range [0-7] and 0xFF is a
699 * wildcard priority used to mask. We scan the ranges reserved
700 * by the hypervisor to find the lowest priority we can use.
703 for (prio = 0; prio < 8; prio++) {
707 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
708 int base = be32_to_cpu(reg[2 * i]);
709 int range = be32_to_cpu(reg[2 * i + 1]);
711 if (prio >= base && prio < base + range)
720 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
728 static const u8 *get_vec5_feature(unsigned int index)
730 unsigned long root, chosen;
734 root = of_get_flat_dt_root();
735 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
736 if (chosen == -FDT_ERR_NOTFOUND)
739 vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
749 static bool xive_spapr_disabled(void)
753 vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
757 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
759 case OV5_FEAT(OV5_XIVE_EITHER):
760 case OV5_FEAT(OV5_XIVE_LEGACY):
762 case OV5_FEAT(OV5_XIVE_EXPLOIT):
763 /* Hypervisor only supports XIVE */
764 if (xive_cmdline_disabled)
765 pr_warn("WARNING: Ignoring cmdline option xive=off\n");
768 pr_warn("%s: Unknown xive support option: 0x%x\n",
774 return xive_cmdline_disabled;
777 bool __init xive_spapr_init(void)
779 struct device_node *np;
782 struct property *prop;
789 if (xive_spapr_disabled())
792 pr_devel("%s()\n", __func__);
793 np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
795 pr_devel("not found !\n");
798 pr_devel("Found %s\n", np->full_name);
800 /* Resource 1 is the OS ring TIMA */
801 if (of_address_to_resource(np, 1, &r)) {
802 pr_err("Failed to get thread mgmnt area resource\n");
805 tima = ioremap(r.start, resource_size(&r));
807 pr_err("Failed to map thread mgmnt area\n");
811 if (!xive_get_max_prio(&max_prio))
814 /* Feed the IRQ number allocator with the ranges given in the DT */
815 reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
817 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
821 if (len % (2 * sizeof(u32)) != 0) {
822 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
826 for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
827 xive_irq_bitmap_add(be32_to_cpu(reg[0]),
828 be32_to_cpu(reg[1]));
830 /* Iterate the EQ sizes and pick one */
831 of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
832 xive_queue_shift = val;
833 if (val == PAGE_SHIFT)
837 /* Initialize XIVE core with our backend */
838 if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
841 pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));