arch/powerpc/sysdev/xive/spapr.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/smp.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/init.h>
  17 #include <linux/of.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/cpumask.h>
  21 #include <linux/mm.h>
  22
  23 #include <asm/prom.h>
  24 #include <asm/io.h>
  25 #include <asm/smp.h>
  26 #include <asm/irq.h>
  27 #include <asm/errno.h>
  28 #include <asm/xive.h>
  29 #include <asm/xive-regs.h>
  30 #include <asm/hvcall.h>
  31
  32 #include "xive-internal.h"
  33
  34 static u32 xive_queue_shift;
  35
  36 struct xive_irq_bitmap {
  37         unsigned long           *bitmap;
  38         unsigned int            base;
  39         unsigned int            count;
  40         spinlock_t              lock;
  41         struct list_head        list;
  42 };
  43
  44 static LIST_HEAD(xive_irq_bitmaps);
  45
  46 static int xive_irq_bitmap_add(int base, int count)
  47 {
  48         struct xive_irq_bitmap *xibm;
  49
  50         xibm = kzalloc(sizeof(*xibm), GFP_ATOMIC);
  51         if (!xibm)
  52                 return -ENOMEM;
  53
  54         spin_lock_init(&xibm->lock);
  55         xibm->base = base;
  56         xibm->count = count;
  57         xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
  58         list_add(&xibm->list, &xive_irq_bitmaps);
  59
  60         pr_info("Using IRQ range [%x-%x]", xibm->base,
  61                 xibm->base + xibm->count - 1);
  62         return 0;
  63 }
  64
  65 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
  66 {
  67         int irq;
  68
  69         irq = find_first_zero_bit(xibm->bitmap, xibm->count);
  70         if (irq != xibm->count) {
  71                 set_bit(irq, xibm->bitmap);
  72                 irq += xibm->base;
  73         } else {
  74                 irq = -ENOMEM;
  75         }
  76
  77         return irq;
  78 }
  79
  80 static int xive_irq_bitmap_alloc(void)
  81 {
  82         struct xive_irq_bitmap *xibm;
  83         unsigned long flags;
  84         int irq = -ENOENT;
  85
  86         list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
  87                 spin_lock_irqsave(&xibm->lock, flags);
  88                 irq = __xive_irq_bitmap_alloc(xibm);
  89                 spin_unlock_irqrestore(&xibm->lock, flags);
  90                 if (irq >= 0)
  91                         break;
  92         }
  93         return irq;
  94 }
  95
  96 static void xive_irq_bitmap_free(int irq)
  97 {
  98         unsigned long flags;
  99         struct xive_irq_bitmap *xibm;
 100
 101         list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
 102                 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
 103                         spin_lock_irqsave(&xibm->lock, flags);
 104                         clear_bit(irq - xibm->base, xibm->bitmap);
 105                         spin_unlock_irqrestore(&xibm->lock, flags);
 106                         break;
 107                 }
 108         }
 109 }
 110
 111 static long plpar_int_get_source_info(unsigned long flags,
 112                                       unsigned long lisn,
 113                                       unsigned long *src_flags,
 114                                       unsigned long *eoi_page,
 115                                       unsigned long *trig_page,
 116                                       unsigned long *esb_shift)
 117 {
 118         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 119         long rc;
 120
 121         rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
 122         if (rc) {
 123                 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
 124                 return rc;
 125         }
 126
 127         *src_flags = retbuf[0];
 128         *eoi_page  = retbuf[1];
 129         *trig_page = retbuf[2];
 130         *esb_shift = retbuf[3];
 131
 132         pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
 133                 retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
 134
 135         return 0;
 136 }
 137
 138 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
 139 #define XIVE_SRC_MASK     (1ull << (63 - 63)) /* unused */
 140
 141 static long plpar_int_set_source_config(unsigned long flags,
 142                                         unsigned long lisn,
 143                                         unsigned long target,
 144                                         unsigned long prio,
 145                                         unsigned long sw_irq)
 146 {
 147         long rc;
 148
 149
 150         pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
 151                 flags, lisn, target, prio, sw_irq);
 152
 153
 154         rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
 155                                 target, prio, sw_irq);
 156         if (rc) {
 157                 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
 158                        lisn, target, prio, rc);
 159                 return rc;
 160         }
 161
 162         return 0;
 163 }
 164
 165 static long plpar_int_get_queue_info(unsigned long flags,
 166                                      unsigned long target,
 167                                      unsigned long priority,
 168                                      unsigned long *esn_page,
 169                                      unsigned long *esn_size)
 170 {
 171         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 172         long rc;
 173
 174         rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target, priority);
 175         if (rc) {
 176                 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
 177                        target, priority, rc);
 178                 return rc;
 179         }
 180
 181         *esn_page = retbuf[0];
 182         *esn_size = retbuf[1];
 183
 184         pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
 185                 retbuf[0], retbuf[1]);
 186
 187         return 0;
 188 }
 189
 190 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
 191
 192 static long plpar_int_set_queue_config(unsigned long flags,
 193                                        unsigned long target,
 194                                        unsigned long priority,
 195                                        unsigned long qpage,
 196                                        unsigned long qsize)
 197 {
 198         long rc;
 199
 200         pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
 201                 flags,  target, priority, qpage, qsize);
 202
 203         rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
 204                                 priority, qpage, qsize);
 205         if (rc) {
 206                 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
 207                        target, priority, qpage, rc);
 208                 return  rc;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
 215 {
 216         long rc;
 217
 218         rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
 219         if (rc) {
 220                 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
 221                 return  rc;
 222         }
 223
 224         return 0;
 225 }
 226
 227 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
 228
 229 static long plpar_int_esb(unsigned long flags,
 230                           unsigned long lisn,
 231                           unsigned long offset,
 232                           unsigned long in_data,
 233                           unsigned long *out_data)
 234 {
 235         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 236         long rc;
 237
 238         pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
 239                 flags,  lisn, offset, in_data);
 240
 241         rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);
 242         if (rc) {
 243                 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
 244                        lisn, offset, rc);
 245                 return  rc;
 246         }
 247
 248         *out_data = retbuf[0];
 249
 250         return 0;
 251 }
 252
 253 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
 254 {
 255         unsigned long read_data;
 256         long rc;
 257
 258         rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
 259                            lisn, offset, data, &read_data);
 260         if (rc)
 261                 return -1;
 262
 263         return write ? 0 : read_data;
 264 }
 265
 266 #define XIVE_SRC_H_INT_ESB     (1ull << (63 - 60))
 267 #define XIVE_SRC_LSI           (1ull << (63 - 61))
 268 #define XIVE_SRC_TRIGGER       (1ull << (63 - 62))
 269 #define XIVE_SRC_STORE_EOI     (1ull << (63 - 63))
 270
 271 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
 272 {
 273         long rc;
 274         unsigned long flags;
 275         unsigned long eoi_page;
 276         unsigned long trig_page;
 277         unsigned long esb_shift;
 278
 279         memset(data, 0, sizeof(*data));
 280
 281         rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
 282                                        &esb_shift);
 283         if (rc)
 284                 return  -EINVAL;
 285
 286         if (flags & XIVE_SRC_H_INT_ESB)
 287                 data->flags  |= XIVE_IRQ_FLAG_H_INT_ESB;
 288         if (flags & XIVE_SRC_STORE_EOI)
 289                 data->flags  |= XIVE_IRQ_FLAG_STORE_EOI;
 290         if (flags & XIVE_SRC_LSI)
 291                 data->flags  |= XIVE_IRQ_FLAG_LSI;
 292         data->eoi_page  = eoi_page;
 293         data->esb_shift = esb_shift;
 294         data->trig_page = trig_page;
 295
 296         data->hw_irq = hw_irq;
 297
 298         /*
 299          * No chip-id for the sPAPR backend. This has an impact how we
 300          * pick a target. See xive_pick_irq_target().
 301          */
 302         data->src_chip = XIVE_INVALID_CHIP_ID;
 303
 304         /*
 305          * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
 306          * be used for interrupt management. Skip the remapping of the
 307          * ESB pages which are not available.
 308          */
 309         if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
 310                 return 0;
 311
 312         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
 313         if (!data->eoi_mmio) {
 314                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
 315                 return -ENOMEM;
 316         }
 317
 318         /* Full function page supports trigger */
 319         if (flags & XIVE_SRC_TRIGGER) {
 320                 data->trig_mmio = data->eoi_mmio;
 321                 return 0;
 322         }
 323
 324         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
 325         if (!data->trig_mmio) {
 326                 iounmap(data->eoi_mmio);
 327                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
 328                 return -ENOMEM;
 329         }
 330         return 0;
 331 }
 332
 333 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 334 {
 335         long rc;
 336
 337         rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
 338                                          prio, sw_irq);
 339
 340         return rc == 0 ? 0 : -ENXIO;
 341 }
 342
 343 /* This can be called multiple time to change a queue configuration */
 344 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
 345                                    __be32 *qpage, u32 order)
 346 {
 347         s64 rc = 0;
 348         unsigned long esn_page;
 349         unsigned long esn_size;
 350         u64 flags, qpage_phys;
 351
 352         /* If there's an actual queue page, clean it */
 353         if (order) {
 354                 if (WARN_ON(!qpage))
 355                         return -EINVAL;
 356                 qpage_phys = __pa(qpage);
 357         } else {
 358                 qpage_phys = 0;
 359         }
 360
 361         /* Initialize the rest of the fields */
 362         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 363         q->idx = 0;
 364         q->toggle = 0;
 365
 366         rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
 367         if (rc) {
 368                 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
 369                        target, prio);
 370                 rc = -EIO;
 371                 goto fail;
 372         }
 373
 374         /* TODO: add support for the notification page */
 375         q->eoi_phys = esn_page;
 376
 377         /* Default is to always notify */
 378         flags = XIVE_EQ_ALWAYS_NOTIFY;
 379
 380         /* Configure and enable the queue in HW */
 381         rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
 382         if (rc) {
 383                 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
 384                        target, prio);
 385                 rc = -EIO;
 386         } else {
 387                 q->qpage = qpage;
 388         }
 389 fail:
 390         return rc;
 391 }
 392
 393 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
 394                                   u8 prio)
 395 {
 396         struct xive_q *q = &xc->queue[prio];
 397         __be32 *qpage;
 398
 399         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 400         if (IS_ERR(qpage))
 401                 return PTR_ERR(qpage);
 402
 403         return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
 404                                           q, prio, qpage, xive_queue_shift);
 405 }
 406
 407 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
 408                                   u8 prio)
 409 {
 410         struct xive_q *q = &xc->queue[prio];
 411         unsigned int alloc_order;
 412         long rc;
 413         int hw_cpu = get_hard_smp_processor_id(cpu);
 414
 415         rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
 416         if (rc)
 417                 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
 418                        hw_cpu, prio);
 419
 420         alloc_order = xive_alloc_order(xive_queue_shift);
 421         free_pages((unsigned long)q->qpage, alloc_order);
 422         q->qpage = NULL;
 423 }
 424
 425 static bool xive_spapr_match(struct device_node *node)
 426 {
 427         /* Ignore cascaded controllers for the moment */
 428         return 1;
 429 }
 430
 431 #ifdef CONFIG_SMP
 432 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 433 {
 434         int irq = xive_irq_bitmap_alloc();
 435
 436         if (irq < 0) {
 437                 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 438                 return -ENXIO;
 439         }
 440
 441         xc->hw_ipi = irq;
 442         return 0;
 443 }
 444
 445 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 446 {
 447         if (xc->hw_ipi == XIVE_BAD_IRQ)
 448                 return;
 449
 450         xive_irq_bitmap_free(xc->hw_ipi);
 451         xc->hw_ipi = XIVE_BAD_IRQ;
 452 }
 453 #endif /* CONFIG_SMP */
 454
 455 static void xive_spapr_shutdown(void)
 456 {
 457         long rc;
 458
 459         rc = plpar_hcall_norets(H_INT_RESET, 0);
 460         if (rc)
 461                 pr_err("H_INT_RESET failed %ld\n", rc);
 462 }
 463
 464 /*
 465  * Perform an "ack" cycle on the current thread. Grab the pending
 466  * active priorities and update the CPPR to the most favored one.
 467  */
 468 static void xive_spapr_update_pending(struct xive_cpu *xc)
 469 {
 470         u8 nsr, cppr;
 471         u16 ack;
 472
 473         /*
 474          * Perform the "Acknowledge O/S to Register" cycle.
 475          *
 476          * Let's speedup the access to the TIMA using the raw I/O
 477          * accessor as we don't need the synchronisation routine of
 478          * the higher level ones
 479          */
 480         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
 481
 482         /* Synchronize subsequent queue accesses */
 483         mb();
 484
 485         /*
 486          * Grab the CPPR and the "NSR" field which indicates the source
 487          * of the interrupt (if any)
 488          */
 489         cppr = ack & 0xff;
 490         nsr = ack >> 8;
 491
 492         if (nsr & TM_QW1_NSR_EO) {
 493                 if (cppr == 0xff)
 494                         return;
 495                 /* Mark the priority pending */
 496                 xc->pending_prio |= 1 << cppr;
 497
 498                 /*
 499                  * A new interrupt should never have a CPPR less favored
 500                  * than our current one.
 501                  */
 502                 if (cppr >= xc->cppr)
 503                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 504                                smp_processor_id(), cppr, xc->cppr);
 505
 506                 /* Update our idea of what the CPPR is */
 507                 xc->cppr = cppr;
 508         }
 509 }
 510
 511 static void xive_spapr_eoi(u32 hw_irq)
 512 {
 513         /* Not used */;
 514 }
 515
 516 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 517 {
 518         /* Only some debug on the TIMA settings */
 519         pr_debug("(HW value: %08x %08x %08x)\n",
 520                  in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
 521                  in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
 522                  in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
 523 }
 524
 525 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 526 {
 527         /* Nothing to do */;
 528 }
 529
 530 static void xive_spapr_sync_source(u32 hw_irq)
 531 {
 532         /* Specs are unclear on what this is doing */
 533         plpar_int_sync(0, hw_irq);
 534 }
 535
 536 static const struct xive_ops xive_spapr_ops = {
 537         .populate_irq_data      = xive_spapr_populate_irq_data,
 538         .configure_irq          = xive_spapr_configure_irq,
 539         .setup_queue            = xive_spapr_setup_queue,
 540         .cleanup_queue          = xive_spapr_cleanup_queue,
 541         .match                  = xive_spapr_match,
 542         .shutdown               = xive_spapr_shutdown,
 543         .update_pending         = xive_spapr_update_pending,
 544         .eoi                    = xive_spapr_eoi,
 545         .setup_cpu              = xive_spapr_setup_cpu,
 546         .teardown_cpu           = xive_spapr_teardown_cpu,
 547         .sync_source            = xive_spapr_sync_source,
 548         .esb_rw                 = xive_spapr_esb_rw,
 549 #ifdef CONFIG_SMP
 550         .get_ipi                = xive_spapr_get_ipi,
 551         .put_ipi                = xive_spapr_put_ipi,
 552 #endif /* CONFIG_SMP */
 553         .name                   = "spapr",
 554 };
 555
 556 /*
 557  * get max priority from "/ibm,plat-res-int-priorities"
 558  */
 559 static bool xive_get_max_prio(u8 *max_prio)
 560 {
 561         struct device_node *rootdn;
 562         const __be32 *reg;
 563         u32 len;
 564         int prio, found;
 565
 566         rootdn = of_find_node_by_path("/");
 567         if (!rootdn) {
 568                 pr_err("not root node found !\n");
 569                 return false;
 570         }
 571
 572         reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
 573         of_node_put(rootdn);
 574         if (!reg) {
 575                 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
 576                 return false;
 577         }
 578
 579         if (len % (2 * sizeof(u32)) != 0) {
 580                 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
 581                 return false;
 582         }
 583
 584         /* HW supports priorities in the range [0-7] and 0xFF is a
 585          * wildcard priority used to mask. We scan the ranges reserved
 586          * by the hypervisor to find the lowest priority we can use.
 587          */
 588         found = 0xFF;
 589         for (prio = 0; prio < 8; prio++) {
 590                 int reserved = 0;
 591                 int i;
 592
 593                 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
 594                         int base  = be32_to_cpu(reg[2 * i]);
 595                         int range = be32_to_cpu(reg[2 * i + 1]);
 596
 597                         if (prio >= base && prio < base + range)
 598                                 reserved++;
 599                 }
 600
 601                 if (!reserved)
 602                         found = prio;
 603         }
 604
 605         if (found == 0xFF) {
 606                 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
 607                 return false;
 608         }
 609
 610         *max_prio = found;
 611         return true;
 612 }
 613
 614 bool __init xive_spapr_init(void)
 615 {
 616         struct device_node *np;
 617         struct resource r;
 618         void __iomem *tima;
 619         struct property *prop;
 620         u8 max_prio;
 621         u32 val;
 622         u32 len;
 623         const __be32 *reg;
 624         int i;
 625
 626         if (xive_cmdline_disabled)
 627                 return false;
 628
 629         pr_devel("%s()\n", __func__);
 630         np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
 631         if (!np) {
 632                 pr_devel("not found !\n");
 633                 return false;
 634         }
 635         pr_devel("Found %s\n", np->full_name);
 636
 637         /* Resource 1 is the OS ring TIMA */
 638         if (of_address_to_resource(np, 1, &r)) {
 639                 pr_err("Failed to get thread mgmnt area resource\n");
 640                 return false;
 641         }
 642         tima = ioremap(r.start, resource_size(&r));
 643         if (!tima) {
 644                 pr_err("Failed to map thread mgmnt area\n");
 645                 return false;
 646         }
 647
 648         if (!xive_get_max_prio(&max_prio))
 649                 return false;
 650
 651         /* Feed the IRQ number allocator with the ranges given in the DT */
 652         reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
 653         if (!reg) {
 654                 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
 655                 return false;
 656         }
 657
 658         if (len % (2 * sizeof(u32)) != 0) {
 659                 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
 660                 return false;
 661         }
 662
 663         for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
 664                 xive_irq_bitmap_add(be32_to_cpu(reg[0]),
 665                                     be32_to_cpu(reg[1]));
 666
 667         /* Iterate the EQ sizes and pick one */
 668         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
 669                 xive_queue_shift = val;
 670                 if (val == PAGE_SHIFT)
 671                         break;
 672         }
 673
 674         /* Initialize XIVE core with our backend */
 675         if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
 676                 return false;
 677
 678         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 679         return true;
 680 }