arch/powerpc/sysdev/xive/native.c

   1 /*
   2  * Copyright 2016,2017 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #define pr_fmt(fmt) "xive: " fmt
  11
  12 #include <linux/types.h>
  13 #include <linux/irq.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/smp.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/init.h>
  19 #include <linux/of.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/mm.h>
  25 #include <linux/kmemleak.h>
  26
  27 #include <asm/prom.h>
  28 #include <asm/io.h>
  29 #include <asm/smp.h>
  30 #include <asm/irq.h>
  31 #include <asm/errno.h>
  32 #include <asm/xive.h>
  33 #include <asm/xive-regs.h>
  34 #include <asm/opal.h>
  35 #include <asm/kvm_ppc.h>
  36
  37 #include "xive-internal.h"
  38
  39
  40 static u32 xive_provision_size;
  41 static u32 *xive_provision_chips;
  42 static u32 xive_provision_chip_count;
  43 static u32 xive_queue_shift;
  44 static u32 xive_pool_vps = XIVE_INVALID_VP;
  45 static struct kmem_cache *xive_provision_cache;
  46
  47 int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
  48 {
  49         __be64 flags, eoi_page, trig_page;
  50         __be32 esb_shift, src_chip;
  51         u64 opal_flags;
  52         s64 rc;
  53
  54         memset(data, 0, sizeof(*data));
  55
  56         rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
  57                                     &esb_shift, &src_chip);
  58         if (rc) {
  59                 pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
  60                        hw_irq, rc);
  61                 return -EINVAL;
  62         }
  63
  64         opal_flags = be64_to_cpu(flags);
  65         if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
  66                 data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
  67         if (opal_flags & OPAL_XIVE_IRQ_LSI)
  68                 data->flags |= XIVE_IRQ_FLAG_LSI;
  69         if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
  70                 data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
  71         if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
  72                 data->flags |= XIVE_IRQ_FLAG_MASK_FW;
  73         if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
  74                 data->flags |= XIVE_IRQ_FLAG_EOI_FW;
  75         data->eoi_page = be64_to_cpu(eoi_page);
  76         data->trig_page = be64_to_cpu(trig_page);
  77         data->esb_shift = be32_to_cpu(esb_shift);
  78         data->src_chip = be32_to_cpu(src_chip);
  79
  80         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
  81         if (!data->eoi_mmio) {
  82                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
  83                 return -ENOMEM;
  84         }
  85
  86         data->hw_irq = hw_irq;
  87
  88         if (!data->trig_page)
  89                 return 0;
  90         if (data->trig_page == data->eoi_page) {
  91                 data->trig_mmio = data->eoi_mmio;
  92                 return 0;
  93         }
  94
  95         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
  96         if (!data->trig_mmio) {
  97                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
  98                 return -ENOMEM;
  99         }
 100         return 0;
 101 }
 102 EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
 103
 104 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 105 {
 106         s64 rc;
 107
 108         for (;;) {
 109                 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
 110                 if (rc != OPAL_BUSY)
 111                         break;
 112                 msleep(1);
 113         }
 114         return rc == 0 ? 0 : -ENXIO;
 115 }
 116 EXPORT_SYMBOL_GPL(xive_native_configure_irq);
 117
 118
 119 /* This can be called multiple time to change a queue configuration */
 120 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 121                                 __be32 *qpage, u32 order, bool can_escalate)
 122 {
 123         s64 rc = 0;
 124         __be64 qeoi_page_be;
 125         __be32 esc_irq_be;
 126         u64 flags, qpage_phys;
 127
 128         /* If there's an actual queue page, clean it */
 129         if (order) {
 130                 if (WARN_ON(!qpage))
 131                         return -EINVAL;
 132                 qpage_phys = __pa(qpage);
 133         } else
 134                 qpage_phys = 0;
 135
 136         /* Initialize the rest of the fields */
 137         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 138         q->idx = 0;
 139         q->toggle = 0;
 140
 141         rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
 142                                       &qeoi_page_be,
 143                                       &esc_irq_be,
 144                                       NULL);
 145         if (rc) {
 146                 pr_err("Error %lld getting queue info prio %d\n", rc, prio);
 147                 rc = -EIO;
 148                 goto fail;
 149         }
 150         q->eoi_phys = be64_to_cpu(qeoi_page_be);
 151
 152         /* Default flags */
 153         flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;
 154
 155         /* Escalation needed ? */
 156         if (can_escalate) {
 157                 q->esc_irq = be32_to_cpu(esc_irq_be);
 158                 flags |= OPAL_XIVE_EQ_ESCALATE;
 159         }
 160
 161         /* Configure and enable the queue in HW */
 162         for (;;) {
 163                 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
 164                 if (rc != OPAL_BUSY)
 165                         break;
 166                 msleep(1);
 167         }
 168         if (rc) {
 169                 pr_err("Error %lld setting queue for prio %d\n", rc, prio);
 170                 rc = -EIO;
 171         } else {
 172                 /*
 173                  * KVM code requires all of the above to be visible before
 174                  * q->qpage is set due to how it manages IPI EOIs
 175                  */
 176                 wmb();
 177                 q->qpage = qpage;
 178         }
 179 fail:
 180         return rc;
 181 }
 182 EXPORT_SYMBOL_GPL(xive_native_configure_queue);
 183
 184 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 185 {
 186         s64 rc;
 187
 188         /* Disable the queue in HW */
 189         for (;;) {
 190                 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
 191                 if (rc != OPAL_BUSY)
 192                         break;
 193                 msleep(1);
 194         }
 195         if (rc)
 196                 pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
 197 }
 198
 199 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
 200 {
 201         __xive_native_disable_queue(vp_id, q, prio);
 202 }
 203 EXPORT_SYMBOL_GPL(xive_native_disable_queue);
 204
 205 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 206 {
 207         struct xive_q *q = &xc->queue[prio];
 208         __be32 *qpage;
 209
 210         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 211         if (IS_ERR(qpage))
 212                 return PTR_ERR(qpage);
 213
 214         return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
 215                                            q, prio, qpage, xive_queue_shift, false);
 216 }
 217
 218 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
 219 {
 220         struct xive_q *q = &xc->queue[prio];
 221         unsigned int alloc_order;
 222
 223         /*
 224          * We use the variant with no iounmap as this is called on exec
 225          * from an IPI and iounmap isn't safe
 226          */
 227         __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
 228         alloc_order = xive_alloc_order(xive_queue_shift);
 229         free_pages((unsigned long)q->qpage, alloc_order);
 230         q->qpage = NULL;
 231 }
 232
 233 static bool xive_native_match(struct device_node *node)
 234 {
 235         return of_device_is_compatible(node, "ibm,opal-xive-vc");
 236 }
 237
 238 static s64 opal_xive_allocate_irq(u32 chip_id)
 239 {
 240         s64 irq = opal_xive_allocate_irq_raw(chip_id);
 241
 242         /*
 243          * Old versions of skiboot can incorrectly return 0xffffffff to
 244          * indicate no space, fix it up here.
 245          */
 246         return irq == 0xffffffff ? OPAL_RESOURCE : irq;
 247 }
 248
 249 #ifdef CONFIG_SMP
 250 static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 251 {
 252         struct device_node *np;
 253         unsigned int chip_id;
 254         s64 irq;
 255
 256         /* Find the chip ID */
 257         np = of_get_cpu_node(cpu, NULL);
 258         if (np) {
 259                 if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
 260                         chip_id = 0;
 261         }
 262
 263         /* Allocate an IPI and populate info about it */
 264         for (;;) {
 265                 irq = opal_xive_allocate_irq(chip_id);
 266                 if (irq == OPAL_BUSY) {
 267                         msleep(1);
 268                         continue;
 269                 }
 270                 if (irq < 0) {
 271                         pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 272                         return -ENXIO;
 273                 }
 274                 xc->hw_ipi = irq;
 275                 break;
 276         }
 277         return 0;
 278 }
 279 #endif /* CONFIG_SMP */
 280
 281 u32 xive_native_alloc_irq(void)
 282 {
 283         s64 rc;
 284
 285         for (;;) {
 286                 rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
 287                 if (rc != OPAL_BUSY)
 288                         break;
 289                 msleep(1);
 290         }
 291         if (rc < 0)
 292                 return 0;
 293         return rc;
 294 }
 295 EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
 296
 297 void xive_native_free_irq(u32 irq)
 298 {
 299         for (;;) {
 300                 s64 rc = opal_xive_free_irq(irq);
 301                 if (rc != OPAL_BUSY)
 302                         break;
 303                 msleep(1);
 304         }
 305 }
 306 EXPORT_SYMBOL_GPL(xive_native_free_irq);
 307
 308 #ifdef CONFIG_SMP
 309 static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 310 {
 311         s64 rc;
 312
 313         /* Free the IPI */
 314         if (xc->hw_ipi == XIVE_BAD_IRQ)
 315                 return;
 316         for (;;) {
 317                 rc = opal_xive_free_irq(xc->hw_ipi);
 318                 if (rc == OPAL_BUSY) {
 319                         msleep(1);
 320                         continue;
 321                 }
 322                 xc->hw_ipi = XIVE_BAD_IRQ;
 323                 break;
 324         }
 325 }
 326 #endif /* CONFIG_SMP */
 327
 328 static void xive_native_shutdown(void)
 329 {
 330         /* Switch the XIVE to emulation mode */
 331         opal_xive_reset(OPAL_XIVE_MODE_EMU);
 332 }
 333
 334 /*
 335  * Perform an "ack" cycle on the current thread, thus
 336  * grabbing the pending active priorities and updating
 337  * the CPPR to the most favored one.
 338  */
 339 static void xive_native_update_pending(struct xive_cpu *xc)
 340 {
 341         u8 he, cppr;
 342         u16 ack;
 343
 344         /* Perform the acknowledge hypervisor to register cycle */
 345         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
 346
 347         /* Synchronize subsequent queue accesses */
 348         mb();
 349
 350         /*
 351          * Grab the CPPR and the "HE" field which indicates the source
 352          * of the hypervisor interrupt (if any)
 353          */
 354         cppr = ack & 0xff;
 355         he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
 356         switch(he) {
 357         case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
 358                 break;
 359         case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
 360                 if (cppr == 0xff)
 361                         return;
 362                 /* Mark the priority pending */
 363                 xc->pending_prio |= 1 << cppr;
 364
 365                 /*
 366                  * A new interrupt should never have a CPPR less favored
 367                  * than our current one.
 368                  */
 369                 if (cppr >= xc->cppr)
 370                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 371                                smp_processor_id(), cppr, xc->cppr);
 372
 373                 /* Update our idea of what the CPPR is */
 374                 xc->cppr = cppr;
 375                 break;
 376         case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
 377         case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
 378                 pr_err("CPU %d got unexpected interrupt type HE=%d\n",
 379                        smp_processor_id(), he);
 380                 return;
 381         }
 382 }
 383
 384 static void xive_native_eoi(u32 hw_irq)
 385 {
 386         /*
 387          * Not normally used except if specific interrupts need
 388          * a workaround on EOI.
 389          */
 390         opal_int_eoi(hw_irq);
 391 }
 392
 393 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 394 {
 395         s64 rc;
 396         u32 vp;
 397         __be64 vp_cam_be;
 398         u64 vp_cam;
 399
 400         if (xive_pool_vps == XIVE_INVALID_VP)
 401                 return;
 402
 403         /* Check if pool VP already active, if it is, pull it */
 404         if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP)
 405                 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 406
 407         /* Enable the pool VP */
 408         vp = xive_pool_vps + cpu;
 409         pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
 410         for (;;) {
 411                 rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
 412                 if (rc != OPAL_BUSY)
 413                         break;
 414                 msleep(1);
 415         }
 416         if (rc) {
 417                 pr_err("Failed to enable pool VP on CPU %d\n", cpu);
 418                 return;
 419         }
 420
 421         /* Grab it's CAM value */
 422         rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
 423         if (rc) {
 424                 pr_err("Failed to get pool VP info CPU %d\n", cpu);
 425                 return;
 426         }
 427         vp_cam = be64_to_cpu(vp_cam_be);
 428
 429         pr_debug("VP CAM = %llx\n", vp_cam);
 430
 431         /* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
 432         pr_debug("(Old HW value: %08x)\n",
 433                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 434         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
 435         out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
 436                  TM_QW2W2_VP | vp_cam);
 437         pr_debug("(New HW value: %08x)\n",
 438                  in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
 439 }
 440
 441 static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 442 {
 443         s64 rc;
 444         u32 vp;
 445
 446         if (xive_pool_vps == XIVE_INVALID_VP)
 447                 return;
 448
 449         /* Pull the pool VP from the CPU */
 450         in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
 451
 452         /* Disable it */
 453         vp = xive_pool_vps + cpu;
 454         for (;;) {
 455                 rc = opal_xive_set_vp_info(vp, 0, 0);
 456                 if (rc != OPAL_BUSY)
 457                         break;
 458                 msleep(1);
 459         }
 460 }
 461
 462 void xive_native_sync_source(u32 hw_irq)
 463 {
 464         opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
 465 }
 466 EXPORT_SYMBOL_GPL(xive_native_sync_source);
 467
 468 static const struct xive_ops xive_native_ops = {
 469         .populate_irq_data      = xive_native_populate_irq_data,
 470         .configure_irq          = xive_native_configure_irq,
 471         .setup_queue            = xive_native_setup_queue,
 472         .cleanup_queue          = xive_native_cleanup_queue,
 473         .match                  = xive_native_match,
 474         .shutdown               = xive_native_shutdown,
 475         .update_pending         = xive_native_update_pending,
 476         .eoi                    = xive_native_eoi,
 477         .setup_cpu              = xive_native_setup_cpu,
 478         .teardown_cpu           = xive_native_teardown_cpu,
 479         .sync_source            = xive_native_sync_source,
 480 #ifdef CONFIG_SMP
 481         .get_ipi                = xive_native_get_ipi,
 482         .put_ipi                = xive_native_put_ipi,
 483 #endif /* CONFIG_SMP */
 484         .name                   = "native",
 485 };
 486
 487 static bool xive_parse_provisioning(struct device_node *np)
 488 {
 489         int rc;
 490
 491         if (of_property_read_u32(np, "ibm,xive-provision-page-size",
 492                                  &xive_provision_size) < 0)
 493                 return true;
 494         rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
 495         if (rc < 0) {
 496                 pr_err("Error %d getting provision chips array\n", rc);
 497                 return false;
 498         }
 499         xive_provision_chip_count = rc;
 500         if (rc == 0)
 501                 return true;
 502
 503         xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
 504                                        GFP_KERNEL);
 505         if (WARN_ON(!xive_provision_chips))
 506                 return false;
 507
 508         rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
 509                                         xive_provision_chips,
 510                                         xive_provision_chip_count);
 511         if (rc < 0) {
 512                 pr_err("Error %d reading provision chips array\n", rc);
 513                 return false;
 514         }
 515
 516         xive_provision_cache = kmem_cache_create("xive-provision",
 517                                                  xive_provision_size,
 518                                                  xive_provision_size,
 519                                                  0, NULL);
 520         if (!xive_provision_cache) {
 521                 pr_err("Failed to allocate provision cache\n");
 522                 return false;
 523         }
 524         return true;
 525 }
 526
 527 static void xive_native_setup_pools(void)
 528 {
 529         /* Allocate a pool big enough */
 530         pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
 531
 532         xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
 533         if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
 534                 pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
 535
 536         pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
 537                  xive_pool_vps, nr_cpu_ids);
 538 }
 539
 540 u32 xive_native_default_eq_shift(void)
 541 {
 542         return xive_queue_shift;
 543 }
 544 EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
 545
 546 bool __init xive_native_init(void)
 547 {
 548         struct device_node *np;
 549         struct resource r;
 550         void __iomem *tima;
 551         struct property *prop;
 552         u8 max_prio = 7;
 553         const __be32 *p;
 554         u32 val, cpu;
 555         s64 rc;
 556
 557         if (xive_cmdline_disabled)
 558                 return false;
 559
 560         pr_devel("xive_native_init()\n");
 561         np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
 562         if (!np) {
 563                 pr_devel("not found !\n");
 564                 return false;
 565         }
 566         pr_devel("Found %pOF\n", np);
 567
 568         /* Resource 1 is HV window */
 569         if (of_address_to_resource(np, 1, &r)) {
 570                 pr_err("Failed to get thread mgmnt area resource\n");
 571                 return false;
 572         }
 573         tima = ioremap(r.start, resource_size(&r));
 574         if (!tima) {
 575                 pr_err("Failed to map thread mgmnt area\n");
 576                 return false;
 577         }
 578
 579         /* Read number of priorities */
 580         if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
 581                 max_prio = val - 1;
 582
 583         /* Iterate the EQ sizes and pick one */
 584         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
 585                 xive_queue_shift = val;
 586                 if (val == PAGE_SHIFT)
 587                         break;
 588         }
 589
 590         /* Configure Thread Management areas for KVM */
 591         for_each_possible_cpu(cpu)
 592                 kvmppc_set_xive_tima(cpu, r.start, tima);
 593
 594         /* Grab size of provisionning pages */
 595         xive_parse_provisioning(np);
 596
 597         /* Switch the XIVE to exploitation mode */
 598         rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
 599         if (rc) {
 600                 pr_err("Switch to exploitation mode failed with error %lld\n", rc);
 601                 return false;
 602         }
 603
 604         /* Setup some dummy HV pool VPs */
 605         xive_native_setup_pools();
 606
 607         /* Initialize XIVE core with our backend */
 608         if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
 609                             max_prio)) {
 610                 opal_xive_reset(OPAL_XIVE_MODE_EMU);
 611                 return false;
 612         }
 613         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 614         return true;
 615 }
 616
 617 static bool xive_native_provision_pages(void)
 618 {
 619         u32 i;
 620         void *p;
 621
 622         for (i = 0; i < xive_provision_chip_count; i++) {
 623                 u32 chip = xive_provision_chips[i];
 624
 625                 /*
 626                  * XXX TODO: Try to make the allocation local to the node where
 627                  * the chip resides.
 628                  */
 629                 p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
 630                 if (!p) {
 631                         pr_err("Failed to allocate provisioning page\n");
 632                         return false;
 633                 }
 634                 kmemleak_ignore(p);
 635                 opal_xive_donate_page(chip, __pa(p));
 636         }
 637         return true;
 638 }
 639
 640 u32 xive_native_alloc_vp_block(u32 max_vcpus)
 641 {
 642         s64 rc;
 643         u32 order;
 644
 645         order = fls(max_vcpus) - 1;
 646         if (max_vcpus > (1 << order))
 647                 order++;
 648
 649         pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
 650                  max_vcpus, order);
 651
 652         for (;;) {
 653                 rc = opal_xive_alloc_vp_block(order);
 654                 switch (rc) {
 655                 case OPAL_BUSY:
 656                         msleep(1);
 657                         break;
 658                 case OPAL_XIVE_PROVISIONING:
 659                         if (!xive_native_provision_pages())
 660                                 return XIVE_INVALID_VP;
 661                         break;
 662                 default:
 663                         if (rc < 0) {
 664                                 pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
 665                                        order, rc);
 666                                 return XIVE_INVALID_VP;
 667                         }
 668                         return rc;
 669                 }
 670         }
 671 }
 672 EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
 673
 674 void xive_native_free_vp_block(u32 vp_base)
 675 {
 676         s64 rc;
 677
 678         if (vp_base == XIVE_INVALID_VP)
 679                 return;
 680
 681         rc = opal_xive_free_vp_block(vp_base);
 682         if (rc < 0)
 683                 pr_warn("OPAL error %lld freeing VP block\n", rc);
 684 }
 685 EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
 686
 687 int xive_native_enable_vp(u32 vp_id)
 688 {
 689         s64 rc;
 690
 691         for (;;) {
 692                 rc = opal_xive_set_vp_info(vp_id, OPAL_XIVE_VP_ENABLED, 0);
 693                 if (rc != OPAL_BUSY)
 694                         break;
 695                 msleep(1);
 696         }
 697         return rc ? -EIO : 0;
 698 }
 699 EXPORT_SYMBOL_GPL(xive_native_enable_vp);
 700
 701 int xive_native_disable_vp(u32 vp_id)
 702 {
 703         s64 rc;
 704
 705         for (;;) {
 706                 rc = opal_xive_set_vp_info(vp_id, 0, 0);
 707                 if (rc != OPAL_BUSY)
 708                         break;
 709                 msleep(1);
 710         }
 711         return rc ? -EIO : 0;
 712 }
 713 EXPORT_SYMBOL_GPL(xive_native_disable_vp);
 714
 715 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
 716 {
 717         __be64 vp_cam_be;
 718         __be32 vp_chip_id_be;
 719         s64 rc;
 720
 721         rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
 722         if (rc)
 723                 return -EIO;
 724         *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
 725         *out_chip_id = be32_to_cpu(vp_chip_id_be);
 726
 727         return 0;
 728 }
 729 EXPORT_SYMBOL_GPL(xive_native_get_vp_info);