2 * Copyright 2016,2017 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #define pr_fmt(fmt) "xive: " fmt
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/debugfs.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/seq_file.h>
20 #include <linux/init.h>
21 #include <linux/cpu.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/msi.h>
26 #include <linux/vmalloc.h>
31 #include <asm/machdep.h>
33 #include <asm/errno.h>
35 #include <asm/xive-regs.h>
38 #include "xive-internal.h"
44 #define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
45 smp_processor_id(), ## __VA_ARGS__)
47 #define DBG_VERBOSE(fmt...) do { } while(0)
51 EXPORT_SYMBOL_GPL(__xive_enabled);
52 bool xive_cmdline_disabled;
54 /* We use only one priority for now */
55 static u8 xive_irq_priority;
57 /* TIMA exported to KVM */
58 void __iomem *xive_tima;
59 EXPORT_SYMBOL_GPL(xive_tima);
63 static const struct xive_ops *xive_ops;
65 /* Our global interrupt domain */
66 static struct irq_domain *xive_irq_domain;
69 /* The IPIs all use the same logical irq number */
70 static u32 xive_ipi_irq;
73 /* Xive state for each CPU */
74 static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
76 /* An invalid CPU target */
77 #define XIVE_INVALID_TARGET (-1)
80 * Read the next entry in a queue, return its content if it's valid
81 * or 0 if there is no new entry.
83 * The queue pointer is moved forward unless "just_peek" is set
85 static u32 xive_read_eq(struct xive_q *q, bool just_peek)
91 cur = be32_to_cpup(q->qpage + q->idx);
93 /* Check valid bit (31) vs current toggle polarity */
94 if ((cur >> 31) == q->toggle)
97 /* If consuming from the queue ... */
100 q->idx = (q->idx + 1) & q->msk;
102 /* Wrap around: flip valid toggle */
106 /* Mask out the valid bit (31) */
107 return cur & 0x7fffffff;
111 * Scans all the queue that may have interrupts in them
112 * (based on "pending_prio") in priority order until an
113 * interrupt is found or all the queues are empty.
115 * Then updates the CPPR (Current Processor Priority
116 * Register) based on the most favored interrupt found
117 * (0xff if none) and return what was found (0 if none).
119 * If just_peek is set, return the most favored pending
120 * interrupt if any but don't update the queue pointers.
122 * Note: This function can operate generically on any number
123 * of queues (up to 8). The current implementation of the XIVE
124 * driver only uses a single queue however.
126 * Note2: This will also "flush" "the pending_count" of a queue
127 * into the "count" when that queue is observed to be empty.
128 * This is used to keep track of the amount of interrupts
129 * targetting a queue. When an interrupt is moved away from
130 * a queue, we only decrement that queue count once the queue
131 * has been observed empty to avoid races.
133 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
138 /* Find highest pending priority */
139 while (xc->pending_prio != 0) {
142 prio = ffs(xc->pending_prio) - 1;
143 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
146 irq = xive_read_eq(&xc->queue[prio], just_peek);
148 /* Found something ? That's it */
152 /* Clear pending bits */
153 xc->pending_prio &= ~(1 << prio);
156 * Check if the queue count needs adjusting due to
157 * interrupts being moved away. See description of
158 * xive_dec_target_count()
160 q = &xc->queue[prio];
161 if (atomic_read(&q->pending_count)) {
162 int p = atomic_xchg(&q->pending_count, 0);
164 WARN_ON(p > atomic_read(&q->count));
165 atomic_sub(p, &q->count);
170 /* If nothing was found, set CPPR to 0xff */
174 /* Update HW CPPR to match if necessary */
175 if (prio != xc->cppr) {
176 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
178 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
185 * This is used to perform the magic loads from an ESB
186 * described in xive.h
188 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
192 /* Handle HW errata */
193 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
194 offset |= offset << 4;
196 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
197 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
199 val = in_be64(xd->eoi_mmio + offset);
204 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
206 /* Handle HW errata */
207 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
208 offset |= offset << 4;
210 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
211 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
213 out_be64(xd->eoi_mmio + offset, data);
217 static notrace void xive_dump_eq(const char *name, struct xive_q *q)
224 i0 = be32_to_cpup(q->qpage + idx);
225 idx = (idx + 1) & q->msk;
226 i1 = be32_to_cpup(q->qpage + idx);
227 xmon_printf(" %s Q T=%d %08x %08x ...\n", name,
231 notrace void xmon_xive_do_dump(int cpu)
233 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
235 xmon_printf("XIVE state for CPU %d:\n", cpu);
236 xmon_printf(" pp=%02x cppr=%02x\n", xc->pending_prio, xc->cppr);
237 xive_dump_eq("IRQ", &xc->queue[xive_irq_priority]);
240 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
241 xmon_printf(" IPI state: %x:%c%c\n", xc->hw_ipi,
242 val & XIVE_ESB_VAL_P ? 'P' : 'p',
243 val & XIVE_ESB_VAL_P ? 'Q' : 'q');
247 #endif /* CONFIG_XMON */
249 static unsigned int xive_get_irq(void)
251 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
255 * This can be called either as a result of a HW interrupt or
256 * as a "replay" because EOI decided there was still something
257 * in one of the queues.
259 * First we perform an ACK cycle in order to update our mask
260 * of pending priorities. This will also have the effect of
261 * updating the CPPR to the most favored pending interrupts.
263 * In the future, if we have a way to differenciate a first
264 * entry (on HW interrupt) from a replay triggered by EOI,
265 * we could skip this on replays unless we soft-mask tells us
266 * that a new HW interrupt occurred.
268 xive_ops->update_pending(xc);
270 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
272 /* Scan our queue(s) for interrupts */
273 irq = xive_scan_interrupts(xc, false);
275 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
276 irq, xc->pending_prio);
278 /* Return pending interrupt if any */
279 if (irq == XIVE_BAD_IRQ)
285 * After EOI'ing an interrupt, we need to re-check the queue
286 * to see if another interrupt is pending since multiple
287 * interrupts can coalesce into a single notification to the
290 * If we find that there is indeed more in there, we call
291 * force_external_irq_replay() to make Linux synthetize an
292 * external interrupt on the next call to local_irq_restore().
294 static void xive_do_queue_eoi(struct xive_cpu *xc)
296 if (xive_scan_interrupts(xc, true) != 0) {
297 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
298 force_external_irq_replay();
303 * EOI an interrupt at the source. There are several methods
304 * to do this depending on the HW version and source type
306 void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
308 /* If the XIVE supports the new "store EOI facility, use it */
309 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
310 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
311 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
313 * The FW told us to call it. This happens for some
314 * interrupt sources that need additional HW whacking
315 * beyond the ESB manipulation. For example LPC interrupts
316 * on P9 DD1.0 need a latch to be clared in the LPC bridge
317 * itself. The Firmware will take care of it.
319 if (WARN_ON_ONCE(!xive_ops->eoi))
321 xive_ops->eoi(hw_irq);
326 * Otherwise for EOI, we use the special MMIO that does
327 * a clear of both P and Q and returns the old Q,
328 * except for LSIs where we use the "EOI cycle" special
331 * This allows us to then do a re-trigger if Q was set
332 * rather than synthesizing an interrupt in software
334 * For LSIs, using the HW EOI cycle works around a problem
335 * on P9 DD1 PHBs where the other ESB accesses don't work
338 if (xd->flags & XIVE_IRQ_FLAG_LSI)
339 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
341 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
342 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
344 /* Re-trigger if needed */
345 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
346 out_be64(xd->trig_mmio, 0);
351 /* irq_chip eoi callback */
352 static void xive_irq_eoi(struct irq_data *d)
354 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
355 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
357 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
358 d->irq, irqd_to_hwirq(d), xc->pending_prio);
361 * EOI the source if it hasn't been disabled and hasn't
362 * been passed-through to a KVM guest
364 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d))
365 xive_do_source_eoi(irqd_to_hwirq(d), xd);
368 * Clear saved_p to indicate that it's no longer occupying
369 * a queue slot on the target queue
373 /* Check for more work in the queue */
374 xive_do_queue_eoi(xc);
378 * Helper used to mask and unmask an interrupt source. This
379 * is only called for normal interrupts that do not require
380 * masking/unmasking via firmware.
382 static void xive_do_source_set_mask(struct xive_irq_data *xd,
388 * If the interrupt had P set, it may be in a queue.
390 * We need to make sure we don't re-enable it until it
391 * has been fetched from that queue and EOId. We keep
392 * a copy of that P state and use it to restore the
393 * ESB accordingly on unmask.
396 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
397 xd->saved_p = !!(val & XIVE_ESB_VAL_P);
398 } else if (xd->saved_p)
399 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
401 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
405 * Try to chose "cpu" as a new interrupt target. Increments
406 * the queue accounting for that target if it's not already
409 static bool xive_try_pick_target(int cpu)
411 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
412 struct xive_q *q = &xc->queue[xive_irq_priority];
416 * Calculate max number of interrupts in that queue.
418 * We leave a gap of 1 just in case...
420 max = (q->msk + 1) - 1;
421 return !!atomic_add_unless(&q->count, 1, max);
425 * Un-account an interrupt for a target CPU. We don't directly
426 * decrement q->count since the interrupt might still be present
429 * Instead increment a separate counter "pending_count" which
430 * will be substracted from "count" later when that CPU observes
431 * the queue to be empty.
433 static void xive_dec_target_count(int cpu)
435 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
436 struct xive_q *q = &xc->queue[xive_irq_priority];
438 if (unlikely(WARN_ON(cpu < 0 || !xc))) {
439 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
444 * We increment the "pending count" which will be used
445 * to decrement the target queue count whenever it's next
446 * processed and found empty. This ensure that we don't
447 * decrement while we still have the interrupt there
450 atomic_inc(&q->pending_count);
453 /* Find a tentative CPU target in a CPU mask */
454 static int xive_find_target_in_mask(const struct cpumask *mask,
457 int cpu, first, num, i;
459 /* Pick up a starting point CPU in the mask based on fuzz */
460 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
464 cpu = cpumask_first(mask);
465 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
466 cpu = cpumask_next(cpu, mask);
469 if (WARN_ON(cpu >= nr_cpu_ids))
470 cpu = cpumask_first(cpu_online_mask);
472 /* Remember first one to handle wrap-around */
476 * Now go through the entire mask until we find a valid
481 * We re-check online as the fallback case passes us
482 * an untested affinity mask
484 if (cpu_online(cpu) && xive_try_pick_target(cpu))
486 cpu = cpumask_next(cpu, mask);
488 if (cpu >= nr_cpu_ids)
489 cpu = cpumask_first(mask);
490 } while (cpu != first);
496 * Pick a target CPU for an interrupt. This is done at
497 * startup or if the affinity is changed in a way that
498 * invalidates the current target.
500 static int xive_pick_irq_target(struct irq_data *d,
501 const struct cpumask *affinity)
503 static unsigned int fuzz;
504 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
509 * If we have chip IDs, first we try to build a mask of
510 * CPUs matching the CPU and find a target in there
512 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
513 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
514 /* Build a mask of matching chip IDs */
515 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
516 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
517 if (xc->chip_id == xd->src_chip)
518 cpumask_set_cpu(cpu, mask);
520 /* Try to find a target */
521 if (cpumask_empty(mask))
524 cpu = xive_find_target_in_mask(mask, fuzz++);
525 free_cpumask_var(mask);
531 /* No chip IDs, fallback to using the affinity mask */
532 return xive_find_target_in_mask(affinity, fuzz++);
535 static unsigned int xive_irq_startup(struct irq_data *d)
537 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
538 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
541 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
544 #ifdef CONFIG_PCI_MSI
546 * The generic MSI code returns with the interrupt disabled on the
547 * card, using the MSI mask bits. Firmware doesn't appear to unmask
548 * at that level, so we do it here by hand.
550 if (irq_data_get_msi_desc(d))
551 pci_msi_unmask_irq(d);
555 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
556 if (target == XIVE_INVALID_TARGET) {
557 /* Try again breaking affinity */
558 target = xive_pick_irq_target(d, cpu_online_mask);
559 if (target == XIVE_INVALID_TARGET)
561 pr_warn("irq %d started with broken affinity\n", d->irq);
565 if (WARN_ON(target == XIVE_INVALID_TARGET ||
566 target >= nr_cpu_ids))
567 target = smp_processor_id();
572 * Configure the logical number to be the Linux IRQ number
573 * and set the target queue
575 rc = xive_ops->configure_irq(hw_irq,
576 get_hard_smp_processor_id(target),
577 xive_irq_priority, d->irq);
582 xive_do_source_set_mask(xd, false);
587 static void xive_irq_shutdown(struct irq_data *d)
589 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
590 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
592 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
595 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
598 /* Mask the interrupt at the source */
599 xive_do_source_set_mask(xd, true);
602 * The above may have set saved_p. We clear it otherwise it
603 * will prevent re-enabling later on. It is ok to forget the
604 * fact that the interrupt might be in a queue because we are
605 * accounting that already in xive_dec_target_count() and will
606 * be re-routing it to a new queue with proper accounting when
607 * it's started up again
612 * Mask the interrupt in HW in the IVT/EAS and set the number
613 * to be the "bad" IRQ number
615 xive_ops->configure_irq(hw_irq,
616 get_hard_smp_processor_id(xd->target),
619 xive_dec_target_count(xd->target);
620 xd->target = XIVE_INVALID_TARGET;
623 static void xive_irq_unmask(struct irq_data *d)
625 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
627 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
630 * This is a workaround for PCI LSI problems on P9, for
631 * these, we call FW to set the mask. The problems might
632 * be fixed by P9 DD2.0, if that is the case, firmware
633 * will no longer set that flag.
635 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
636 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
637 xive_ops->configure_irq(hw_irq,
638 get_hard_smp_processor_id(xd->target),
639 xive_irq_priority, d->irq);
643 xive_do_source_set_mask(xd, false);
646 static void xive_irq_mask(struct irq_data *d)
648 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
650 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
653 * This is a workaround for PCI LSI problems on P9, for
654 * these, we call OPAL to set the mask. The problems might
655 * be fixed by P9 DD2.0, if that is the case, firmware
656 * will no longer set that flag.
658 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
659 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
660 xive_ops->configure_irq(hw_irq,
661 get_hard_smp_processor_id(xd->target),
666 xive_do_source_set_mask(xd, true);
669 static int xive_irq_set_affinity(struct irq_data *d,
670 const struct cpumask *cpumask,
673 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
674 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
675 u32 target, old_target;
678 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
680 /* Is this valid ? */
681 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
684 /* Don't do anything if the interrupt isn't started */
685 if (!irqd_is_started(d))
686 return IRQ_SET_MASK_OK;
689 * If existing target is already in the new mask, and is
690 * online then do nothing.
692 if (xd->target != XIVE_INVALID_TARGET &&
693 cpu_online(xd->target) &&
694 cpumask_test_cpu(xd->target, cpumask))
695 return IRQ_SET_MASK_OK;
697 /* Pick a new target */
698 target = xive_pick_irq_target(d, cpumask);
700 /* No target found */
701 if (target == XIVE_INVALID_TARGET)
705 if (WARN_ON(target >= nr_cpu_ids))
706 target = smp_processor_id();
708 old_target = xd->target;
711 * Only configure the irq if it's not currently passed-through to
714 if (!irqd_is_forwarded_to_vcpu(d))
715 rc = xive_ops->configure_irq(hw_irq,
716 get_hard_smp_processor_id(target),
717 xive_irq_priority, d->irq);
719 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
723 pr_devel(" target: 0x%x\n", target);
726 /* Give up previous target */
727 if (old_target != XIVE_INVALID_TARGET)
728 xive_dec_target_count(old_target);
730 return IRQ_SET_MASK_OK;
733 static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
735 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
738 * We only support these. This has really no effect other than setting
739 * the corresponding descriptor bits mind you but those will in turn
740 * affect the resend function when re-enabling an edge interrupt.
742 * Set set the default to edge as explained in map().
744 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
745 flow_type = IRQ_TYPE_EDGE_RISING;
747 if (flow_type != IRQ_TYPE_EDGE_RISING &&
748 flow_type != IRQ_TYPE_LEVEL_LOW)
751 irqd_set_trigger_type(d, flow_type);
754 * Double check it matches what the FW thinks
756 * NOTE: We don't know yet if the PAPR interface will provide
757 * the LSI vs MSI information apart from the device-tree so
758 * this check might have to move into an optional backend call
759 * that is specific to the native backend
761 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
762 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
763 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
764 d->irq, (u32)irqd_to_hwirq(d),
765 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
766 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
769 return IRQ_SET_MASK_OK_NOCOPY;
772 static int xive_irq_retrigger(struct irq_data *d)
774 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
776 /* This should be only for MSIs */
777 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
781 * To perform a retrigger, we first set the PQ bits to
782 * 11, then perform an EOI.
784 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
787 * Note: We pass "0" to the hw_irq argument in order to
788 * avoid calling into the backend EOI code which we don't
789 * want to do in the case of a re-trigger. Backends typically
790 * only do EOI for LSIs anyway.
792 xive_do_source_eoi(0, xd);
797 static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
799 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
800 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
805 * We only support this on interrupts that do not require
806 * firmware calls for masking and unmasking
808 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
812 * This is called by KVM with state non-NULL for enabling
813 * pass-through or NULL for disabling it
816 irqd_set_forwarded_to_vcpu(d);
818 /* Set it to PQ=10 state to prevent further sends */
819 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
821 /* No target ? nothing to do */
822 if (xd->target == XIVE_INVALID_TARGET) {
824 * An untargetted interrupt should have been
825 * also masked at the source
833 * If P was set, adjust state to PQ=11 to indicate
834 * that a resend is needed for the interrupt to reach
835 * the guest. Also remember the value of P.
837 * This also tells us that it's in flight to a host queue
838 * or has already been fetched but hasn't been EOIed yet
839 * by the host. This it's potentially using up a host
840 * queue slot. This is important to know because as long
841 * as this is the case, we must not hard-unmask it when
842 * "returning" that interrupt to the host.
844 * This saved_p is cleared by the host EOI, when we know
845 * for sure the queue slot is no longer in use.
848 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
852 * Sync the XIVE source HW to ensure the interrupt
853 * has gone through the EAS before we change its
854 * target to the guest. That should guarantee us
855 * that we *will* eventually get an EOI for it on
856 * the host. Otherwise there would be a small window
857 * for P to be seen here but the interrupt going
858 * to the guest queue.
860 if (xive_ops->sync_source)
861 xive_ops->sync_source(hw_irq);
865 irqd_clr_forwarded_to_vcpu(d);
867 /* No host target ? hard mask and return */
868 if (xd->target == XIVE_INVALID_TARGET) {
869 xive_do_source_set_mask(xd, true);
874 * Sync the XIVE source HW to ensure the interrupt
875 * has gone through the EAS before we change its
876 * target to the host.
878 if (xive_ops->sync_source)
879 xive_ops->sync_source(hw_irq);
882 * By convention we are called with the interrupt in
883 * a PQ=10 or PQ=11 state, ie, it won't fire and will
884 * have latched in Q whether there's a pending HW
887 * First reconfigure the target.
889 rc = xive_ops->configure_irq(hw_irq,
890 get_hard_smp_processor_id(xd->target),
891 xive_irq_priority, d->irq);
896 * Then if saved_p is not set, effectively re-enable the
897 * interrupt with an EOI. If it is set, we know there is
898 * still a message in a host queue somewhere that will be
901 * Note: We don't check irqd_irq_disabled(). Effectively,
902 * we *will* let the irq get through even if masked if the
903 * HW is still firing it in order to deal with the whole
904 * saved_p business properly. If the interrupt triggers
905 * while masked, the generic code will re-mask it anyway.
908 xive_do_source_eoi(hw_irq, xd);
914 static struct irq_chip xive_irq_chip = {
916 .irq_startup = xive_irq_startup,
917 .irq_shutdown = xive_irq_shutdown,
918 .irq_eoi = xive_irq_eoi,
919 .irq_mask = xive_irq_mask,
920 .irq_unmask = xive_irq_unmask,
921 .irq_set_affinity = xive_irq_set_affinity,
922 .irq_set_type = xive_irq_set_type,
923 .irq_retrigger = xive_irq_retrigger,
924 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
927 bool is_xive_irq(struct irq_chip *chip)
929 return chip == &xive_irq_chip;
931 EXPORT_SYMBOL_GPL(is_xive_irq);
933 void xive_cleanup_irq_data(struct xive_irq_data *xd)
936 unmap_kernel_range((unsigned long)xd->eoi_mmio,
937 1u << xd->esb_shift);
938 iounmap(xd->eoi_mmio);
939 if (xd->eoi_mmio == xd->trig_mmio)
940 xd->trig_mmio = NULL;
944 unmap_kernel_range((unsigned long)xd->trig_mmio,
945 1u << xd->esb_shift);
946 iounmap(xd->trig_mmio);
947 xd->trig_mmio = NULL;
950 EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
952 static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
954 struct xive_irq_data *xd;
957 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
960 rc = xive_ops->populate_irq_data(hw, xd);
965 xd->target = XIVE_INVALID_TARGET;
966 irq_set_handler_data(virq, xd);
969 * Turn OFF by default the interrupt being mapped. A side
970 * effect of this check is the mapping the ESB page of the
971 * interrupt in the Linux address space. This prevents page
972 * fault issues in the crash handler which masks all
975 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
980 static void xive_irq_free_data(unsigned int virq)
982 struct xive_irq_data *xd = irq_get_handler_data(virq);
986 irq_set_handler_data(virq, NULL);
987 xive_cleanup_irq_data(xd);
993 static void xive_cause_ipi(int cpu)
996 struct xive_irq_data *xd;
998 xc = per_cpu(xive_cpu, cpu);
1000 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1001 smp_processor_id(), cpu, xc->hw_ipi);
1004 if (WARN_ON(!xd->trig_mmio))
1006 out_be64(xd->trig_mmio, 0);
1009 static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1011 return smp_ipi_demux();
1014 static void xive_ipi_eoi(struct irq_data *d)
1016 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1018 /* Handle possible race with unplug and drop stale IPIs */
1022 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1023 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1025 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
1026 xive_do_queue_eoi(xc);
1029 static void xive_ipi_do_nothing(struct irq_data *d)
1032 * Nothing to do, we never mask/unmask IPIs, but the callback
1033 * has to exist for the struct irq_chip.
1037 static struct irq_chip xive_ipi_chip = {
1039 .irq_eoi = xive_ipi_eoi,
1040 .irq_mask = xive_ipi_do_nothing,
1041 .irq_unmask = xive_ipi_do_nothing,
1044 static void __init xive_request_ipi(void)
1049 * Initialization failed, move on, we might manage to
1050 * reach the point where we display our errors before
1051 * the system falls appart
1053 if (!xive_irq_domain)
1057 virq = irq_create_mapping(xive_irq_domain, 0);
1058 xive_ipi_irq = virq;
1060 WARN_ON(request_irq(virq, xive_muxed_ipi_action,
1061 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
1064 static int xive_setup_cpu_ipi(unsigned int cpu)
1066 struct xive_cpu *xc;
1069 pr_debug("Setting up IPI for CPU %d\n", cpu);
1071 xc = per_cpu(xive_cpu, cpu);
1073 /* Check if we are already setup */
1074 if (xc->hw_ipi != XIVE_BAD_IRQ)
1077 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1078 if (xive_ops->get_ipi(cpu, xc))
1082 * Populate the IRQ data in the xive_cpu structure and
1083 * configure the HW / enable the IPIs.
1085 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1087 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1090 rc = xive_ops->configure_irq(xc->hw_ipi,
1091 get_hard_smp_processor_id(cpu),
1092 xive_irq_priority, xive_ipi_irq);
1094 pr_err("Failed to map IPI CPU %d\n", cpu);
1097 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1098 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1101 xive_do_source_set_mask(&xc->ipi_data, false);
1106 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1108 /* Disable the IPI and free the IRQ data */
1110 /* Already cleaned up ? */
1111 if (xc->hw_ipi == XIVE_BAD_IRQ)
1115 xive_do_source_set_mask(&xc->ipi_data, true);
1118 * Note: We don't call xive_cleanup_irq_data() to free
1119 * the mappings as this is called from an IPI on kexec
1120 * which is not a safe environment to call iounmap()
1123 /* Deconfigure/mask in the backend */
1124 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1125 0xff, xive_ipi_irq);
1127 /* Free the IPIs in the backend */
1128 xive_ops->put_ipi(cpu, xc);
1131 void __init xive_smp_probe(void)
1133 smp_ops->cause_ipi = xive_cause_ipi;
1135 /* Register the IPI */
1138 /* Allocate and setup IPI for the boot CPU */
1139 xive_setup_cpu_ipi(smp_processor_id());
1142 #endif /* CONFIG_SMP */
1144 static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1150 * Mark interrupts as edge sensitive by default so that resend
1151 * actually works. Will fix that up below if needed.
1153 irq_clear_status_flags(virq, IRQ_LEVEL);
1156 /* IPIs are special and come up with HW number 0 */
1159 * IPIs are marked per-cpu. We use separate HW interrupts under
1160 * the hood but associated with the same "linux" interrupt
1162 irq_set_chip_and_handler(virq, &xive_ipi_chip,
1168 rc = xive_irq_alloc_data(virq, hw);
1172 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1177 static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1179 struct irq_data *data = irq_get_irq_data(virq);
1180 unsigned int hw_irq;
1182 /* XXX Assign BAD number */
1185 hw_irq = (unsigned int)irqd_to_hwirq(data);
1187 xive_irq_free_data(virq);
1190 static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1191 const u32 *intspec, unsigned int intsize,
1192 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1195 *out_hwirq = intspec[0];
1198 * If intsize is at least 2, we look for the type in the second cell,
1199 * we assume the LSB indicates a level interrupt.
1203 *out_flags = IRQ_TYPE_LEVEL_LOW;
1205 *out_flags = IRQ_TYPE_EDGE_RISING;
1207 *out_flags = IRQ_TYPE_LEVEL_LOW;
1212 static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1213 enum irq_domain_bus_token bus_token)
1215 return xive_ops->match(node);
1218 static const struct irq_domain_ops xive_irq_domain_ops = {
1219 .match = xive_irq_domain_match,
1220 .map = xive_irq_domain_map,
1221 .unmap = xive_irq_domain_unmap,
1222 .xlate = xive_irq_domain_xlate,
1225 static void __init xive_init_host(void)
1227 xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ,
1228 &xive_irq_domain_ops, NULL);
1229 if (WARN_ON(xive_irq_domain == NULL))
1231 irq_set_default_host(xive_irq_domain);
1234 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1236 if (xc->queue[xive_irq_priority].qpage)
1237 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1240 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1244 /* We setup 1 queues for now with a 64k page */
1245 if (!xc->queue[xive_irq_priority].qpage)
1246 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1251 static int xive_prepare_cpu(unsigned int cpu)
1253 struct xive_cpu *xc;
1255 xc = per_cpu(xive_cpu, cpu);
1257 struct device_node *np;
1259 xc = kzalloc_node(sizeof(struct xive_cpu),
1260 GFP_KERNEL, cpu_to_node(cpu));
1263 np = of_get_cpu_node(cpu, NULL);
1265 xc->chip_id = of_get_ibm_chip_id(np);
1267 xc->hw_ipi = XIVE_BAD_IRQ;
1269 per_cpu(xive_cpu, cpu) = xc;
1272 /* Setup EQs if not already */
1273 return xive_setup_cpu_queues(cpu, xc);
1276 static void xive_setup_cpu(void)
1278 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1280 /* Debug: Dump the TM state */
1281 pr_devel("CPU %d [HW 0x%02x] VT=%02x\n",
1282 smp_processor_id(), hard_smp_processor_id(),
1283 in_8(xive_tima + xive_tima_offset + TM_WORD2));
1285 /* The backend might have additional things to do */
1286 if (xive_ops->setup_cpu)
1287 xive_ops->setup_cpu(smp_processor_id(), xc);
1289 /* Set CPPR to 0xff to enable flow of interrupts */
1291 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1295 void xive_smp_setup_cpu(void)
1297 pr_devel("SMP setup CPU %d\n", smp_processor_id());
1299 /* This will have already been done on the boot CPU */
1300 if (smp_processor_id() != boot_cpuid)
1305 int xive_smp_prepare_cpu(unsigned int cpu)
1309 /* Allocate per-CPU data and queues */
1310 rc = xive_prepare_cpu(cpu);
1314 /* Allocate and setup IPI for the new CPU */
1315 return xive_setup_cpu_ipi(cpu);
1318 #ifdef CONFIG_HOTPLUG_CPU
1319 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1323 /* We assume local irqs are disabled */
1324 WARN_ON(!irqs_disabled());
1326 /* Check what's already in the CPU queue */
1327 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1329 * We need to re-route that interrupt to its new destination.
1330 * First get and lock the descriptor
1332 struct irq_desc *desc = irq_to_desc(irq);
1333 struct irq_data *d = irq_desc_get_irq_data(desc);
1334 struct xive_irq_data *xd;
1335 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1338 * Ignore anything that isn't a XIVE irq and ignore
1339 * IPIs, so can just be dropped.
1341 if (d->domain != xive_irq_domain || hw_irq == 0)
1345 * The IRQ should have already been re-routed, it's just a
1346 * stale in the old queue, so re-trigger it in order to make
1347 * it reach is new destination.
1350 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1353 raw_spin_lock(&desc->lock);
1354 xd = irq_desc_get_handler_data(desc);
1357 * For LSIs, we EOI, this will cause a resend if it's
1358 * still asserted. Otherwise do an MSI retrigger.
1360 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1361 xive_do_source_eoi(irqd_to_hwirq(d), xd);
1363 xive_irq_retrigger(d);
1365 raw_spin_unlock(&desc->lock);
1369 void xive_smp_disable_cpu(void)
1371 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1372 unsigned int cpu = smp_processor_id();
1374 /* Migrate interrupts away from the CPU */
1375 irq_migrate_all_off_this_cpu();
1377 /* Set CPPR to 0 to disable flow of interrupts */
1379 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1381 /* Flush everything still in the queue */
1382 xive_flush_cpu_queue(cpu, xc);
1384 /* Re-enable CPPR */
1386 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1389 void xive_flush_interrupt(void)
1391 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1392 unsigned int cpu = smp_processor_id();
1394 /* Called if an interrupt occurs while the CPU is hot unplugged */
1395 xive_flush_cpu_queue(cpu, xc);
1398 #endif /* CONFIG_HOTPLUG_CPU */
1400 #endif /* CONFIG_SMP */
1402 void xive_teardown_cpu(void)
1404 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1405 unsigned int cpu = smp_processor_id();
1407 /* Set CPPR to 0 to disable flow of interrupts */
1409 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1411 if (xive_ops->teardown_cpu)
1412 xive_ops->teardown_cpu(cpu, xc);
1415 /* Get rid of IPI */
1416 xive_cleanup_cpu_ipi(cpu, xc);
1419 /* Disable and free the queues */
1420 xive_cleanup_cpu_queues(cpu, xc);
1423 void xive_kexec_teardown_cpu(int secondary)
1425 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1426 unsigned int cpu = smp_processor_id();
1428 /* Set CPPR to 0 to disable flow of interrupts */
1430 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1432 /* Backend cleanup if any */
1433 if (xive_ops->teardown_cpu)
1434 xive_ops->teardown_cpu(cpu, xc);
1437 /* Get rid of IPI */
1438 xive_cleanup_cpu_ipi(cpu, xc);
1441 /* Disable and free the queues */
1442 xive_cleanup_cpu_queues(cpu, xc);
1445 void xive_shutdown(void)
1447 xive_ops->shutdown();
1450 bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
1454 xive_tima_offset = offset;
1456 xive_irq_priority = max_prio;
1458 ppc_md.get_irq = xive_get_irq;
1459 __xive_enabled = true;
1461 pr_devel("Initializing host..\n");
1464 pr_devel("Initializing boot CPU..\n");
1466 /* Allocate per-CPU data and queues */
1467 xive_prepare_cpu(smp_processor_id());
1469 /* Get ready for interrupts */
1472 pr_info("Interrupt handling initialized with %s backend\n",
1474 pr_info("Using priority %d for all interrupts\n", max_prio);
1479 __be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1481 unsigned int alloc_order;
1485 alloc_order = xive_alloc_order(queue_shift);
1486 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1488 return ERR_PTR(-ENOMEM);
1489 qpage = (__be32 *)page_address(pages);
1490 memset(qpage, 0, 1 << queue_shift);
1495 static int __init xive_off(char *arg)
1497 xive_cmdline_disabled = true;
1500 __setup("xive=off", xive_off);