1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2016,2017 IBM Corporation.
6 #define pr_fmt(fmt) "xive: " fmt
8 #include <linux/types.h>
9 #include <linux/threads.h>
10 #include <linux/kernel.h>
11 #include <linux/irq.h>
12 #include <linux/debugfs.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/seq_file.h>
16 #include <linux/init.h>
17 #include <linux/cpu.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/msi.h>
22 #include <linux/vmalloc.h>
27 #include <asm/machdep.h>
29 #include <asm/errno.h>
31 #include <asm/xive-regs.h>
34 #include "xive-internal.h"
40 #define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
41 smp_processor_id(), ## __VA_ARGS__)
43 #define DBG_VERBOSE(fmt...) do { } while(0)
47 EXPORT_SYMBOL_GPL(__xive_enabled);
48 bool xive_cmdline_disabled;
50 /* We use only one priority for now */
51 static u8 xive_irq_priority;
53 /* TIMA exported to KVM */
54 void __iomem *xive_tima;
55 EXPORT_SYMBOL_GPL(xive_tima);
59 static const struct xive_ops *xive_ops;
61 /* Our global interrupt domain */
62 static struct irq_domain *xive_irq_domain;
65 /* The IPIs all use the same logical irq number */
66 static u32 xive_ipi_irq;
69 /* Xive state for each CPU */
70 static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
72 /* An invalid CPU target */
73 #define XIVE_INVALID_TARGET (-1)
76 * Read the next entry in a queue, return its content if it's valid
77 * or 0 if there is no new entry.
79 * The queue pointer is moved forward unless "just_peek" is set
81 static u32 xive_read_eq(struct xive_q *q, bool just_peek)
87 cur = be32_to_cpup(q->qpage + q->idx);
89 /* Check valid bit (31) vs current toggle polarity */
90 if ((cur >> 31) == q->toggle)
93 /* If consuming from the queue ... */
96 q->idx = (q->idx + 1) & q->msk;
98 /* Wrap around: flip valid toggle */
102 /* Mask out the valid bit (31) */
103 return cur & 0x7fffffff;
107 * Scans all the queue that may have interrupts in them
108 * (based on "pending_prio") in priority order until an
109 * interrupt is found or all the queues are empty.
111 * Then updates the CPPR (Current Processor Priority
112 * Register) based on the most favored interrupt found
113 * (0xff if none) and return what was found (0 if none).
115 * If just_peek is set, return the most favored pending
116 * interrupt if any but don't update the queue pointers.
118 * Note: This function can operate generically on any number
119 * of queues (up to 8). The current implementation of the XIVE
120 * driver only uses a single queue however.
122 * Note2: This will also "flush" "the pending_count" of a queue
123 * into the "count" when that queue is observed to be empty.
124 * This is used to keep track of the amount of interrupts
125 * targetting a queue. When an interrupt is moved away from
126 * a queue, we only decrement that queue count once the queue
127 * has been observed empty to avoid races.
129 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
134 /* Find highest pending priority */
135 while (xc->pending_prio != 0) {
138 prio = ffs(xc->pending_prio) - 1;
139 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
142 irq = xive_read_eq(&xc->queue[prio], just_peek);
144 /* Found something ? That's it */
146 if (just_peek || irq_to_desc(irq))
149 * We should never get here; if we do then we must
150 * have failed to synchronize the interrupt properly
151 * when shutting it down.
153 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
159 /* Clear pending bits */
160 xc->pending_prio &= ~(1 << prio);
163 * Check if the queue count needs adjusting due to
164 * interrupts being moved away. See description of
165 * xive_dec_target_count()
167 q = &xc->queue[prio];
168 if (atomic_read(&q->pending_count)) {
169 int p = atomic_xchg(&q->pending_count, 0);
171 WARN_ON(p > atomic_read(&q->count));
172 atomic_sub(p, &q->count);
177 /* If nothing was found, set CPPR to 0xff */
181 /* Update HW CPPR to match if necessary */
182 if (prio != xc->cppr) {
183 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
185 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
192 * This is used to perform the magic loads from an ESB
193 * described in xive-regs.h
195 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
199 /* Handle HW errata */
200 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
201 offset |= offset << 4;
203 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
204 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
206 val = in_be64(xd->eoi_mmio + offset);
211 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
213 /* Handle HW errata */
214 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
215 offset |= offset << 4;
217 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
218 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
220 out_be64(xd->eoi_mmio + offset, data);
224 static notrace void xive_dump_eq(const char *name, struct xive_q *q)
231 i0 = be32_to_cpup(q->qpage + idx);
232 idx = (idx + 1) & q->msk;
233 i1 = be32_to_cpup(q->qpage + idx);
234 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
235 q->idx, q->toggle, i0, i1);
238 notrace void xmon_xive_do_dump(int cpu)
240 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
242 xmon_printf("CPU %d:", cpu);
244 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
248 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
250 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
251 val & XIVE_ESB_VAL_P ? 'P' : '-',
252 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
255 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
260 static struct irq_data *xive_get_irq_data(u32 hw_irq)
262 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
264 return irq ? irq_get_irq_data(irq) : NULL;
267 int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
274 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
276 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
280 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
281 hw_irq, target, prio, lirq);
284 d = xive_get_irq_data(hw_irq);
287 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
288 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
290 xmon_printf("PQ=%c%c",
291 val & XIVE_ESB_VAL_P ? 'P' : '-',
292 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
299 #endif /* CONFIG_XMON */
301 static unsigned int xive_get_irq(void)
303 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
307 * This can be called either as a result of a HW interrupt or
308 * as a "replay" because EOI decided there was still something
309 * in one of the queues.
311 * First we perform an ACK cycle in order to update our mask
312 * of pending priorities. This will also have the effect of
313 * updating the CPPR to the most favored pending interrupts.
315 * In the future, if we have a way to differentiate a first
316 * entry (on HW interrupt) from a replay triggered by EOI,
317 * we could skip this on replays unless we soft-mask tells us
318 * that a new HW interrupt occurred.
320 xive_ops->update_pending(xc);
322 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
324 /* Scan our queue(s) for interrupts */
325 irq = xive_scan_interrupts(xc, false);
327 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
328 irq, xc->pending_prio);
330 /* Return pending interrupt if any */
331 if (irq == XIVE_BAD_IRQ)
337 * After EOI'ing an interrupt, we need to re-check the queue
338 * to see if another interrupt is pending since multiple
339 * interrupts can coalesce into a single notification to the
342 * If we find that there is indeed more in there, we call
343 * force_external_irq_replay() to make Linux synthetize an
344 * external interrupt on the next call to local_irq_restore().
346 static void xive_do_queue_eoi(struct xive_cpu *xc)
348 if (xive_scan_interrupts(xc, true) != 0) {
349 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
350 force_external_irq_replay();
355 * EOI an interrupt at the source. There are several methods
356 * to do this depending on the HW version and source type
358 static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
361 /* If the XIVE supports the new "store EOI facility, use it */
362 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
363 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
364 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
366 * The FW told us to call it. This happens for some
367 * interrupt sources that need additional HW whacking
368 * beyond the ESB manipulation. For example LPC interrupts
369 * on P9 DD1.0 needed a latch to be clared in the LPC bridge
370 * itself. The Firmware will take care of it.
372 if (WARN_ON_ONCE(!xive_ops->eoi))
374 xive_ops->eoi(hw_irq);
379 * Otherwise for EOI, we use the special MMIO that does
380 * a clear of both P and Q and returns the old Q,
381 * except for LSIs where we use the "EOI cycle" special
384 * This allows us to then do a re-trigger if Q was set
385 * rather than synthesizing an interrupt in software
387 * For LSIs the HW EOI cycle is used rather than PQ bits,
388 * as they are automatically re-triggred in HW when still
391 if (xd->flags & XIVE_IRQ_FLAG_LSI)
392 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
394 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
395 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
397 /* Re-trigger if needed */
398 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
399 out_be64(xd->trig_mmio, 0);
404 /* irq_chip eoi callback, called with irq descriptor lock held */
405 static void xive_irq_eoi(struct irq_data *d)
407 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
408 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
410 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
411 d->irq, irqd_to_hwirq(d), xc->pending_prio);
414 * EOI the source if it hasn't been disabled and hasn't
415 * been passed-through to a KVM guest
417 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
418 !(xd->flags & XIVE_IRQ_NO_EOI))
419 xive_do_source_eoi(irqd_to_hwirq(d), xd);
424 * Clear saved_p to indicate that it's no longer occupying
425 * a queue slot on the target queue
429 /* Check for more work in the queue */
430 xive_do_queue_eoi(xc);
434 * Helper used to mask and unmask an interrupt source. This
435 * is only called for normal interrupts that do not require
436 * masking/unmasking via firmware.
438 static void xive_do_source_set_mask(struct xive_irq_data *xd,
444 * If the interrupt had P set, it may be in a queue.
446 * We need to make sure we don't re-enable it until it
447 * has been fetched from that queue and EOId. We keep
448 * a copy of that P state and use it to restore the
449 * ESB accordingly on unmask.
452 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
453 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
456 } else if (xd->saved_p) {
457 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
460 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
466 * Try to chose "cpu" as a new interrupt target. Increments
467 * the queue accounting for that target if it's not already
470 static bool xive_try_pick_target(int cpu)
472 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
473 struct xive_q *q = &xc->queue[xive_irq_priority];
477 * Calculate max number of interrupts in that queue.
479 * We leave a gap of 1 just in case...
481 max = (q->msk + 1) - 1;
482 return !!atomic_add_unless(&q->count, 1, max);
486 * Un-account an interrupt for a target CPU. We don't directly
487 * decrement q->count since the interrupt might still be present
490 * Instead increment a separate counter "pending_count" which
491 * will be substracted from "count" later when that CPU observes
492 * the queue to be empty.
494 static void xive_dec_target_count(int cpu)
496 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
497 struct xive_q *q = &xc->queue[xive_irq_priority];
499 if (WARN_ON(cpu < 0 || !xc)) {
500 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
505 * We increment the "pending count" which will be used
506 * to decrement the target queue count whenever it's next
507 * processed and found empty. This ensure that we don't
508 * decrement while we still have the interrupt there
511 atomic_inc(&q->pending_count);
514 /* Find a tentative CPU target in a CPU mask */
515 static int xive_find_target_in_mask(const struct cpumask *mask,
518 int cpu, first, num, i;
520 /* Pick up a starting point CPU in the mask based on fuzz */
521 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
525 cpu = cpumask_first(mask);
526 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
527 cpu = cpumask_next(cpu, mask);
530 if (WARN_ON(cpu >= nr_cpu_ids))
531 cpu = cpumask_first(cpu_online_mask);
533 /* Remember first one to handle wrap-around */
537 * Now go through the entire mask until we find a valid
542 * We re-check online as the fallback case passes us
543 * an untested affinity mask
545 if (cpu_online(cpu) && xive_try_pick_target(cpu))
547 cpu = cpumask_next(cpu, mask);
549 if (cpu >= nr_cpu_ids)
550 cpu = cpumask_first(mask);
551 } while (cpu != first);
557 * Pick a target CPU for an interrupt. This is done at
558 * startup or if the affinity is changed in a way that
559 * invalidates the current target.
561 static int xive_pick_irq_target(struct irq_data *d,
562 const struct cpumask *affinity)
564 static unsigned int fuzz;
565 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
570 * If we have chip IDs, first we try to build a mask of
571 * CPUs matching the CPU and find a target in there
573 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
574 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
575 /* Build a mask of matching chip IDs */
576 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
577 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
578 if (xc->chip_id == xd->src_chip)
579 cpumask_set_cpu(cpu, mask);
581 /* Try to find a target */
582 if (cpumask_empty(mask))
585 cpu = xive_find_target_in_mask(mask, fuzz++);
586 free_cpumask_var(mask);
592 /* No chip IDs, fallback to using the affinity mask */
593 return xive_find_target_in_mask(affinity, fuzz++);
596 static unsigned int xive_irq_startup(struct irq_data *d)
598 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
599 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
604 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
607 #ifdef CONFIG_PCI_MSI
609 * The generic MSI code returns with the interrupt disabled on the
610 * card, using the MSI mask bits. Firmware doesn't appear to unmask
611 * at that level, so we do it here by hand.
613 if (irq_data_get_msi_desc(d))
614 pci_msi_unmask_irq(d);
618 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
619 if (target == XIVE_INVALID_TARGET) {
620 /* Try again breaking affinity */
621 target = xive_pick_irq_target(d, cpu_online_mask);
622 if (target == XIVE_INVALID_TARGET)
624 pr_warn("irq %d started with broken affinity\n", d->irq);
628 if (WARN_ON(target == XIVE_INVALID_TARGET ||
629 target >= nr_cpu_ids))
630 target = smp_processor_id();
635 * Configure the logical number to be the Linux IRQ number
636 * and set the target queue
638 rc = xive_ops->configure_irq(hw_irq,
639 get_hard_smp_processor_id(target),
640 xive_irq_priority, d->irq);
645 xive_do_source_set_mask(xd, false);
650 /* called with irq descriptor lock held */
651 static void xive_irq_shutdown(struct irq_data *d)
653 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
654 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
656 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
659 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
662 /* Mask the interrupt at the source */
663 xive_do_source_set_mask(xd, true);
666 * Mask the interrupt in HW in the IVT/EAS and set the number
667 * to be the "bad" IRQ number
669 xive_ops->configure_irq(hw_irq,
670 get_hard_smp_processor_id(xd->target),
673 xive_dec_target_count(xd->target);
674 xd->target = XIVE_INVALID_TARGET;
677 static void xive_irq_unmask(struct irq_data *d)
679 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
681 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
684 * This is a workaround for PCI LSI problems on P9, for
685 * these, we call FW to set the mask. The problems might
686 * be fixed by P9 DD2.0, if that is the case, firmware
687 * will no longer set that flag.
689 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
690 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
691 xive_ops->configure_irq(hw_irq,
692 get_hard_smp_processor_id(xd->target),
693 xive_irq_priority, d->irq);
697 xive_do_source_set_mask(xd, false);
700 static void xive_irq_mask(struct irq_data *d)
702 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
704 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
707 * This is a workaround for PCI LSI problems on P9, for
708 * these, we call OPAL to set the mask. The problems might
709 * be fixed by P9 DD2.0, if that is the case, firmware
710 * will no longer set that flag.
712 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
713 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
714 xive_ops->configure_irq(hw_irq,
715 get_hard_smp_processor_id(xd->target),
720 xive_do_source_set_mask(xd, true);
723 static int xive_irq_set_affinity(struct irq_data *d,
724 const struct cpumask *cpumask,
727 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
728 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
729 u32 target, old_target;
732 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
734 /* Is this valid ? */
735 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
738 /* Don't do anything if the interrupt isn't started */
739 if (!irqd_is_started(d))
740 return IRQ_SET_MASK_OK;
743 * If existing target is already in the new mask, and is
744 * online then do nothing.
746 if (xd->target != XIVE_INVALID_TARGET &&
747 cpu_online(xd->target) &&
748 cpumask_test_cpu(xd->target, cpumask))
749 return IRQ_SET_MASK_OK;
751 /* Pick a new target */
752 target = xive_pick_irq_target(d, cpumask);
754 /* No target found */
755 if (target == XIVE_INVALID_TARGET)
759 if (WARN_ON(target >= nr_cpu_ids))
760 target = smp_processor_id();
762 old_target = xd->target;
765 * Only configure the irq if it's not currently passed-through to
768 if (!irqd_is_forwarded_to_vcpu(d))
769 rc = xive_ops->configure_irq(hw_irq,
770 get_hard_smp_processor_id(target),
771 xive_irq_priority, d->irq);
773 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
777 pr_devel(" target: 0x%x\n", target);
780 /* Give up previous target */
781 if (old_target != XIVE_INVALID_TARGET)
782 xive_dec_target_count(old_target);
784 return IRQ_SET_MASK_OK;
787 static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
789 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
792 * We only support these. This has really no effect other than setting
793 * the corresponding descriptor bits mind you but those will in turn
794 * affect the resend function when re-enabling an edge interrupt.
796 * Set set the default to edge as explained in map().
798 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
799 flow_type = IRQ_TYPE_EDGE_RISING;
801 if (flow_type != IRQ_TYPE_EDGE_RISING &&
802 flow_type != IRQ_TYPE_LEVEL_LOW)
805 irqd_set_trigger_type(d, flow_type);
808 * Double check it matches what the FW thinks
810 * NOTE: We don't know yet if the PAPR interface will provide
811 * the LSI vs MSI information apart from the device-tree so
812 * this check might have to move into an optional backend call
813 * that is specific to the native backend
815 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
816 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
817 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
818 d->irq, (u32)irqd_to_hwirq(d),
819 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
820 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
823 return IRQ_SET_MASK_OK_NOCOPY;
826 static int xive_irq_retrigger(struct irq_data *d)
828 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
830 /* This should be only for MSIs */
831 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
835 * To perform a retrigger, we first set the PQ bits to
836 * 11, then perform an EOI.
838 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
841 * Note: We pass "0" to the hw_irq argument in order to
842 * avoid calling into the backend EOI code which we don't
843 * want to do in the case of a re-trigger. Backends typically
844 * only do EOI for LSIs anyway.
846 xive_do_source_eoi(0, xd);
852 * Caller holds the irq descriptor lock, so this won't be called
853 * concurrently with xive_get_irqchip_state on the same interrupt.
855 static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
857 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
858 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
863 * We only support this on interrupts that do not require
864 * firmware calls for masking and unmasking
866 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
870 * This is called by KVM with state non-NULL for enabling
871 * pass-through or NULL for disabling it
874 irqd_set_forwarded_to_vcpu(d);
876 /* Set it to PQ=10 state to prevent further sends */
877 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
879 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
880 xd->stale_p = !xd->saved_p;
883 /* No target ? nothing to do */
884 if (xd->target == XIVE_INVALID_TARGET) {
886 * An untargetted interrupt should have been
887 * also masked at the source
889 WARN_ON(xd->saved_p);
895 * If P was set, adjust state to PQ=11 to indicate
896 * that a resend is needed for the interrupt to reach
897 * the guest. Also remember the value of P.
899 * This also tells us that it's in flight to a host queue
900 * or has already been fetched but hasn't been EOIed yet
901 * by the host. This it's potentially using up a host
902 * queue slot. This is important to know because as long
903 * as this is the case, we must not hard-unmask it when
904 * "returning" that interrupt to the host.
906 * This saved_p is cleared by the host EOI, when we know
907 * for sure the queue slot is no longer in use.
910 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
913 * Sync the XIVE source HW to ensure the interrupt
914 * has gone through the EAS before we change its
915 * target to the guest. That should guarantee us
916 * that we *will* eventually get an EOI for it on
917 * the host. Otherwise there would be a small window
918 * for P to be seen here but the interrupt going
919 * to the guest queue.
921 if (xive_ops->sync_source)
922 xive_ops->sync_source(hw_irq);
925 irqd_clr_forwarded_to_vcpu(d);
927 /* No host target ? hard mask and return */
928 if (xd->target == XIVE_INVALID_TARGET) {
929 xive_do_source_set_mask(xd, true);
934 * Sync the XIVE source HW to ensure the interrupt
935 * has gone through the EAS before we change its
936 * target to the host.
938 if (xive_ops->sync_source)
939 xive_ops->sync_source(hw_irq);
942 * By convention we are called with the interrupt in
943 * a PQ=10 or PQ=11 state, ie, it won't fire and will
944 * have latched in Q whether there's a pending HW
947 * First reconfigure the target.
949 rc = xive_ops->configure_irq(hw_irq,
950 get_hard_smp_processor_id(xd->target),
951 xive_irq_priority, d->irq);
956 * Then if saved_p is not set, effectively re-enable the
957 * interrupt with an EOI. If it is set, we know there is
958 * still a message in a host queue somewhere that will be
961 * Note: We don't check irqd_irq_disabled(). Effectively,
962 * we *will* let the irq get through even if masked if the
963 * HW is still firing it in order to deal with the whole
964 * saved_p business properly. If the interrupt triggers
965 * while masked, the generic code will re-mask it anyway.
968 xive_do_source_eoi(hw_irq, xd);
974 /* Called with irq descriptor lock held. */
975 static int xive_get_irqchip_state(struct irq_data *data,
976 enum irqchip_irq_state which, bool *state)
978 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
982 case IRQCHIP_STATE_ACTIVE:
983 pq = xive_esb_read(xd, XIVE_ESB_GET);
986 * The esb value being all 1's means we couldn't get
987 * the PQ state of the interrupt through mmio. It may
988 * happen, for example when querying a PHB interrupt
989 * while the PHB is in an error state. We consider the
990 * interrupt to be inactive in that case.
992 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
993 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
994 !irqd_irq_disabled(data)));
1001 static struct irq_chip xive_irq_chip = {
1003 .irq_startup = xive_irq_startup,
1004 .irq_shutdown = xive_irq_shutdown,
1005 .irq_eoi = xive_irq_eoi,
1006 .irq_mask = xive_irq_mask,
1007 .irq_unmask = xive_irq_unmask,
1008 .irq_set_affinity = xive_irq_set_affinity,
1009 .irq_set_type = xive_irq_set_type,
1010 .irq_retrigger = xive_irq_retrigger,
1011 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
1012 .irq_get_irqchip_state = xive_get_irqchip_state,
1015 bool is_xive_irq(struct irq_chip *chip)
1017 return chip == &xive_irq_chip;
1019 EXPORT_SYMBOL_GPL(is_xive_irq);
1021 void xive_cleanup_irq_data(struct xive_irq_data *xd)
1024 unmap_kernel_range((unsigned long)xd->eoi_mmio,
1025 1u << xd->esb_shift);
1026 iounmap(xd->eoi_mmio);
1027 if (xd->eoi_mmio == xd->trig_mmio)
1028 xd->trig_mmio = NULL;
1029 xd->eoi_mmio = NULL;
1031 if (xd->trig_mmio) {
1032 unmap_kernel_range((unsigned long)xd->trig_mmio,
1033 1u << xd->esb_shift);
1034 iounmap(xd->trig_mmio);
1035 xd->trig_mmio = NULL;
1038 EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
1040 static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
1042 struct xive_irq_data *xd;
1045 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1048 rc = xive_ops->populate_irq_data(hw, xd);
1053 xd->target = XIVE_INVALID_TARGET;
1054 irq_set_handler_data(virq, xd);
1057 * Turn OFF by default the interrupt being mapped. A side
1058 * effect of this check is the mapping the ESB page of the
1059 * interrupt in the Linux address space. This prevents page
1060 * fault issues in the crash handler which masks all
1063 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1068 static void xive_irq_free_data(unsigned int virq)
1070 struct xive_irq_data *xd = irq_get_handler_data(virq);
1074 irq_set_handler_data(virq, NULL);
1075 xive_cleanup_irq_data(xd);
1081 static void xive_cause_ipi(int cpu)
1083 struct xive_cpu *xc;
1084 struct xive_irq_data *xd;
1086 xc = per_cpu(xive_cpu, cpu);
1088 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1089 smp_processor_id(), cpu, xc->hw_ipi);
1092 if (WARN_ON(!xd->trig_mmio))
1094 out_be64(xd->trig_mmio, 0);
1097 static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1099 return smp_ipi_demux();
1102 static void xive_ipi_eoi(struct irq_data *d)
1104 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1106 /* Handle possible race with unplug and drop stale IPIs */
1110 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1111 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1113 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
1114 xive_do_queue_eoi(xc);
1117 static void xive_ipi_do_nothing(struct irq_data *d)
1120 * Nothing to do, we never mask/unmask IPIs, but the callback
1121 * has to exist for the struct irq_chip.
1125 static struct irq_chip xive_ipi_chip = {
1127 .irq_eoi = xive_ipi_eoi,
1128 .irq_mask = xive_ipi_do_nothing,
1129 .irq_unmask = xive_ipi_do_nothing,
1132 static void __init xive_request_ipi(void)
1137 * Initialization failed, move on, we might manage to
1138 * reach the point where we display our errors before
1139 * the system falls appart
1141 if (!xive_irq_domain)
1145 virq = irq_create_mapping(xive_irq_domain, 0);
1146 xive_ipi_irq = virq;
1148 WARN_ON(request_irq(virq, xive_muxed_ipi_action,
1149 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
1152 static int xive_setup_cpu_ipi(unsigned int cpu)
1154 struct xive_cpu *xc;
1157 pr_debug("Setting up IPI for CPU %d\n", cpu);
1159 xc = per_cpu(xive_cpu, cpu);
1161 /* Check if we are already setup */
1162 if (xc->hw_ipi != XIVE_BAD_IRQ)
1165 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1166 if (xive_ops->get_ipi(cpu, xc))
1170 * Populate the IRQ data in the xive_cpu structure and
1171 * configure the HW / enable the IPIs.
1173 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1175 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1178 rc = xive_ops->configure_irq(xc->hw_ipi,
1179 get_hard_smp_processor_id(cpu),
1180 xive_irq_priority, xive_ipi_irq);
1182 pr_err("Failed to map IPI CPU %d\n", cpu);
1185 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1186 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1189 xive_do_source_set_mask(&xc->ipi_data, false);
1194 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1196 /* Disable the IPI and free the IRQ data */
1198 /* Already cleaned up ? */
1199 if (xc->hw_ipi == XIVE_BAD_IRQ)
1203 xive_do_source_set_mask(&xc->ipi_data, true);
1206 * Note: We don't call xive_cleanup_irq_data() to free
1207 * the mappings as this is called from an IPI on kexec
1208 * which is not a safe environment to call iounmap()
1211 /* Deconfigure/mask in the backend */
1212 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1213 0xff, xive_ipi_irq);
1215 /* Free the IPIs in the backend */
1216 xive_ops->put_ipi(cpu, xc);
1219 void __init xive_smp_probe(void)
1221 smp_ops->cause_ipi = xive_cause_ipi;
1223 /* Register the IPI */
1226 /* Allocate and setup IPI for the boot CPU */
1227 xive_setup_cpu_ipi(smp_processor_id());
1230 #endif /* CONFIG_SMP */
1232 static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1238 * Mark interrupts as edge sensitive by default so that resend
1239 * actually works. Will fix that up below if needed.
1241 irq_clear_status_flags(virq, IRQ_LEVEL);
1244 /* IPIs are special and come up with HW number 0 */
1247 * IPIs are marked per-cpu. We use separate HW interrupts under
1248 * the hood but associated with the same "linux" interrupt
1250 irq_set_chip_and_handler(virq, &xive_ipi_chip,
1256 rc = xive_irq_alloc_data(virq, hw);
1260 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1265 static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1267 struct irq_data *data = irq_get_irq_data(virq);
1268 unsigned int hw_irq;
1270 /* XXX Assign BAD number */
1273 hw_irq = (unsigned int)irqd_to_hwirq(data);
1275 xive_irq_free_data(virq);
1278 static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1279 const u32 *intspec, unsigned int intsize,
1280 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1283 *out_hwirq = intspec[0];
1286 * If intsize is at least 2, we look for the type in the second cell,
1287 * we assume the LSB indicates a level interrupt.
1291 *out_flags = IRQ_TYPE_LEVEL_LOW;
1293 *out_flags = IRQ_TYPE_EDGE_RISING;
1295 *out_flags = IRQ_TYPE_LEVEL_LOW;
1300 static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1301 enum irq_domain_bus_token bus_token)
1303 return xive_ops->match(node);
1306 static const struct irq_domain_ops xive_irq_domain_ops = {
1307 .match = xive_irq_domain_match,
1308 .map = xive_irq_domain_map,
1309 .unmap = xive_irq_domain_unmap,
1310 .xlate = xive_irq_domain_xlate,
1313 static void __init xive_init_host(void)
1315 xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ,
1316 &xive_irq_domain_ops, NULL);
1317 if (WARN_ON(xive_irq_domain == NULL))
1319 irq_set_default_host(xive_irq_domain);
1322 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1324 if (xc->queue[xive_irq_priority].qpage)
1325 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1328 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1332 /* We setup 1 queues for now with a 64k page */
1333 if (!xc->queue[xive_irq_priority].qpage)
1334 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1339 static int xive_prepare_cpu(unsigned int cpu)
1341 struct xive_cpu *xc;
1343 xc = per_cpu(xive_cpu, cpu);
1345 struct device_node *np;
1347 xc = kzalloc_node(sizeof(struct xive_cpu),
1348 GFP_KERNEL, cpu_to_node(cpu));
1351 np = of_get_cpu_node(cpu, NULL);
1353 xc->chip_id = of_get_ibm_chip_id(np);
1355 xc->hw_ipi = XIVE_BAD_IRQ;
1357 per_cpu(xive_cpu, cpu) = xc;
1360 /* Setup EQs if not already */
1361 return xive_setup_cpu_queues(cpu, xc);
1364 static void xive_setup_cpu(void)
1366 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1368 /* The backend might have additional things to do */
1369 if (xive_ops->setup_cpu)
1370 xive_ops->setup_cpu(smp_processor_id(), xc);
1372 /* Set CPPR to 0xff to enable flow of interrupts */
1374 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1378 void xive_smp_setup_cpu(void)
1380 pr_devel("SMP setup CPU %d\n", smp_processor_id());
1382 /* This will have already been done on the boot CPU */
1383 if (smp_processor_id() != boot_cpuid)
1388 int xive_smp_prepare_cpu(unsigned int cpu)
1392 /* Allocate per-CPU data and queues */
1393 rc = xive_prepare_cpu(cpu);
1397 /* Allocate and setup IPI for the new CPU */
1398 return xive_setup_cpu_ipi(cpu);
1401 #ifdef CONFIG_HOTPLUG_CPU
1402 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1406 /* We assume local irqs are disabled */
1407 WARN_ON(!irqs_disabled());
1409 /* Check what's already in the CPU queue */
1410 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1412 * We need to re-route that interrupt to its new destination.
1413 * First get and lock the descriptor
1415 struct irq_desc *desc = irq_to_desc(irq);
1416 struct irq_data *d = irq_desc_get_irq_data(desc);
1417 struct xive_irq_data *xd;
1418 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1421 * Ignore anything that isn't a XIVE irq and ignore
1422 * IPIs, so can just be dropped.
1424 if (d->domain != xive_irq_domain || hw_irq == 0)
1428 * The IRQ should have already been re-routed, it's just a
1429 * stale in the old queue, so re-trigger it in order to make
1430 * it reach is new destination.
1433 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1436 raw_spin_lock(&desc->lock);
1437 xd = irq_desc_get_handler_data(desc);
1440 * Clear saved_p to indicate that it's no longer pending
1442 xd->saved_p = false;
1445 * For LSIs, we EOI, this will cause a resend if it's
1446 * still asserted. Otherwise do an MSI retrigger.
1448 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1449 xive_do_source_eoi(irqd_to_hwirq(d), xd);
1451 xive_irq_retrigger(d);
1453 raw_spin_unlock(&desc->lock);
1457 void xive_smp_disable_cpu(void)
1459 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1460 unsigned int cpu = smp_processor_id();
1462 /* Migrate interrupts away from the CPU */
1463 irq_migrate_all_off_this_cpu();
1465 /* Set CPPR to 0 to disable flow of interrupts */
1467 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1469 /* Flush everything still in the queue */
1470 xive_flush_cpu_queue(cpu, xc);
1472 /* Re-enable CPPR */
1474 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1477 void xive_flush_interrupt(void)
1479 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1480 unsigned int cpu = smp_processor_id();
1482 /* Called if an interrupt occurs while the CPU is hot unplugged */
1483 xive_flush_cpu_queue(cpu, xc);
1486 #endif /* CONFIG_HOTPLUG_CPU */
1488 #endif /* CONFIG_SMP */
1490 void xive_teardown_cpu(void)
1492 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1493 unsigned int cpu = smp_processor_id();
1495 /* Set CPPR to 0 to disable flow of interrupts */
1497 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1499 if (xive_ops->teardown_cpu)
1500 xive_ops->teardown_cpu(cpu, xc);
1503 /* Get rid of IPI */
1504 xive_cleanup_cpu_ipi(cpu, xc);
1507 /* Disable and free the queues */
1508 xive_cleanup_cpu_queues(cpu, xc);
1511 void xive_shutdown(void)
1513 xive_ops->shutdown();
1516 bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
1520 xive_tima_offset = offset;
1522 xive_irq_priority = max_prio;
1524 ppc_md.get_irq = xive_get_irq;
1525 __xive_enabled = true;
1527 pr_devel("Initializing host..\n");
1530 pr_devel("Initializing boot CPU..\n");
1532 /* Allocate per-CPU data and queues */
1533 xive_prepare_cpu(smp_processor_id());
1535 /* Get ready for interrupts */
1538 pr_info("Interrupt handling initialized with %s backend\n",
1540 pr_info("Using priority %d for all interrupts\n", max_prio);
1545 __be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1547 unsigned int alloc_order;
1551 alloc_order = xive_alloc_order(queue_shift);
1552 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1554 return ERR_PTR(-ENOMEM);
1555 qpage = (__be32 *)page_address(pages);
1556 memset(qpage, 0, 1 << queue_shift);
1561 static int __init xive_off(char *arg)
1563 xive_cmdline_disabled = true;
1566 __setup("xive=off", xive_off);