2 * Freescale MPC85xx/MPC86xx RapidIO support
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <asm/machdep.h>
43 #undef DEBUG_PW /* Port-Write debugging */
45 #define RIO_PORT1_EDCSR 0x0640
46 #define RIO_PORT2_EDCSR 0x0680
47 #define RIO_PORT1_IECSR 0x10130
48 #define RIO_PORT2_IECSR 0x101B0
50 #define RIO_GCCSR 0x13c
51 #define RIO_ESCSR 0x158
52 #define ESCSR_CLEAR 0x07120204
53 #define RIO_PORT2_ESCSR 0x178
54 #define RIO_CCSR 0x15c
55 #define RIO_LTLEDCSR_IER 0x80000000
56 #define RIO_LTLEDCSR_PRT 0x01000000
57 #define IECSR_CLEAR 0x80000000
58 #define RIO_ISR_AACR 0x10120
59 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
61 #define RIWTAR_TRAD_VAL_SHIFT 12
62 #define RIWTAR_TRAD_MASK 0x00FFFFFF
63 #define RIWBAR_BADD_VAL_SHIFT 12
64 #define RIWBAR_BADD_MASK 0x003FFFFF
65 #define RIWAR_ENABLE 0x80000000
66 #define RIWAR_TGINT_LOCAL 0x00F00000
67 #define RIWAR_RDTYP_NO_SNOOP 0x00040000
68 #define RIWAR_RDTYP_SNOOP 0x00050000
69 #define RIWAR_WRTYP_NO_SNOOP 0x00004000
70 #define RIWAR_WRTYP_SNOOP 0x00005000
71 #define RIWAR_WRTYP_ALLOC 0x00006000
72 #define RIWAR_SIZE_MASK 0x0000003F
74 static DEFINE_SPINLOCK(fsl_rio_config_lock);
76 #define __fsl_read_rio_config(x, addr, err, op) \
77 __asm__ __volatile__( \
78 "1: "op" %1,0(%2)\n" \
81 ".section .fixup,\"ax\"\n" \
87 : "=r" (err), "=r" (x) \
88 : "b" (addr), "i" (-EFAULT), "0" (err))
90 void __iomem *rio_regs_win;
91 void __iomem *rmu_regs_win;
92 resource_size_t rio_law_start;
94 struct fsl_rio_dbell *dbell;
95 struct fsl_rio_pw *pw;
98 int fsl_rio_mcheck_exception(struct pt_regs *regs)
100 const struct exception_table_entry *entry;
101 unsigned long reason;
106 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
107 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
108 /* Check if we are prepared to handle this fault */
109 entry = search_exception_tables(regs->nip);
111 pr_debug("RIO: %s - MC Exception handled\n",
113 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
116 regs->nip = extable_fixup(entry);
123 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
127 * fsl_local_config_read - Generate a MPC85xx local config space read
128 * @mport: RapidIO master port info
129 * @index: ID of RapdiIO interface
130 * @offset: Offset into configuration space
131 * @len: Length (in bytes) of the maintenance transaction
132 * @data: Value to be read into
134 * Generates a MPC85xx local configuration space read. Returns %0 on
135 * success or %-EINVAL on failure.
137 static int fsl_local_config_read(struct rio_mport *mport,
138 int index, u32 offset, int len, u32 *data)
140 struct rio_priv *priv = mport->priv;
141 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
143 *data = in_be32(priv->regs_win + offset);
149 * fsl_local_config_write - Generate a MPC85xx local config space write
150 * @mport: RapidIO master port info
151 * @index: ID of RapdiIO interface
152 * @offset: Offset into configuration space
153 * @len: Length (in bytes) of the maintenance transaction
154 * @data: Value to be written
156 * Generates a MPC85xx local configuration space write. Returns %0 on
157 * success or %-EINVAL on failure.
159 static int fsl_local_config_write(struct rio_mport *mport,
160 int index, u32 offset, int len, u32 data)
162 struct rio_priv *priv = mport->priv;
164 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
165 index, offset, data);
166 out_be32(priv->regs_win + offset, data);
172 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
173 * @mport: RapidIO master port info
174 * @index: ID of RapdiIO interface
175 * @destid: Destination ID of transaction
176 * @hopcount: Number of hops to target device
177 * @offset: Offset into configuration space
178 * @len: Length (in bytes) of the maintenance transaction
179 * @val: Location to be read into
181 * Generates a MPC85xx read maintenance transaction. Returns %0 on
182 * success or %-EINVAL on failure.
185 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
186 u8 hopcount, u32 offset, int len, u32 *val)
188 struct rio_priv *priv = mport->priv;
194 ("fsl_rio_config_read:"
195 " index %d destid %d hopcount %d offset %8.8x len %d\n",
196 index, destid, hopcount, offset, len);
198 /* 16MB maintenance window possible */
199 /* allow only aligned access to maintenance registers */
200 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
203 spin_lock_irqsave(&fsl_rio_config_lock, flags);
205 out_be32(&priv->maint_atmu_regs->rowtar,
206 (destid << 22) | (hopcount << 12) | (offset >> 12));
207 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
209 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
212 __fsl_read_rio_config(rval, data, err, "lbz");
215 __fsl_read_rio_config(rval, data, err, "lhz");
218 __fsl_read_rio_config(rval, data, err, "lwz");
221 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
226 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
227 err, destid, hopcount, offset);
230 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
237 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
238 * @mport: RapidIO master port info
239 * @index: ID of RapdiIO interface
240 * @destid: Destination ID of transaction
241 * @hopcount: Number of hops to target device
242 * @offset: Offset into configuration space
243 * @len: Length (in bytes) of the maintenance transaction
244 * @val: Value to be written
246 * Generates an MPC85xx write maintenance transaction. Returns %0 on
247 * success or %-EINVAL on failure.
250 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
251 u8 hopcount, u32 offset, int len, u32 val)
253 struct rio_priv *priv = mport->priv;
259 ("fsl_rio_config_write:"
260 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
261 index, destid, hopcount, offset, len, val);
263 /* 16MB maintenance windows possible */
264 /* allow only aligned access to maintenance registers */
265 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
268 spin_lock_irqsave(&fsl_rio_config_lock, flags);
270 out_be32(&priv->maint_atmu_regs->rowtar,
271 (destid << 22) | (hopcount << 12) | (offset >> 12));
272 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
274 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
277 out_8((u8 *) data, val);
280 out_be16((u16 *) data, val);
283 out_be32((u32 *) data, val);
288 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
293 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
297 /* close inbound windows */
298 for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
299 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
302 int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
303 u64 rstart, u64 size, u32 flags)
305 struct rio_priv *priv = mport->priv;
307 unsigned int base_size_log;
308 u64 win_start, win_end;
312 if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
315 base_size_log = ilog2(size);
316 base_size = 1 << base_size_log;
318 /* check if addresses are aligned with the window size */
319 if (lstart & (base_size - 1))
321 if (rstart & (base_size - 1))
324 /* check for conflicting ranges */
325 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
326 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
327 if ((riwar & RIWAR_ENABLE) == 0)
329 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
330 << RIWBAR_BADD_VAL_SHIFT;
331 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
332 if (rstart < win_end && (rstart + size) > win_start)
336 /* find unused atmu */
337 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
338 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
339 if ((riwar & RIWAR_ENABLE) == 0)
342 if (i >= RIO_INB_ATMU_COUNT)
345 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
346 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
347 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
348 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
353 void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
355 u32 win_start_shift, base_start_shift;
356 struct rio_priv *priv = mport->priv;
360 /* skip default window */
361 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
362 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
363 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
364 if ((riwar & RIWAR_ENABLE) == 0)
367 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
368 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
369 if (win_start_shift == base_start_shift) {
370 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
376 void fsl_rio_port_error_handler(int offset)
378 /*XXX: Error recovery is not implemented, we just clear errors */
379 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
382 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
383 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
384 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
386 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
387 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
388 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
391 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
396 switch (ccsr >> 30) {
407 dev_info(dev, "Hardware port width: %s\n", str);
409 switch ((ccsr >> 27) & 7) {
411 str = "Single-lane 0";
414 str = "Single-lane 2";
423 dev_info(dev, "Training connection status: %s\n", str);
426 if (!(ccsr & 0x80000000))
427 dev_info(dev, "Output port operating in 8-bit mode\n");
428 if (!(ccsr & 0x08000000))
429 dev_info(dev, "Input port operating in 8-bit mode\n");
434 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
435 * @dev: platform_device pointer
437 * Initializes MPC85xx RapidIO hardware interface, configures
438 * master port with system-specific info, and registers the
439 * master port with the RapidIO subsystem.
441 int fsl_rio_setup(struct platform_device *dev)
444 struct rio_mport *port;
445 struct rio_priv *priv;
447 const u32 *dt_range, *cell, *port_index;
448 u32 active_ports = 0;
449 struct resource regs, rmu_regs;
450 struct device_node *np, *rmu_node;
453 u64 range_start, range_size;
457 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
459 if (!dev->dev.of_node) {
460 dev_err(&dev->dev, "Device OF-Node is NULL");
464 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
466 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
470 dev_info(&dev->dev, "Of-device full name %pOF\n",
472 dev_info(&dev->dev, "Regs: %pR\n", ®s);
474 rio_regs_win = ioremap(regs.start, resource_size(®s));
476 dev_err(&dev->dev, "Unable to map rio register window\n");
481 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
486 ops->lcread = fsl_local_config_read;
487 ops->lcwrite = fsl_local_config_write;
488 ops->cread = fsl_rio_config_read;
489 ops->cwrite = fsl_rio_config_write;
490 ops->dsend = fsl_rio_doorbell_send;
491 ops->pwenable = fsl_rio_pw_enable;
492 ops->open_outb_mbox = fsl_open_outb_mbox;
493 ops->open_inb_mbox = fsl_open_inb_mbox;
494 ops->close_outb_mbox = fsl_close_outb_mbox;
495 ops->close_inb_mbox = fsl_close_inb_mbox;
496 ops->add_outb_message = fsl_add_outb_message;
497 ops->add_inb_buffer = fsl_add_inb_buffer;
498 ops->get_inb_message = fsl_get_inb_message;
499 ops->map_inb = fsl_map_inb_mem;
500 ops->unmap_inb = fsl_unmap_inb_mem;
502 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
504 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
508 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
510 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
514 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
516 dev_err(&dev->dev, "Unable to map rmu register window\n");
520 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
525 /*set up doobell node*/
526 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
528 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
532 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
534 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
538 dbell->dev = &dev->dev;
539 dbell->bellirq = irq_of_parse_and_map(np, 1);
540 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
542 aw = of_n_addr_cells(np);
543 dt_range = of_get_property(np, "reg", &rlen);
545 pr_err("%pOF: unable to find 'reg' property\n",
550 range_start = of_read_number(dt_range, aw);
551 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
554 /*set up port write node*/
555 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
557 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
561 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
563 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
568 pw->pwirq = irq_of_parse_and_map(np, 0);
569 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
570 aw = of_n_addr_cells(np);
571 dt_range = of_get_property(np, "reg", &rlen);
573 pr_err("%pOF: unable to find 'reg' property\n",
578 range_start = of_read_number(dt_range, aw);
579 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
581 /*set up ports node*/
582 for_each_child_of_node(dev->dev.of_node, np) {
583 port_index = of_get_property(np, "cell-index", NULL);
585 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
590 dt_range = of_get_property(np, "ranges", &rlen);
592 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
597 /* Get node address wide */
598 cell = of_get_property(np, "#address-cells", NULL);
602 aw = of_n_addr_cells(np);
603 /* Get node size wide */
604 cell = of_get_property(np, "#size-cells", NULL);
608 sw = of_n_size_cells(np);
609 /* Get parent address wide wide */
610 paw = of_n_addr_cells(np);
611 range_start = of_read_number(dt_range + aw, paw);
612 range_size = of_read_number(dt_range + aw + paw, sw);
614 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
615 np, range_start, range_size);
617 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
621 rc = rio_mport_initialize(port);
628 port->index = (unsigned char)i;
630 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
632 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
637 INIT_LIST_HEAD(&port->dbells);
638 port->iores.start = range_start;
639 port->iores.end = port->iores.start + range_size - 1;
640 port->iores.flags = IORESOURCE_MEM;
641 port->iores.name = "rio_io_win";
643 if (request_resource(&iomem_resource, &port->iores) < 0) {
644 dev_err(&dev->dev, "RIO: Error requesting master port region"
645 " 0x%016llx-0x%016llx\n",
646 (u64)port->iores.start, (u64)port->iores.end);
651 sprintf(port->name, "RIO mport %d", i);
653 priv->dev = &dev->dev;
654 port->dev.parent = &dev->dev;
657 port->phys_efptr = 0x100;
659 priv->regs_win = rio_regs_win;
661 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
663 /* Checking the port training status */
664 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
665 dev_err(&dev->dev, "Port %d is not ready. "
666 "Try to restart connection...\n", i);
668 out_be32(priv->regs_win
669 + RIO_CCSR + i*0x20, 0);
671 setbits32(priv->regs_win
672 + RIO_CCSR + i*0x20, 0x02000000);
674 setbits32(priv->regs_win
675 + RIO_CCSR + i*0x20, 0x00600000);
677 if (in_be32((priv->regs_win
678 + RIO_ESCSR + i*0x20)) & 1) {
680 "Port %d restart failed.\n", i);
681 release_resource(&port->iores);
686 dev_info(&dev->dev, "Port %d restart success!\n", i);
688 fsl_rio_info(&dev->dev, ccsr);
690 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
691 & RIO_PEF_CTLS) >> 4;
692 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
693 port->sys_size ? 65536 : 256);
695 if (port->host_deviceid >= 0)
696 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
697 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
699 out_be32(priv->regs_win + RIO_GCCSR,
700 RIO_PORT_GEN_MASTER);
702 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
703 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
704 RIO_ATMU_REGS_PORT2_OFFSET));
706 priv->maint_atmu_regs = priv->atmu_regs + 1;
707 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
709 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
710 RIO_INB_ATMU_REGS_PORT2_OFFSET));
712 /* Set to receive packets with any dest ID */
713 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
716 /* Configure maintenance transaction window */
717 out_be32(&priv->maint_atmu_regs->rowbar,
718 port->iores.start >> 12);
719 out_be32(&priv->maint_atmu_regs->rowar,
720 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
722 priv->maint_win = ioremap(port->iores.start,
725 rio_law_start = range_start;
727 fsl_rio_setup_rmu(port, rmu_np[i]);
728 fsl_rio_inbound_mem_init(priv);
730 dbell->mport[i] = port;
733 if (rio_register_mport(port)) {
734 release_resource(&port->iores);
747 fsl_rio_doorbell_init(dbell);
748 fsl_rio_port_write_init(pw);
758 iounmap(rmu_regs_win);
763 iounmap(rio_regs_win);
769 /* The probe function for RapidIO peer-to-peer network.
771 static int fsl_of_rio_rpn_probe(struct platform_device *dev)
773 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
776 return fsl_rio_setup(dev);
779 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
781 .compatible = "fsl,srio",
786 static struct platform_driver fsl_of_rio_rpn_driver = {
788 .name = "fsl-of-rio",
789 .of_match_table = fsl_of_rio_rpn_ids,
791 .probe = fsl_of_rio_rpn_probe,
794 static __init int fsl_of_rio_rpn_init(void)
796 return platform_driver_register(&fsl_of_rio_rpn_driver);
799 subsys_initcall(fsl_of_rio_rpn_init);