arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <linux/rculist.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/rtas.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/firmware.h>
  48 #include <asm/tce.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/udbg.h>
  51 #include <asm/mmzone.h>
  52 #include <asm/plpar_wrappers.h>
  53
  54 #include "pseries.h"
  55
  56 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  57 {
  58         struct iommu_table_group *table_group = NULL;
  59         struct iommu_table *tbl = NULL;
  60         struct iommu_table_group_link *tgl = NULL;
  61
  62         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  63                            node);
  64         if (!table_group)
  65                 goto fail_exit;
  66
  67         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  68         if (!tbl)
  69                 goto fail_exit;
  70
  71         tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
  72                         node);
  73         if (!tgl)
  74                 goto fail_exit;
  75
  76         INIT_LIST_HEAD_RCU(&tbl->it_group_list);
  77         tgl->table_group = table_group;
  78         list_add_rcu(&tgl->next, &tbl->it_group_list);
  79
  80         table_group->tables[0] = tbl;
  81
  82         return table_group;
  83
  84 fail_exit:
  85         kfree(tgl);
  86         kfree(table_group);
  87         kfree(tbl);
  88
  89         return NULL;
  90 }
  91
  92 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  93                 const char *node_name)
  94 {
  95         struct iommu_table *tbl;
  96 #ifdef CONFIG_IOMMU_API
  97         struct iommu_table_group_link *tgl;
  98 #endif
  99
 100         if (!table_group)
 101                 return;
 102
 103         tbl = table_group->tables[0];
 104 #ifdef CONFIG_IOMMU_API
 105         tgl = list_first_entry_or_null(&tbl->it_group_list,
 106                         struct iommu_table_group_link, next);
 107
 108         WARN_ON_ONCE(!tgl);
 109         if (tgl) {
 110                 list_del_rcu(&tgl->next);
 111                 kfree(tgl);
 112         }
 113         if (table_group->group) {
 114                 iommu_group_put(table_group->group);
 115                 BUG_ON(table_group->group);
 116         }
 117 #endif
 118         iommu_free_table(tbl, node_name);
 119
 120         kfree(table_group);
 121 }
 122
 123 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 124                               long npages, unsigned long uaddr,
 125                               enum dma_data_direction direction,
 126                               unsigned long attrs)
 127 {
 128         u64 proto_tce;
 129         __be64 *tcep, *tces;
 130         u64 rpn;
 131
 132         proto_tce = TCE_PCI_READ; // Read allowed
 133
 134         if (direction != DMA_TO_DEVICE)
 135                 proto_tce |= TCE_PCI_WRITE;
 136
 137         tces = tcep = ((__be64 *)tbl->it_base) + index;
 138
 139         while (npages--) {
 140                 /* can't move this out since we might cross MEMBLOCK boundary */
 141                 rpn = __pa(uaddr) >> TCE_SHIFT;
 142                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 143
 144                 uaddr += TCE_PAGE_SIZE;
 145                 tcep++;
 146         }
 147         return 0;
 148 }
 149
 150
 151 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 152 {
 153         __be64 *tcep, *tces;
 154
 155         tces = tcep = ((__be64 *)tbl->it_base) + index;
 156
 157         while (npages--)
 158                 *(tcep++) = 0;
 159 }
 160
 161 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 162 {
 163         __be64 *tcep;
 164
 165         tcep = ((__be64 *)tbl->it_base) + index;
 166
 167         return be64_to_cpu(*tcep);
 168 }
 169
 170 static void tce_free_pSeriesLP(unsigned long liobn, long, long);
 171 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 172
 173 static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift,
 174                                 long npages, unsigned long uaddr,
 175                                 enum dma_data_direction direction,
 176                                 unsigned long attrs)
 177 {
 178         u64 rc = 0;
 179         u64 proto_tce, tce;
 180         u64 rpn;
 181         int ret = 0;
 182         long tcenum_start = tcenum, npages_start = npages;
 183
 184         rpn = __pa(uaddr) >> tceshift;
 185         proto_tce = TCE_PCI_READ;
 186         if (direction != DMA_TO_DEVICE)
 187                 proto_tce |= TCE_PCI_WRITE;
 188
 189         while (npages--) {
 190                 tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift;
 191                 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce);
 192
 193                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 194                         ret = (int)rc;
 195                         tce_free_pSeriesLP(liobn, tcenum_start,
 196                                            (npages_start - (npages + 1)));
 197                         break;
 198                 }
 199
 200                 if (rc && printk_ratelimit()) {
 201                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 202                         printk("\tindex   = 0x%llx\n", (u64)liobn);
 203                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 204                         printk("\ttce val = 0x%llx\n", tce );
 205                         dump_stack();
 206                 }
 207
 208                 tcenum++;
 209                 rpn++;
 210         }
 211         return ret;
 212 }
 213
 214 static DEFINE_PER_CPU(__be64 *, tce_page);
 215
 216 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 217                                      long npages, unsigned long uaddr,
 218                                      enum dma_data_direction direction,
 219                                      unsigned long attrs)
 220 {
 221         u64 rc = 0;
 222         u64 proto_tce;
 223         __be64 *tcep;
 224         u64 rpn;
 225         long l, limit;
 226         long tcenum_start = tcenum, npages_start = npages;
 227         int ret = 0;
 228         unsigned long flags;
 229
 230         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 231                 return tce_build_pSeriesLP(tbl->it_index, tcenum,
 232                                            tbl->it_page_shift, npages, uaddr,
 233                                            direction, attrs);
 234         }
 235
 236         local_irq_save(flags);  /* to protect tcep and the page behind it */
 237
 238         tcep = __this_cpu_read(tce_page);
 239
 240         /* This is safe to do since interrupts are off when we're called
 241          * from iommu_alloc{,_sg}()
 242          */
 243         if (!tcep) {
 244                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 245                 /* If allocation fails, fall back to the loop implementation */
 246                 if (!tcep) {
 247                         local_irq_restore(flags);
 248                         return tce_build_pSeriesLP(tbl->it_index, tcenum,
 249                                         tbl->it_page_shift,
 250                                         npages, uaddr, direction, attrs);
 251                 }
 252                 __this_cpu_write(tce_page, tcep);
 253         }
 254
 255         rpn = __pa(uaddr) >> TCE_SHIFT;
 256         proto_tce = TCE_PCI_READ;
 257         if (direction != DMA_TO_DEVICE)
 258                 proto_tce |= TCE_PCI_WRITE;
 259
 260         /* We can map max one pageful of TCEs at a time */
 261         do {
 262                 /*
 263                  * Set up the page with TCE data, looping through and setting
 264                  * the values.
 265                  */
 266                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 267
 268                 for (l = 0; l < limit; l++) {
 269                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 270                         rpn++;
 271                 }
 272
 273                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 274                                             (u64)tcenum << 12,
 275                                             (u64)__pa(tcep),
 276                                             limit);
 277
 278                 npages -= limit;
 279                 tcenum += limit;
 280         } while (npages > 0 && !rc);
 281
 282         local_irq_restore(flags);
 283
 284         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 285                 ret = (int)rc;
 286                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 287                                         (npages_start - (npages + limit)));
 288                 return ret;
 289         }
 290
 291         if (rc && printk_ratelimit()) {
 292                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 293                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 294                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 295                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 296                 dump_stack();
 297         }
 298         return ret;
 299 }
 300
 301 static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages)
 302 {
 303         u64 rc;
 304
 305         while (npages--) {
 306                 rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0);
 307
 308                 if (rc && printk_ratelimit()) {
 309                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 310                         printk("\tindex   = 0x%llx\n", (u64)liobn);
 311                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 312                         dump_stack();
 313                 }
 314
 315                 tcenum++;
 316         }
 317 }
 318
 319
 320 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 321 {
 322         u64 rc;
 323
 324         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 325                 return tce_free_pSeriesLP(tbl->it_index, tcenum, npages);
 326
 327         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 328
 329         if (rc && printk_ratelimit()) {
 330                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 331                 printk("\trc      = %lld\n", rc);
 332                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 333                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 334                 dump_stack();
 335         }
 336 }
 337
 338 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 339 {
 340         u64 rc;
 341         unsigned long tce_ret;
 342
 343         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 344
 345         if (rc && printk_ratelimit()) {
 346                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 347                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 348                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 349                 dump_stack();
 350         }
 351
 352         return tce_ret;
 353 }
 354
 355 /* this is compatible with cells for the device tree property */
 356 struct dynamic_dma_window_prop {
 357         __be32  liobn;          /* tce table number */
 358         __be64  dma_base;       /* address hi,lo */
 359         __be32  tce_shift;      /* ilog2(tce_page_size) */
 360         __be32  window_shift;   /* ilog2(tce_window_size) */
 361 };
 362
 363 struct direct_window {
 364         struct device_node *device;
 365         const struct dynamic_dma_window_prop *prop;
 366         struct list_head list;
 367 };
 368
 369 /* Dynamic DMA Window support */
 370 struct ddw_query_response {
 371         u32 windows_available;
 372         u32 largest_available_block;
 373         u32 page_size;
 374         u32 migration_capable;
 375 };
 376
 377 struct ddw_create_response {
 378         u32 liobn;
 379         u32 addr_hi;
 380         u32 addr_lo;
 381 };
 382
 383 static LIST_HEAD(direct_window_list);
 384 /* prevents races between memory on/offline and window creation */
 385 static DEFINE_SPINLOCK(direct_window_list_lock);
 386 /* protects initializing window twice for same device */
 387 static DEFINE_MUTEX(direct_window_init_mutex);
 388 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 389
 390 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 391                                         unsigned long num_pfn, const void *arg)
 392 {
 393         const struct dynamic_dma_window_prop *maprange = arg;
 394         int rc;
 395         u64 tce_size, num_tce, dma_offset, next;
 396         u32 tce_shift;
 397         long limit;
 398
 399         tce_shift = be32_to_cpu(maprange->tce_shift);
 400         tce_size = 1ULL << tce_shift;
 401         next = start_pfn << PAGE_SHIFT;
 402         num_tce = num_pfn << PAGE_SHIFT;
 403
 404         /* round back to the beginning of the tce page size */
 405         num_tce += next & (tce_size - 1);
 406         next &= ~(tce_size - 1);
 407
 408         /* covert to number of tces */
 409         num_tce |= tce_size - 1;
 410         num_tce >>= tce_shift;
 411
 412         do {
 413                 /*
 414                  * Set up the page with TCE data, looping through and setting
 415                  * the values.
 416                  */
 417                 limit = min_t(long, num_tce, 512);
 418                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 419
 420                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 421                                              dma_offset,
 422                                              0, limit);
 423                 next += limit * tce_size;
 424                 num_tce -= limit;
 425         } while (num_tce > 0 && !rc);
 426
 427         return rc;
 428 }
 429
 430 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 431                                         unsigned long num_pfn, const void *arg)
 432 {
 433         const struct dynamic_dma_window_prop *maprange = arg;
 434         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 435         __be64 *tcep;
 436         u32 tce_shift;
 437         u64 rc = 0;
 438         long l, limit;
 439
 440         if (!firmware_has_feature(FW_FEATURE_MULTITCE)) {
 441                 unsigned long tceshift = be32_to_cpu(maprange->tce_shift);
 442                 unsigned long dmastart = (start_pfn << PAGE_SHIFT) +
 443                                 be64_to_cpu(maprange->dma_base);
 444                 unsigned long tcenum = dmastart >> tceshift;
 445                 unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift;
 446                 void *uaddr = __va(start_pfn << PAGE_SHIFT);
 447
 448                 return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn),
 449                                 tcenum, tceshift, npages, (unsigned long) uaddr,
 450                                 DMA_BIDIRECTIONAL, 0);
 451         }
 452
 453         local_irq_disable();    /* to protect tcep and the page behind it */
 454         tcep = __this_cpu_read(tce_page);
 455
 456         if (!tcep) {
 457                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 458                 if (!tcep) {
 459                         local_irq_enable();
 460                         return -ENOMEM;
 461                 }
 462                 __this_cpu_write(tce_page, tcep);
 463         }
 464
 465         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 466
 467         liobn = (u64)be32_to_cpu(maprange->liobn);
 468         tce_shift = be32_to_cpu(maprange->tce_shift);
 469         tce_size = 1ULL << tce_shift;
 470         next = start_pfn << PAGE_SHIFT;
 471         num_tce = num_pfn << PAGE_SHIFT;
 472
 473         /* round back to the beginning of the tce page size */
 474         num_tce += next & (tce_size - 1);
 475         next &= ~(tce_size - 1);
 476
 477         /* covert to number of tces */
 478         num_tce |= tce_size - 1;
 479         num_tce >>= tce_shift;
 480
 481         /* We can map max one pageful of TCEs at a time */
 482         do {
 483                 /*
 484                  * Set up the page with TCE data, looping through and setting
 485                  * the values.
 486                  */
 487                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 488                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 489
 490                 for (l = 0; l < limit; l++) {
 491                         tcep[l] = cpu_to_be64(proto_tce | next);
 492                         next += tce_size;
 493                 }
 494
 495                 rc = plpar_tce_put_indirect(liobn,
 496                                             dma_offset,
 497                                             (u64)__pa(tcep),
 498                                             limit);
 499
 500                 num_tce -= limit;
 501         } while (num_tce > 0 && !rc);
 502
 503         /* error cleanup: caller will clear whole range */
 504
 505         local_irq_enable();
 506         return rc;
 507 }
 508
 509 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 510                 unsigned long num_pfn, void *arg)
 511 {
 512         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 513 }
 514
 515 static void iommu_table_setparms(struct pci_controller *phb,
 516                                  struct device_node *dn,
 517                                  struct iommu_table *tbl)
 518 {
 519         struct device_node *node;
 520         const unsigned long *basep;
 521         const u32 *sizep;
 522
 523         node = phb->dn;
 524
 525         basep = of_get_property(node, "linux,tce-base", NULL);
 526         sizep = of_get_property(node, "linux,tce-size", NULL);
 527         if (basep == NULL || sizep == NULL) {
 528                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 529                                 "missing tce entries !\n", dn->full_name);
 530                 return;
 531         }
 532
 533         tbl->it_base = (unsigned long)__va(*basep);
 534
 535         if (!is_kdump_kernel())
 536                 memset((void *)tbl->it_base, 0, *sizep);
 537
 538         tbl->it_busno = phb->bus->number;
 539         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 540
 541         /* Units of tce entries */
 542         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 543
 544         /* Test if we are going over 2GB of DMA space */
 545         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 546                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 547                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 548         }
 549
 550         phb->dma_window_base_cur += phb->dma_window_size;
 551
 552         /* Set the tce table size - measured in entries */
 553         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 554
 555         tbl->it_index = 0;
 556         tbl->it_blocksize = 16;
 557         tbl->it_type = TCE_PCI;
 558 }
 559
 560 /*
 561  * iommu_table_setparms_lpar
 562  *
 563  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 564  */
 565 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 566                                       struct device_node *dn,
 567                                       struct iommu_table *tbl,
 568                                       const __be32 *dma_window)
 569 {
 570         unsigned long offset, size;
 571
 572         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 573
 574         tbl->it_busno = phb->bus->number;
 575         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 576         tbl->it_base   = 0;
 577         tbl->it_blocksize  = 16;
 578         tbl->it_type = TCE_PCI;
 579         tbl->it_offset = offset >> tbl->it_page_shift;
 580         tbl->it_size = size >> tbl->it_page_shift;
 581 }
 582
 583 struct iommu_table_ops iommu_table_pseries_ops = {
 584         .set = tce_build_pSeries,
 585         .clear = tce_free_pSeries,
 586         .get = tce_get_pseries
 587 };
 588
 589 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 590 {
 591         struct device_node *dn;
 592         struct iommu_table *tbl;
 593         struct device_node *isa_dn, *isa_dn_orig;
 594         struct device_node *tmp;
 595         struct pci_dn *pci;
 596         int children;
 597
 598         dn = pci_bus_to_OF_node(bus);
 599
 600         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 601
 602         if (bus->self) {
 603                 /* This is not a root bus, any setup will be done for the
 604                  * device-side of the bridge in iommu_dev_setup_pSeries().
 605                  */
 606                 return;
 607         }
 608         pci = PCI_DN(dn);
 609
 610         /* Check if the ISA bus on the system is under
 611          * this PHB.
 612          */
 613         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 614
 615         while (isa_dn && isa_dn != dn)
 616                 isa_dn = isa_dn->parent;
 617
 618         of_node_put(isa_dn_orig);
 619
 620         /* Count number of direct PCI children of the PHB. */
 621         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 622                 children++;
 623
 624         pr_debug("Children: %d\n", children);
 625
 626         /* Calculate amount of DMA window per slot. Each window must be
 627          * a power of two (due to pci_alloc_consistent requirements).
 628          *
 629          * Keep 256MB aside for PHBs with ISA.
 630          */
 631
 632         if (!isa_dn) {
 633                 /* No ISA/IDE - just set window size and return */
 634                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 635
 636                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 637                         pci->phb->dma_window_size >>= 1;
 638                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 639                          pci->phb->dma_window_size);
 640                 pci->phb->dma_window_base_cur = 0;
 641
 642                 return;
 643         }
 644
 645         /* If we have ISA, then we probably have an IDE
 646          * controller too. Allocate a 128MB table but
 647          * skip the first 128MB to avoid stepping on ISA
 648          * space.
 649          */
 650         pci->phb->dma_window_size = 0x8000000ul;
 651         pci->phb->dma_window_base_cur = 0x8000000ul;
 652
 653         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 654         tbl = pci->table_group->tables[0];
 655
 656         iommu_table_setparms(pci->phb, dn, tbl);
 657         tbl->it_ops = &iommu_table_pseries_ops;
 658         iommu_init_table(tbl, pci->phb->node);
 659         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 660
 661         /* Divide the rest (1.75GB) among the children */
 662         pci->phb->dma_window_size = 0x80000000ul;
 663         while (pci->phb->dma_window_size * children > 0x70000000ul)
 664                 pci->phb->dma_window_size >>= 1;
 665
 666         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 667 }
 668
 669 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 670         .set = tce_buildmulti_pSeriesLP,
 671         .clear = tce_freemulti_pSeriesLP,
 672         .get = tce_get_pSeriesLP
 673 };
 674
 675 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 676 {
 677         struct iommu_table *tbl;
 678         struct device_node *dn, *pdn;
 679         struct pci_dn *ppci;
 680         const __be32 *dma_window = NULL;
 681
 682         dn = pci_bus_to_OF_node(bus);
 683
 684         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 685                  dn->full_name);
 686
 687         /* Find nearest ibm,dma-window, walking up the device tree */
 688         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 689                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 690                 if (dma_window != NULL)
 691                         break;
 692         }
 693
 694         if (dma_window == NULL) {
 695                 pr_debug("  no ibm,dma-window property !\n");
 696                 return;
 697         }
 698
 699         ppci = PCI_DN(pdn);
 700
 701         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 702                  pdn->full_name, ppci->table_group);
 703
 704         if (!ppci->table_group) {
 705                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 706                 tbl = ppci->table_group->tables[0];
 707                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 708                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 709                 iommu_init_table(tbl, ppci->phb->node);
 710                 iommu_register_group(ppci->table_group,
 711                                 pci_domain_nr(bus), 0);
 712                 pr_debug("  created table: %p\n", ppci->table_group);
 713         }
 714 }
 715
 716
 717 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 718 {
 719         struct device_node *dn;
 720         struct iommu_table *tbl;
 721
 722         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 723
 724         dn = dev->dev.of_node;
 725
 726         /* If we're the direct child of a root bus, then we need to allocate
 727          * an iommu table ourselves. The bus setup code should have setup
 728          * the window sizes already.
 729          */
 730         if (!dev->bus->self) {
 731                 struct pci_controller *phb = PCI_DN(dn)->phb;
 732
 733                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 734                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 735                 tbl = PCI_DN(dn)->table_group->tables[0];
 736                 iommu_table_setparms(phb, dn, tbl);
 737                 tbl->it_ops = &iommu_table_pseries_ops;
 738                 iommu_init_table(tbl, phb->node);
 739                 iommu_register_group(PCI_DN(dn)->table_group,
 740                                 pci_domain_nr(phb->bus), 0);
 741                 set_iommu_table_base(&dev->dev, tbl);
 742                 iommu_add_device(&dev->dev);
 743                 return;
 744         }
 745
 746         /* If this device is further down the bus tree, search upwards until
 747          * an already allocated iommu table is found and use that.
 748          */
 749
 750         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 751                 dn = dn->parent;
 752
 753         if (dn && PCI_DN(dn)) {
 754                 set_iommu_table_base(&dev->dev,
 755                                 PCI_DN(dn)->table_group->tables[0]);
 756                 iommu_add_device(&dev->dev);
 757         } else
 758                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 759                        pci_name(dev));
 760 }
 761
 762 static int __read_mostly disable_ddw;
 763
 764 static int __init disable_ddw_setup(char *str)
 765 {
 766         disable_ddw = 1;
 767         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 768
 769         return 0;
 770 }
 771
 772 early_param("disable_ddw", disable_ddw_setup);
 773
 774 static void remove_ddw(struct device_node *np, bool remove_prop)
 775 {
 776         struct dynamic_dma_window_prop *dwp;
 777         struct property *win64;
 778         u32 ddw_avail[3];
 779         u64 liobn;
 780         int ret = 0;
 781
 782         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 783                                          &ddw_avail[0], 3);
 784
 785         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 786         if (!win64)
 787                 return;
 788
 789         if (ret || win64->length < sizeof(*dwp))
 790                 goto delprop;
 791
 792         dwp = win64->value;
 793         liobn = (u64)be32_to_cpu(dwp->liobn);
 794
 795         /* clear the whole window, note the arg is in kernel pages */
 796         ret = tce_clearrange_multi_pSeriesLP(0,
 797                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 798         if (ret)
 799                 pr_warning("%s failed to clear tces in window.\n",
 800                          np->full_name);
 801         else
 802                 pr_debug("%s successfully cleared tces in window.\n",
 803                          np->full_name);
 804
 805         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 806         if (ret)
 807                 pr_warning("%s: failed to remove direct window: rtas returned "
 808                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 809                         np->full_name, ret, ddw_avail[2], liobn);
 810         else
 811                 pr_debug("%s: successfully removed direct window: rtas returned "
 812                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 813                         np->full_name, ret, ddw_avail[2], liobn);
 814
 815 delprop:
 816         if (remove_prop)
 817                 ret = of_remove_property(np, win64);
 818         if (ret)
 819                 pr_warning("%s: failed to remove direct window property: %d\n",
 820                         np->full_name, ret);
 821 }
 822
 823 static u64 find_existing_ddw(struct device_node *pdn)
 824 {
 825         struct direct_window *window;
 826         const struct dynamic_dma_window_prop *direct64;
 827         u64 dma_addr = 0;
 828
 829         spin_lock(&direct_window_list_lock);
 830         /* check if we already created a window and dupe that config if so */
 831         list_for_each_entry(window, &direct_window_list, list) {
 832                 if (window->device == pdn) {
 833                         direct64 = window->prop;
 834                         dma_addr = be64_to_cpu(direct64->dma_base);
 835                         break;
 836                 }
 837         }
 838         spin_unlock(&direct_window_list_lock);
 839
 840         return dma_addr;
 841 }
 842
 843 static int find_existing_ddw_windows(void)
 844 {
 845         int len;
 846         struct device_node *pdn;
 847         struct direct_window *window;
 848         const struct dynamic_dma_window_prop *direct64;
 849
 850         if (!firmware_has_feature(FW_FEATURE_LPAR))
 851                 return 0;
 852
 853         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 854                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 855                 if (!direct64)
 856                         continue;
 857
 858                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 859                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 860                         kfree(window);
 861                         remove_ddw(pdn, true);
 862                         continue;
 863                 }
 864
 865                 window->device = pdn;
 866                 window->prop = direct64;
 867                 spin_lock(&direct_window_list_lock);
 868                 list_add(&window->list, &direct_window_list);
 869                 spin_unlock(&direct_window_list_lock);
 870         }
 871
 872         return 0;
 873 }
 874 machine_arch_initcall(pseries, find_existing_ddw_windows);
 875
 876 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 877                         struct ddw_query_response *query)
 878 {
 879         struct device_node *dn;
 880         struct pci_dn *pdn;
 881         u32 cfg_addr;
 882         u64 buid;
 883         int ret;
 884
 885         /*
 886          * Get the config address and phb buid of the PE window.
 887          * Rely on eeh to retrieve this for us.
 888          * Retrieve them from the pci device, not the node with the
 889          * dma-window property
 890          */
 891         dn = pci_device_to_OF_node(dev);
 892         pdn = PCI_DN(dn);
 893         buid = pdn->phb->buid;
 894         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 895
 896         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 897                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 898         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 899                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 900                 BUID_LO(buid), ret);
 901         return ret;
 902 }
 903
 904 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 905                         struct ddw_create_response *create, int page_shift,
 906                         int window_shift)
 907 {
 908         struct device_node *dn;
 909         struct pci_dn *pdn;
 910         u32 cfg_addr;
 911         u64 buid;
 912         int ret;
 913
 914         /*
 915          * Get the config address and phb buid of the PE window.
 916          * Rely on eeh to retrieve this for us.
 917          * Retrieve them from the pci device, not the node with the
 918          * dma-window property
 919          */
 920         dn = pci_device_to_OF_node(dev);
 921         pdn = PCI_DN(dn);
 922         buid = pdn->phb->buid;
 923         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 924
 925         do {
 926                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 927                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 928                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 929                                 page_shift, window_shift);
 930         } while (rtas_busy_delay(ret));
 931         dev_info(&dev->dev,
 932                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 933                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 934                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 935                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 936
 937         return ret;
 938 }
 939
 940 struct failed_ddw_pdn {
 941         struct device_node *pdn;
 942         struct list_head list;
 943 };
 944
 945 static LIST_HEAD(failed_ddw_pdn_list);
 946
 947 /*
 948  * If the PE supports dynamic dma windows, and there is space for a table
 949  * that can map all pages in a linear offset, then setup such a table,
 950  * and record the dma-offset in the struct device.
 951  *
 952  * dev: the pci device we are checking
 953  * pdn: the parent pe node with the ibm,dma_window property
 954  * Future: also check if we can remap the base window for our base page size
 955  *
 956  * returns the dma offset for use by dma_set_mask
 957  */
 958 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
 959 {
 960         int len, ret;
 961         struct ddw_query_response query;
 962         struct ddw_create_response create;
 963         int page_shift;
 964         u64 dma_addr, max_addr;
 965         struct device_node *dn;
 966         u32 ddw_avail[3];
 967         struct direct_window *window;
 968         struct property *win64;
 969         struct dynamic_dma_window_prop *ddwprop;
 970         struct failed_ddw_pdn *fpdn;
 971
 972         mutex_lock(&direct_window_init_mutex);
 973
 974         dma_addr = find_existing_ddw(pdn);
 975         if (dma_addr != 0)
 976                 goto out_unlock;
 977
 978         /*
 979          * If we already went through this for a previous function of
 980          * the same device and failed, we don't want to muck with the
 981          * DMA window again, as it will race with in-flight operations
 982          * and can lead to EEHs. The above mutex protects access to the
 983          * list.
 984          */
 985         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
 986                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
 987                         goto out_unlock;
 988         }
 989
 990         /*
 991          * the ibm,ddw-applicable property holds the tokens for:
 992          * ibm,query-pe-dma-window
 993          * ibm,create-pe-dma-window
 994          * ibm,remove-pe-dma-window
 995          * for the given node in that order.
 996          * the property is actually in the parent, not the PE
 997          */
 998         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
 999                                          &ddw_avail[0], 3);
1000         if (ret)
1001                 goto out_failed;
1002
1003        /*
1004          * Query if there is a second window of size to map the
1005          * whole partition.  Query returns number of windows, largest
1006          * block assigned to PE (partition endpoint), and two bitmasks
1007          * of page sizes: supported and supported for migrate-dma.
1008          */
1009         dn = pci_device_to_OF_node(dev);
1010         ret = query_ddw(dev, ddw_avail, &query);
1011         if (ret != 0)
1012                 goto out_failed;
1013
1014         if (query.windows_available == 0) {
1015                 /*
1016                  * no additional windows are available for this device.
1017                  * We might be able to reallocate the existing window,
1018                  * trading in for a larger page size.
1019                  */
1020                 dev_dbg(&dev->dev, "no free dynamic windows");
1021                 goto out_failed;
1022         }
1023         if (query.page_size & 4) {
1024                 page_shift = 24; /* 16MB */
1025         } else if (query.page_size & 2) {
1026                 page_shift = 16; /* 64kB */
1027         } else if (query.page_size & 1) {
1028                 page_shift = 12; /* 4kB */
1029         } else {
1030                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1031                           query.page_size);
1032                 goto out_failed;
1033         }
1034         /* verify the window * number of ptes will map the partition */
1035         /* check largest block * page size > max memory hotplug addr */
1036         max_addr = memory_hotplug_max();
1037         if (query.largest_available_block < (max_addr >> page_shift)) {
1038                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1039                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1040                           1ULL << page_shift);
1041                 goto out_failed;
1042         }
1043         len = order_base_2(max_addr);
1044         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1045         if (!win64) {
1046                 dev_info(&dev->dev,
1047                         "couldn't allocate property for 64bit dma window\n");
1048                 goto out_failed;
1049         }
1050         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1051         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1052         win64->length = sizeof(*ddwprop);
1053         if (!win64->name || !win64->value) {
1054                 dev_info(&dev->dev,
1055                         "couldn't allocate property name and value\n");
1056                 goto out_free_prop;
1057         }
1058
1059         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1060         if (ret != 0)
1061                 goto out_free_prop;
1062
1063         ddwprop->liobn = cpu_to_be32(create.liobn);
1064         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1065                         create.addr_lo);
1066         ddwprop->tce_shift = cpu_to_be32(page_shift);
1067         ddwprop->window_shift = cpu_to_be32(len);
1068
1069         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1070                   create.liobn, dn->full_name);
1071
1072         window = kzalloc(sizeof(*window), GFP_KERNEL);
1073         if (!window)
1074                 goto out_clear_window;
1075
1076         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1077                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1078         if (ret) {
1079                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1080                          dn->full_name, ret);
1081                 goto out_free_window;
1082         }
1083
1084         ret = of_add_property(pdn, win64);
1085         if (ret) {
1086                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1087                          pdn->full_name, ret);
1088                 goto out_free_window;
1089         }
1090
1091         window->device = pdn;
1092         window->prop = ddwprop;
1093         spin_lock(&direct_window_list_lock);
1094         list_add(&window->list, &direct_window_list);
1095         spin_unlock(&direct_window_list_lock);
1096
1097         dma_addr = be64_to_cpu(ddwprop->dma_base);
1098         goto out_unlock;
1099
1100 out_free_window:
1101         kfree(window);
1102
1103 out_clear_window:
1104         remove_ddw(pdn, true);
1105
1106 out_free_prop:
1107         kfree(win64->name);
1108         kfree(win64->value);
1109         kfree(win64);
1110
1111 out_failed:
1112
1113         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1114         if (!fpdn)
1115                 goto out_unlock;
1116         fpdn->pdn = pdn;
1117         list_add(&fpdn->list, &failed_ddw_pdn_list);
1118
1119 out_unlock:
1120         mutex_unlock(&direct_window_init_mutex);
1121         return dma_addr;
1122 }
1123
1124 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1125 {
1126         struct device_node *pdn, *dn;
1127         struct iommu_table *tbl;
1128         const __be32 *dma_window = NULL;
1129         struct pci_dn *pci;
1130
1131         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1132
1133         /* dev setup for LPAR is a little tricky, since the device tree might
1134          * contain the dma-window properties per-device and not necessarily
1135          * for the bus. So we need to search upwards in the tree until we
1136          * either hit a dma-window property, OR find a parent with a table
1137          * already allocated.
1138          */
1139         dn = pci_device_to_OF_node(dev);
1140         pr_debug("  node is %s\n", dn->full_name);
1141
1142         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1143              pdn = pdn->parent) {
1144                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1145                 if (dma_window)
1146                         break;
1147         }
1148
1149         if (!pdn || !PCI_DN(pdn)) {
1150                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1151                        "no DMA window found for pci dev=%s dn=%s\n",
1152                                  pci_name(dev), of_node_full_name(dn));
1153                 return;
1154         }
1155         pr_debug("  parent is %s\n", pdn->full_name);
1156
1157         pci = PCI_DN(pdn);
1158         if (!pci->table_group) {
1159                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1160                 tbl = pci->table_group->tables[0];
1161                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1162                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1163                 iommu_init_table(tbl, pci->phb->node);
1164                 iommu_register_group(pci->table_group,
1165                                 pci_domain_nr(pci->phb->bus), 0);
1166                 pr_debug("  created table: %p\n", pci->table_group);
1167         } else {
1168                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1169         }
1170
1171         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1172         iommu_add_device(&dev->dev);
1173 }
1174
1175 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1176 {
1177         bool ddw_enabled = false;
1178         struct device_node *pdn, *dn;
1179         struct pci_dev *pdev;
1180         const __be32 *dma_window = NULL;
1181         u64 dma_offset;
1182
1183         if (!dev->dma_mask)
1184                 return -EIO;
1185
1186         if (!dev_is_pci(dev))
1187                 goto check_mask;
1188
1189         pdev = to_pci_dev(dev);
1190
1191         /* only attempt to use a new window if 64-bit DMA is requested */
1192         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1193                 dn = pci_device_to_OF_node(pdev);
1194                 dev_dbg(dev, "node is %s\n", dn->full_name);
1195
1196                 /*
1197                  * the device tree might contain the dma-window properties
1198                  * per-device and not necessarily for the bus. So we need to
1199                  * search upwards in the tree until we either hit a dma-window
1200                  * property, OR find a parent with a table already allocated.
1201                  */
1202                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1203                                 pdn = pdn->parent) {
1204                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1205                         if (dma_window)
1206                                 break;
1207                 }
1208                 if (pdn && PCI_DN(pdn)) {
1209                         dma_offset = enable_ddw(pdev, pdn);
1210                         if (dma_offset != 0) {
1211                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1212                                 set_dma_offset(dev, dma_offset);
1213                                 set_dma_ops(dev, &dma_direct_ops);
1214                                 ddw_enabled = true;
1215                         }
1216                 }
1217         }
1218
1219         /* fall back on iommu ops */
1220         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1221                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1222                 set_dma_ops(dev, &dma_iommu_ops);
1223         }
1224
1225 check_mask:
1226         if (!dma_supported(dev, dma_mask))
1227                 return -EIO;
1228
1229         *dev->dma_mask = dma_mask;
1230         return 0;
1231 }
1232
1233 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1234 {
1235         if (!dev->dma_mask)
1236                 return 0;
1237
1238         if (!disable_ddw && dev_is_pci(dev)) {
1239                 struct pci_dev *pdev = to_pci_dev(dev);
1240                 struct device_node *dn;
1241
1242                 dn = pci_device_to_OF_node(pdev);
1243
1244                 /* search upwards for ibm,dma-window */
1245                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1246                                 dn = dn->parent)
1247                         if (of_get_property(dn, "ibm,dma-window", NULL))
1248                                 break;
1249                 /* if there is a ibm,ddw-applicable property require 64 bits */
1250                 if (dn && PCI_DN(dn) &&
1251                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1252                         return DMA_BIT_MASK(64);
1253         }
1254
1255         return dma_iommu_ops.get_required_mask(dev);
1256 }
1257
1258 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1259                 void *data)
1260 {
1261         struct direct_window *window;
1262         struct memory_notify *arg = data;
1263         int ret = 0;
1264
1265         switch (action) {
1266         case MEM_GOING_ONLINE:
1267                 spin_lock(&direct_window_list_lock);
1268                 list_for_each_entry(window, &direct_window_list, list) {
1269                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1270                                         arg->nr_pages, window->prop);
1271                         /* XXX log error */
1272                 }
1273                 spin_unlock(&direct_window_list_lock);
1274                 break;
1275         case MEM_CANCEL_ONLINE:
1276         case MEM_OFFLINE:
1277                 spin_lock(&direct_window_list_lock);
1278                 list_for_each_entry(window, &direct_window_list, list) {
1279                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1280                                         arg->nr_pages, window->prop);
1281                         /* XXX log error */
1282                 }
1283                 spin_unlock(&direct_window_list_lock);
1284                 break;
1285         default:
1286                 break;
1287         }
1288         if (ret && action != MEM_CANCEL_ONLINE)
1289                 return NOTIFY_BAD;
1290
1291         return NOTIFY_OK;
1292 }
1293
1294 static struct notifier_block iommu_mem_nb = {
1295         .notifier_call = iommu_mem_notifier,
1296 };
1297
1298 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1299 {
1300         int err = NOTIFY_OK;
1301         struct of_reconfig_data *rd = data;
1302         struct device_node *np = rd->dn;
1303         struct pci_dn *pci = PCI_DN(np);
1304         struct direct_window *window;
1305
1306         switch (action) {
1307         case OF_RECONFIG_DETACH_NODE:
1308                 /*
1309                  * Removing the property will invoke the reconfig
1310                  * notifier again, which causes dead-lock on the
1311                  * read-write semaphore of the notifier chain. So
1312                  * we have to remove the property when releasing
1313                  * the device node.
1314                  */
1315                 remove_ddw(np, false);
1316                 if (pci && pci->table_group)
1317                         iommu_pseries_free_group(pci->table_group,
1318                                         np->full_name);
1319
1320                 spin_lock(&direct_window_list_lock);
1321                 list_for_each_entry(window, &direct_window_list, list) {
1322                         if (window->device == np) {
1323                                 list_del(&window->list);
1324                                 kfree(window);
1325                                 break;
1326                         }
1327                 }
1328                 spin_unlock(&direct_window_list_lock);
1329                 break;
1330         default:
1331                 err = NOTIFY_DONE;
1332                 break;
1333         }
1334         return err;
1335 }
1336
1337 static struct notifier_block iommu_reconfig_nb = {
1338         .notifier_call = iommu_reconfig_notifier,
1339 };
1340
1341 /* These are called very early. */
1342 void iommu_init_early_pSeries(void)
1343 {
1344         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1345                 return;
1346
1347         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1348                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1349                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1350                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1351                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1352         } else {
1353                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1354                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1355         }
1356
1357
1358         of_reconfig_notifier_register(&iommu_reconfig_nb);
1359         register_memory_notifier(&iommu_mem_nb);
1360
1361         set_pci_dma_ops(&dma_iommu_ops);
1362 }
1363
1364 static int __init disable_multitce(char *str)
1365 {
1366         if (strcmp(str, "off") == 0 &&
1367             firmware_has_feature(FW_FEATURE_LPAR) &&
1368             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1369                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1370                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1371         }
1372         return 1;
1373 }
1374
1375 __setup("multitce=", disable_multitce);
1376
1377 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);