1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
7 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
8 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/slab.h>
17 #include <linux/memblock.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/pci.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/crash_dump.h>
23 #include <linux/memory.h>
25 #include <linux/iommu.h>
26 #include <linux/rculist.h>
30 #include <asm/iommu.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <asm/firmware.h>
35 #include <asm/ppc-pci.h>
37 #include <asm/mmzone.h>
38 #include <asm/plpar_wrappers.h>
42 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
44 struct iommu_table_group *table_group;
45 struct iommu_table *tbl;
47 table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
52 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
56 INIT_LIST_HEAD_RCU(&tbl->it_group_list);
57 kref_init(&tbl->it_kref);
59 table_group->tables[0] = tbl;
68 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
69 const char *node_name)
71 struct iommu_table *tbl;
76 tbl = table_group->tables[0];
77 #ifdef CONFIG_IOMMU_API
78 if (table_group->group) {
79 iommu_group_put(table_group->group);
80 BUG_ON(table_group->group);
83 iommu_tce_table_put(tbl);
88 static int tce_build_pSeries(struct iommu_table *tbl, long index,
89 long npages, unsigned long uaddr,
90 enum dma_data_direction direction,
97 proto_tce = TCE_PCI_READ; // Read allowed
99 if (direction != DMA_TO_DEVICE)
100 proto_tce |= TCE_PCI_WRITE;
102 tcep = ((__be64 *)tbl->it_base) + index;
105 /* can't move this out since we might cross MEMBLOCK boundary */
106 rpn = __pa(uaddr) >> TCE_SHIFT;
107 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
109 uaddr += TCE_PAGE_SIZE;
116 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
120 tcep = ((__be64 *)tbl->it_base) + index;
126 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
130 tcep = ((__be64 *)tbl->it_base) + index;
132 return be64_to_cpu(*tcep);
135 static void tce_free_pSeriesLP(unsigned long liobn, long, long);
136 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
138 static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift,
139 long npages, unsigned long uaddr,
140 enum dma_data_direction direction,
147 long tcenum_start = tcenum, npages_start = npages;
149 rpn = __pa(uaddr) >> tceshift;
150 proto_tce = TCE_PCI_READ;
151 if (direction != DMA_TO_DEVICE)
152 proto_tce |= TCE_PCI_WRITE;
155 tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift;
156 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce);
158 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
160 tce_free_pSeriesLP(liobn, tcenum_start,
161 (npages_start - (npages + 1)));
165 if (rc && printk_ratelimit()) {
166 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
167 printk("\tindex = 0x%llx\n", (u64)liobn);
168 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
169 printk("\ttce val = 0x%llx\n", tce );
179 static DEFINE_PER_CPU(__be64 *, tce_page);
181 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
182 long npages, unsigned long uaddr,
183 enum dma_data_direction direction,
191 long tcenum_start = tcenum, npages_start = npages;
195 if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
196 return tce_build_pSeriesLP(tbl->it_index, tcenum,
197 tbl->it_page_shift, npages, uaddr,
201 local_irq_save(flags); /* to protect tcep and the page behind it */
203 tcep = __this_cpu_read(tce_page);
205 /* This is safe to do since interrupts are off when we're called
206 * from iommu_alloc{,_sg}()
209 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
210 /* If allocation fails, fall back to the loop implementation */
212 local_irq_restore(flags);
213 return tce_build_pSeriesLP(tbl->it_index, tcenum,
215 npages, uaddr, direction, attrs);
217 __this_cpu_write(tce_page, tcep);
220 rpn = __pa(uaddr) >> TCE_SHIFT;
221 proto_tce = TCE_PCI_READ;
222 if (direction != DMA_TO_DEVICE)
223 proto_tce |= TCE_PCI_WRITE;
225 /* We can map max one pageful of TCEs at a time */
228 * Set up the page with TCE data, looping through and setting
231 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
233 for (l = 0; l < limit; l++) {
234 tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
238 rc = plpar_tce_put_indirect((u64)tbl->it_index,
245 } while (npages > 0 && !rc);
247 local_irq_restore(flags);
249 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
251 tce_freemulti_pSeriesLP(tbl, tcenum_start,
252 (npages_start - (npages + limit)));
256 if (rc && printk_ratelimit()) {
257 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
258 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
259 printk("\tnpages = 0x%llx\n", (u64)npages);
260 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
266 static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages)
271 rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0);
273 if (rc && printk_ratelimit()) {
274 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
275 printk("\tindex = 0x%llx\n", (u64)liobn);
276 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
285 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
289 if (!firmware_has_feature(FW_FEATURE_MULTITCE))
290 return tce_free_pSeriesLP(tbl->it_index, tcenum, npages);
292 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
294 if (rc && printk_ratelimit()) {
295 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
296 printk("\trc = %lld\n", rc);
297 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
298 printk("\tnpages = 0x%llx\n", (u64)npages);
303 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
306 unsigned long tce_ret;
308 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
310 if (rc && printk_ratelimit()) {
311 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
312 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
313 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
320 /* this is compatible with cells for the device tree property */
321 struct dynamic_dma_window_prop {
322 __be32 liobn; /* tce table number */
323 __be64 dma_base; /* address hi,lo */
324 __be32 tce_shift; /* ilog2(tce_page_size) */
325 __be32 window_shift; /* ilog2(tce_window_size) */
328 struct direct_window {
329 struct device_node *device;
330 const struct dynamic_dma_window_prop *prop;
331 struct list_head list;
334 /* Dynamic DMA Window support */
335 struct ddw_query_response {
336 u32 windows_available;
337 u32 largest_available_block;
339 u32 migration_capable;
342 struct ddw_create_response {
348 static LIST_HEAD(direct_window_list);
349 /* prevents races between memory on/offline and window creation */
350 static DEFINE_SPINLOCK(direct_window_list_lock);
351 /* protects initializing window twice for same device */
352 static DEFINE_MUTEX(direct_window_init_mutex);
353 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
355 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
356 unsigned long num_pfn, const void *arg)
358 const struct dynamic_dma_window_prop *maprange = arg;
360 u64 tce_size, num_tce, dma_offset, next;
364 tce_shift = be32_to_cpu(maprange->tce_shift);
365 tce_size = 1ULL << tce_shift;
366 next = start_pfn << PAGE_SHIFT;
367 num_tce = num_pfn << PAGE_SHIFT;
369 /* round back to the beginning of the tce page size */
370 num_tce += next & (tce_size - 1);
371 next &= ~(tce_size - 1);
373 /* covert to number of tces */
374 num_tce |= tce_size - 1;
375 num_tce >>= tce_shift;
379 * Set up the page with TCE data, looping through and setting
382 limit = min_t(long, num_tce, 512);
383 dma_offset = next + be64_to_cpu(maprange->dma_base);
385 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
388 next += limit * tce_size;
390 } while (num_tce > 0 && !rc);
395 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
396 unsigned long num_pfn, const void *arg)
398 const struct dynamic_dma_window_prop *maprange = arg;
399 u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
405 if (!firmware_has_feature(FW_FEATURE_MULTITCE)) {
406 unsigned long tceshift = be32_to_cpu(maprange->tce_shift);
407 unsigned long dmastart = (start_pfn << PAGE_SHIFT) +
408 be64_to_cpu(maprange->dma_base);
409 unsigned long tcenum = dmastart >> tceshift;
410 unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift;
411 void *uaddr = __va(start_pfn << PAGE_SHIFT);
413 return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn),
414 tcenum, tceshift, npages, (unsigned long) uaddr,
415 DMA_BIDIRECTIONAL, 0);
418 local_irq_disable(); /* to protect tcep and the page behind it */
419 tcep = __this_cpu_read(tce_page);
422 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
427 __this_cpu_write(tce_page, tcep);
430 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
432 liobn = (u64)be32_to_cpu(maprange->liobn);
433 tce_shift = be32_to_cpu(maprange->tce_shift);
434 tce_size = 1ULL << tce_shift;
435 next = start_pfn << PAGE_SHIFT;
436 num_tce = num_pfn << PAGE_SHIFT;
438 /* round back to the beginning of the tce page size */
439 num_tce += next & (tce_size - 1);
440 next &= ~(tce_size - 1);
442 /* covert to number of tces */
443 num_tce |= tce_size - 1;
444 num_tce >>= tce_shift;
446 /* We can map max one pageful of TCEs at a time */
449 * Set up the page with TCE data, looping through and setting
452 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
453 dma_offset = next + be64_to_cpu(maprange->dma_base);
455 for (l = 0; l < limit; l++) {
456 tcep[l] = cpu_to_be64(proto_tce | next);
460 rc = plpar_tce_put_indirect(liobn,
466 } while (num_tce > 0 && !rc);
468 /* error cleanup: caller will clear whole range */
474 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
475 unsigned long num_pfn, void *arg)
477 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
480 static void iommu_table_setparms(struct pci_controller *phb,
481 struct device_node *dn,
482 struct iommu_table *tbl)
484 struct device_node *node;
485 const unsigned long *basep;
490 basep = of_get_property(node, "linux,tce-base", NULL);
491 sizep = of_get_property(node, "linux,tce-size", NULL);
492 if (basep == NULL || sizep == NULL) {
493 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %pOF has "
494 "missing tce entries !\n", dn);
498 tbl->it_base = (unsigned long)__va(*basep);
500 if (!is_kdump_kernel())
501 memset((void *)tbl->it_base, 0, *sizep);
503 tbl->it_busno = phb->bus->number;
504 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
506 /* Units of tce entries */
507 tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
509 /* Test if we are going over 2GB of DMA space */
510 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
511 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
512 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
515 phb->dma_window_base_cur += phb->dma_window_size;
517 /* Set the tce table size - measured in entries */
518 tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
521 tbl->it_blocksize = 16;
522 tbl->it_type = TCE_PCI;
526 * iommu_table_setparms_lpar
528 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
530 static void iommu_table_setparms_lpar(struct pci_controller *phb,
531 struct device_node *dn,
532 struct iommu_table *tbl,
533 struct iommu_table_group *table_group,
534 const __be32 *dma_window)
536 unsigned long offset, size;
538 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
540 tbl->it_busno = phb->bus->number;
541 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
543 tbl->it_blocksize = 16;
544 tbl->it_type = TCE_PCI;
545 tbl->it_offset = offset >> tbl->it_page_shift;
546 tbl->it_size = size >> tbl->it_page_shift;
548 table_group->tce32_start = offset;
549 table_group->tce32_size = size;
552 struct iommu_table_ops iommu_table_pseries_ops = {
553 .set = tce_build_pSeries,
554 .clear = tce_free_pSeries,
555 .get = tce_get_pseries
558 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
560 struct device_node *dn;
561 struct iommu_table *tbl;
562 struct device_node *isa_dn, *isa_dn_orig;
563 struct device_node *tmp;
567 dn = pci_bus_to_OF_node(bus);
569 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %pOF\n", dn);
572 /* This is not a root bus, any setup will be done for the
573 * device-side of the bridge in iommu_dev_setup_pSeries().
579 /* Check if the ISA bus on the system is under
582 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
584 while (isa_dn && isa_dn != dn)
585 isa_dn = isa_dn->parent;
587 of_node_put(isa_dn_orig);
589 /* Count number of direct PCI children of the PHB. */
590 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
593 pr_debug("Children: %d\n", children);
595 /* Calculate amount of DMA window per slot. Each window must be
596 * a power of two (due to pci_alloc_consistent requirements).
598 * Keep 256MB aside for PHBs with ISA.
602 /* No ISA/IDE - just set window size and return */
603 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
605 while (pci->phb->dma_window_size * children > 0x80000000ul)
606 pci->phb->dma_window_size >>= 1;
607 pr_debug("No ISA/IDE, window size is 0x%llx\n",
608 pci->phb->dma_window_size);
609 pci->phb->dma_window_base_cur = 0;
614 /* If we have ISA, then we probably have an IDE
615 * controller too. Allocate a 128MB table but
616 * skip the first 128MB to avoid stepping on ISA
619 pci->phb->dma_window_size = 0x8000000ul;
620 pci->phb->dma_window_base_cur = 0x8000000ul;
622 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
623 tbl = pci->table_group->tables[0];
625 iommu_table_setparms(pci->phb, dn, tbl);
626 tbl->it_ops = &iommu_table_pseries_ops;
627 iommu_init_table(tbl, pci->phb->node, 0, 0);
629 /* Divide the rest (1.75GB) among the children */
630 pci->phb->dma_window_size = 0x80000000ul;
631 while (pci->phb->dma_window_size * children > 0x70000000ul)
632 pci->phb->dma_window_size >>= 1;
634 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
637 #ifdef CONFIG_IOMMU_API
638 static int tce_exchange_pseries(struct iommu_table *tbl, long index, unsigned
639 long *tce, enum dma_data_direction *direction,
643 unsigned long ioba = (unsigned long) index << tbl->it_page_shift;
644 unsigned long flags, oldtce = 0;
645 u64 proto_tce = iommu_direction_to_tce_perm(*direction);
646 unsigned long newtce = *tce | proto_tce;
648 spin_lock_irqsave(&tbl->large_pool.lock, flags);
650 rc = plpar_tce_get((u64)tbl->it_index, ioba, &oldtce);
652 rc = plpar_tce_put((u64)tbl->it_index, ioba, newtce);
655 *direction = iommu_tce_direction(oldtce);
656 *tce = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
659 spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
665 struct iommu_table_ops iommu_table_lpar_multi_ops = {
666 .set = tce_buildmulti_pSeriesLP,
667 #ifdef CONFIG_IOMMU_API
668 .xchg_no_kill = tce_exchange_pseries,
670 .clear = tce_freemulti_pSeriesLP,
671 .get = tce_get_pSeriesLP
674 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
676 struct iommu_table *tbl;
677 struct device_node *dn, *pdn;
679 const __be32 *dma_window = NULL;
681 dn = pci_bus_to_OF_node(bus);
683 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %pOF\n",
686 /* Find nearest ibm,dma-window, walking up the device tree */
687 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
688 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
689 if (dma_window != NULL)
693 if (dma_window == NULL) {
694 pr_debug(" no ibm,dma-window property !\n");
700 pr_debug(" parent is %pOF, iommu_table: 0x%p\n",
701 pdn, ppci->table_group);
703 if (!ppci->table_group) {
704 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
705 tbl = ppci->table_group->tables[0];
706 iommu_table_setparms_lpar(ppci->phb, pdn, tbl,
707 ppci->table_group, dma_window);
708 tbl->it_ops = &iommu_table_lpar_multi_ops;
709 iommu_init_table(tbl, ppci->phb->node, 0, 0);
710 iommu_register_group(ppci->table_group,
711 pci_domain_nr(bus), 0);
712 pr_debug(" created table: %p\n", ppci->table_group);
717 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
719 struct device_node *dn;
720 struct iommu_table *tbl;
722 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
724 dn = dev->dev.of_node;
726 /* If we're the direct child of a root bus, then we need to allocate
727 * an iommu table ourselves. The bus setup code should have setup
728 * the window sizes already.
730 if (!dev->bus->self) {
731 struct pci_controller *phb = PCI_DN(dn)->phb;
733 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
734 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
735 tbl = PCI_DN(dn)->table_group->tables[0];
736 iommu_table_setparms(phb, dn, tbl);
737 tbl->it_ops = &iommu_table_pseries_ops;
738 iommu_init_table(tbl, phb->node, 0, 0);
739 set_iommu_table_base(&dev->dev, tbl);
743 /* If this device is further down the bus tree, search upwards until
744 * an already allocated iommu table is found and use that.
747 while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
750 if (dn && PCI_DN(dn))
751 set_iommu_table_base(&dev->dev,
752 PCI_DN(dn)->table_group->tables[0]);
754 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
758 static int __read_mostly disable_ddw;
760 static int __init disable_ddw_setup(char *str)
763 printk(KERN_INFO "ppc iommu: disabling ddw.\n");
768 early_param("disable_ddw", disable_ddw_setup);
770 static void remove_ddw(struct device_node *np, bool remove_prop)
772 struct dynamic_dma_window_prop *dwp;
773 struct property *win64;
778 ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
781 win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
785 if (ret || win64->length < sizeof(*dwp))
789 liobn = (u64)be32_to_cpu(dwp->liobn);
791 /* clear the whole window, note the arg is in kernel pages */
792 ret = tce_clearrange_multi_pSeriesLP(0,
793 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
795 pr_warn("%pOF failed to clear tces in window.\n",
798 pr_debug("%pOF successfully cleared tces in window.\n",
801 ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
803 pr_warn("%pOF: failed to remove direct window: rtas returned "
804 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
805 np, ret, ddw_avail[2], liobn);
807 pr_debug("%pOF: successfully removed direct window: rtas returned "
808 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
809 np, ret, ddw_avail[2], liobn);
813 ret = of_remove_property(np, win64);
815 pr_warn("%pOF: failed to remove direct window property: %d\n",
819 static u64 find_existing_ddw(struct device_node *pdn)
821 struct direct_window *window;
822 const struct dynamic_dma_window_prop *direct64;
825 spin_lock(&direct_window_list_lock);
826 /* check if we already created a window and dupe that config if so */
827 list_for_each_entry(window, &direct_window_list, list) {
828 if (window->device == pdn) {
829 direct64 = window->prop;
830 dma_addr = be64_to_cpu(direct64->dma_base);
834 spin_unlock(&direct_window_list_lock);
839 static int find_existing_ddw_windows(void)
842 struct device_node *pdn;
843 struct direct_window *window;
844 const struct dynamic_dma_window_prop *direct64;
846 if (!firmware_has_feature(FW_FEATURE_LPAR))
849 for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
850 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
854 window = kzalloc(sizeof(*window), GFP_KERNEL);
855 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
857 remove_ddw(pdn, true);
861 window->device = pdn;
862 window->prop = direct64;
863 spin_lock(&direct_window_list_lock);
864 list_add(&window->list, &direct_window_list);
865 spin_unlock(&direct_window_list_lock);
870 machine_arch_initcall(pseries, find_existing_ddw_windows);
872 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
873 struct ddw_query_response *query)
875 struct device_node *dn;
882 * Get the config address and phb buid of the PE window.
883 * Rely on eeh to retrieve this for us.
884 * Retrieve them from the pci device, not the node with the
885 * dma-window property
887 dn = pci_device_to_OF_node(dev);
889 buid = pdn->phb->buid;
890 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
892 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
893 cfg_addr, BUID_HI(buid), BUID_LO(buid));
894 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
895 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
900 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
901 struct ddw_create_response *create, int page_shift,
904 struct device_node *dn;
911 * Get the config address and phb buid of the PE window.
912 * Rely on eeh to retrieve this for us.
913 * Retrieve them from the pci device, not the node with the
914 * dma-window property
916 dn = pci_device_to_OF_node(dev);
918 buid = pdn->phb->buid;
919 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
922 /* extra outputs are LIOBN and dma-addr (hi, lo) */
923 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
924 cfg_addr, BUID_HI(buid), BUID_LO(buid),
925 page_shift, window_shift);
926 } while (rtas_busy_delay(ret));
928 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
929 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
930 cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
931 window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
936 struct failed_ddw_pdn {
937 struct device_node *pdn;
938 struct list_head list;
941 static LIST_HEAD(failed_ddw_pdn_list);
943 static phys_addr_t ddw_memory_hotplug_max(void)
945 phys_addr_t max_addr = memory_hotplug_max();
946 struct device_node *memory;
948 for_each_node_by_type(memory, "memory") {
949 unsigned long start, size;
950 int n_mem_addr_cells, n_mem_size_cells, len;
951 const __be32 *memcell_buf;
953 memcell_buf = of_get_property(memory, "reg", &len);
954 if (!memcell_buf || len <= 0)
957 n_mem_addr_cells = of_n_addr_cells(memory);
958 n_mem_size_cells = of_n_size_cells(memory);
960 start = of_read_number(memcell_buf, n_mem_addr_cells);
961 memcell_buf += n_mem_addr_cells;
962 size = of_read_number(memcell_buf, n_mem_size_cells);
963 memcell_buf += n_mem_size_cells;
965 max_addr = max_t(phys_addr_t, max_addr, start + size);
972 * If the PE supports dynamic dma windows, and there is space for a table
973 * that can map all pages in a linear offset, then setup such a table,
974 * and record the dma-offset in the struct device.
976 * dev: the pci device we are checking
977 * pdn: the parent pe node with the ibm,dma_window property
978 * Future: also check if we can remap the base window for our base page size
980 * returns the dma offset for use by the direct mapped DMA code.
982 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
985 struct ddw_query_response query;
986 struct ddw_create_response create;
988 u64 dma_addr, max_addr;
989 struct device_node *dn;
991 struct direct_window *window;
992 struct property *win64;
993 struct dynamic_dma_window_prop *ddwprop;
994 struct failed_ddw_pdn *fpdn;
996 mutex_lock(&direct_window_init_mutex);
998 dma_addr = find_existing_ddw(pdn);
1003 * If we already went through this for a previous function of
1004 * the same device and failed, we don't want to muck with the
1005 * DMA window again, as it will race with in-flight operations
1006 * and can lead to EEHs. The above mutex protects access to the
1009 list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
1010 if (fpdn->pdn == pdn)
1015 * the ibm,ddw-applicable property holds the tokens for:
1016 * ibm,query-pe-dma-window
1017 * ibm,create-pe-dma-window
1018 * ibm,remove-pe-dma-window
1019 * for the given node in that order.
1020 * the property is actually in the parent, not the PE
1022 ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
1028 * Query if there is a second window of size to map the
1029 * whole partition. Query returns number of windows, largest
1030 * block assigned to PE (partition endpoint), and two bitmasks
1031 * of page sizes: supported and supported for migrate-dma.
1033 dn = pci_device_to_OF_node(dev);
1034 ret = query_ddw(dev, ddw_avail, &query);
1038 if (query.windows_available == 0) {
1040 * no additional windows are available for this device.
1041 * We might be able to reallocate the existing window,
1042 * trading in for a larger page size.
1044 dev_dbg(&dev->dev, "no free dynamic windows");
1047 if (query.page_size & 4) {
1048 page_shift = 24; /* 16MB */
1049 } else if (query.page_size & 2) {
1050 page_shift = 16; /* 64kB */
1051 } else if (query.page_size & 1) {
1052 page_shift = 12; /* 4kB */
1054 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1058 /* verify the window * number of ptes will map the partition */
1059 /* check largest block * page size > max memory hotplug addr */
1060 max_addr = ddw_memory_hotplug_max();
1061 if (query.largest_available_block < (max_addr >> page_shift)) {
1062 dev_dbg(&dev->dev, "can't map partition max 0x%llx with %u "
1063 "%llu-sized pages\n", max_addr, query.largest_available_block,
1064 1ULL << page_shift);
1067 len = order_base_2(max_addr);
1068 win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1071 "couldn't allocate property for 64bit dma window\n");
1074 win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1075 win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1076 win64->length = sizeof(*ddwprop);
1077 if (!win64->name || !win64->value) {
1079 "couldn't allocate property name and value\n");
1083 ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1087 ddwprop->liobn = cpu_to_be32(create.liobn);
1088 ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1090 ddwprop->tce_shift = cpu_to_be32(page_shift);
1091 ddwprop->window_shift = cpu_to_be32(len);
1093 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n",
1096 window = kzalloc(sizeof(*window), GFP_KERNEL);
1098 goto out_clear_window;
1100 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1101 win64->value, tce_setrange_multi_pSeriesLP_walk);
1103 dev_info(&dev->dev, "failed to map direct window for %pOF: %d\n",
1105 goto out_free_window;
1108 ret = of_add_property(pdn, win64);
1110 dev_err(&dev->dev, "unable to add dma window property for %pOF: %d",
1112 goto out_free_window;
1115 window->device = pdn;
1116 window->prop = ddwprop;
1117 spin_lock(&direct_window_list_lock);
1118 list_add(&window->list, &direct_window_list);
1119 spin_unlock(&direct_window_list_lock);
1121 dma_addr = be64_to_cpu(ddwprop->dma_base);
1128 remove_ddw(pdn, true);
1132 kfree(win64->value);
1137 fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1141 list_add(&fpdn->list, &failed_ddw_pdn_list);
1144 mutex_unlock(&direct_window_init_mutex);
1148 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1150 struct device_node *pdn, *dn;
1151 struct iommu_table *tbl;
1152 const __be32 *dma_window = NULL;
1155 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1157 /* dev setup for LPAR is a little tricky, since the device tree might
1158 * contain the dma-window properties per-device and not necessarily
1159 * for the bus. So we need to search upwards in the tree until we
1160 * either hit a dma-window property, OR find a parent with a table
1161 * already allocated.
1163 dn = pci_device_to_OF_node(dev);
1164 pr_debug(" node is %pOF\n", dn);
1166 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1167 pdn = pdn->parent) {
1168 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1173 if (!pdn || !PCI_DN(pdn)) {
1174 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1175 "no DMA window found for pci dev=%s dn=%pOF\n",
1179 pr_debug(" parent is %pOF\n", pdn);
1182 if (!pci->table_group) {
1183 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1184 tbl = pci->table_group->tables[0];
1185 iommu_table_setparms_lpar(pci->phb, pdn, tbl,
1186 pci->table_group, dma_window);
1187 tbl->it_ops = &iommu_table_lpar_multi_ops;
1188 iommu_init_table(tbl, pci->phb->node, 0, 0);
1189 iommu_register_group(pci->table_group,
1190 pci_domain_nr(pci->phb->bus), 0);
1191 pr_debug(" created table: %p\n", pci->table_group);
1193 pr_debug(" found DMA window, table: %p\n", pci->table_group);
1196 set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1197 iommu_add_device(pci->table_group, &dev->dev);
1200 static bool iommu_bypass_supported_pSeriesLP(struct pci_dev *pdev, u64 dma_mask)
1202 struct device_node *dn = pci_device_to_OF_node(pdev), *pdn;
1203 const __be32 *dma_window = NULL;
1205 /* only attempt to use a new window if 64-bit DMA is requested */
1206 if (dma_mask < DMA_BIT_MASK(64))
1209 dev_dbg(&pdev->dev, "node is %pOF\n", dn);
1212 * the device tree might contain the dma-window properties
1213 * per-device and not necessarily for the bus. So we need to
1214 * search upwards in the tree until we either hit a dma-window
1215 * property, OR find a parent with a table already allocated.
1217 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1218 pdn = pdn->parent) {
1219 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1224 if (pdn && PCI_DN(pdn)) {
1225 pdev->dev.archdata.dma_offset = enable_ddw(pdev, pdn);
1226 if (pdev->dev.archdata.dma_offset)
1233 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1236 struct direct_window *window;
1237 struct memory_notify *arg = data;
1241 case MEM_GOING_ONLINE:
1242 spin_lock(&direct_window_list_lock);
1243 list_for_each_entry(window, &direct_window_list, list) {
1244 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1245 arg->nr_pages, window->prop);
1248 spin_unlock(&direct_window_list_lock);
1250 case MEM_CANCEL_ONLINE:
1252 spin_lock(&direct_window_list_lock);
1253 list_for_each_entry(window, &direct_window_list, list) {
1254 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1255 arg->nr_pages, window->prop);
1258 spin_unlock(&direct_window_list_lock);
1263 if (ret && action != MEM_CANCEL_ONLINE)
1269 static struct notifier_block iommu_mem_nb = {
1270 .notifier_call = iommu_mem_notifier,
1273 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1275 int err = NOTIFY_OK;
1276 struct of_reconfig_data *rd = data;
1277 struct device_node *np = rd->dn;
1278 struct pci_dn *pci = PCI_DN(np);
1279 struct direct_window *window;
1282 case OF_RECONFIG_DETACH_NODE:
1284 * Removing the property will invoke the reconfig
1285 * notifier again, which causes dead-lock on the
1286 * read-write semaphore of the notifier chain. So
1287 * we have to remove the property when releasing
1290 remove_ddw(np, false);
1291 if (pci && pci->table_group)
1292 iommu_pseries_free_group(pci->table_group,
1295 spin_lock(&direct_window_list_lock);
1296 list_for_each_entry(window, &direct_window_list, list) {
1297 if (window->device == np) {
1298 list_del(&window->list);
1303 spin_unlock(&direct_window_list_lock);
1312 static struct notifier_block iommu_reconfig_nb = {
1313 .notifier_call = iommu_reconfig_notifier,
1316 /* These are called very early. */
1317 void iommu_init_early_pSeries(void)
1319 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1322 if (firmware_has_feature(FW_FEATURE_LPAR)) {
1323 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1324 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1326 pseries_pci_controller_ops.iommu_bypass_supported =
1327 iommu_bypass_supported_pSeriesLP;
1329 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1330 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1334 of_reconfig_notifier_register(&iommu_reconfig_nb);
1335 register_memory_notifier(&iommu_mem_nb);
1337 set_pci_dma_ops(&dma_iommu_ops);
1340 static int __init disable_multitce(char *str)
1342 if (strcmp(str, "off") == 0 &&
1343 firmware_has_feature(FW_FEATURE_LPAR) &&
1344 firmware_has_feature(FW_FEATURE_MULTITCE)) {
1345 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1346 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1351 __setup("multitce=", disable_multitce);
1353 static int tce_iommu_bus_notifier(struct notifier_block *nb,
1354 unsigned long action, void *data)
1356 struct device *dev = data;
1359 case BUS_NOTIFY_DEL_DEVICE:
1360 iommu_del_device(dev);
1367 static struct notifier_block tce_iommu_bus_nb = {
1368 .notifier_call = tce_iommu_bus_notifier,
1371 static int __init tce_iommu_bus_notifier_init(void)
1373 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
1376 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);