arch/powerpc/platforms/pseries/iommu.c

   1 /*
   2  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
   3  *
   4  * Rewrite, cleanup:
   5  *
   6  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   7  * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
   8  *
   9  * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/types.h>
  29 #include <linux/slab.h>
  30 #include <linux/mm.h>
  31 #include <linux/memblock.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/string.h>
  34 #include <linux/pci.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/crash_dump.h>
  37 #include <linux/memory.h>
  38 #include <linux/of.h>
  39 #include <linux/iommu.h>
  40 #include <linux/rculist.h>
  41 #include <asm/io.h>
  42 #include <asm/prom.h>
  43 #include <asm/rtas.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/firmware.h>
  48 #include <asm/tce.h>
  49 #include <asm/ppc-pci.h>
  50 #include <asm/udbg.h>
  51 #include <asm/mmzone.h>
  52 #include <asm/plpar_wrappers.h>
  53
  54 #include "pseries.h"
  55
  56 static struct iommu_table_group *iommu_pseries_alloc_group(int node)
  57 {
  58         struct iommu_table_group *table_group = NULL;
  59         struct iommu_table *tbl = NULL;
  60         struct iommu_table_group_link *tgl = NULL;
  61
  62         table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
  63                            node);
  64         if (!table_group)
  65                 goto fail_exit;
  66
  67         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
  68         if (!tbl)
  69                 goto fail_exit;
  70
  71         tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
  72                         node);
  73         if (!tgl)
  74                 goto fail_exit;
  75
  76         INIT_LIST_HEAD_RCU(&tbl->it_group_list);
  77         tgl->table_group = table_group;
  78         list_add_rcu(&tgl->next, &tbl->it_group_list);
  79
  80         table_group->tables[0] = tbl;
  81
  82         return table_group;
  83
  84 fail_exit:
  85         kfree(tgl);
  86         kfree(table_group);
  87         kfree(tbl);
  88
  89         return NULL;
  90 }
  91
  92 static void iommu_pseries_free_group(struct iommu_table_group *table_group,
  93                 const char *node_name)
  94 {
  95         struct iommu_table *tbl;
  96 #ifdef CONFIG_IOMMU_API
  97         struct iommu_table_group_link *tgl;
  98 #endif
  99
 100         if (!table_group)
 101                 return;
 102
 103         tbl = table_group->tables[0];
 104 #ifdef CONFIG_IOMMU_API
 105         tgl = list_first_entry_or_null(&tbl->it_group_list,
 106                         struct iommu_table_group_link, next);
 107
 108         WARN_ON_ONCE(!tgl);
 109         if (tgl) {
 110                 list_del_rcu(&tgl->next);
 111                 kfree(tgl);
 112         }
 113         if (table_group->group) {
 114                 iommu_group_put(table_group->group);
 115                 BUG_ON(table_group->group);
 116         }
 117 #endif
 118         iommu_free_table(tbl, node_name);
 119
 120         kfree(table_group);
 121 }
 122
 123 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
 124                                       __be64 *startp, __be64 *endp)
 125 {
 126         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 127         unsigned long start, end, inc;
 128
 129         start = __pa(startp);
 130         end = __pa(endp);
 131         inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
 132
 133         /* If this is non-zero, change the format.  We shift the
 134          * address and or in the magic from the device tree. */
 135         if (tbl->it_busno) {
 136                 start <<= 12;
 137                 end <<= 12;
 138                 inc <<= 12;
 139                 start |= tbl->it_busno;
 140                 end |= tbl->it_busno;
 141         }
 142
 143         end |= inc - 1; /* round up end to be different than start */
 144
 145         mb(); /* Make sure TCEs in memory are written */
 146         while (start <= end) {
 147                 out_be64(invalidate, start);
 148                 start += inc;
 149         }
 150 }
 151
 152 static int tce_build_pSeries(struct iommu_table *tbl, long index,
 153                               long npages, unsigned long uaddr,
 154                               enum dma_data_direction direction,
 155                               struct dma_attrs *attrs)
 156 {
 157         u64 proto_tce;
 158         __be64 *tcep, *tces;
 159         u64 rpn;
 160
 161         proto_tce = TCE_PCI_READ; // Read allowed
 162
 163         if (direction != DMA_TO_DEVICE)
 164                 proto_tce |= TCE_PCI_WRITE;
 165
 166         tces = tcep = ((__be64 *)tbl->it_base) + index;
 167
 168         while (npages--) {
 169                 /* can't move this out since we might cross MEMBLOCK boundary */
 170                 rpn = __pa(uaddr) >> TCE_SHIFT;
 171                 *tcep = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 172
 173                 uaddr += TCE_PAGE_SIZE;
 174                 tcep++;
 175         }
 176
 177         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 178                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 179         return 0;
 180 }
 181
 182
 183 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
 184 {
 185         __be64 *tcep, *tces;
 186
 187         tces = tcep = ((__be64 *)tbl->it_base) + index;
 188
 189         while (npages--)
 190                 *(tcep++) = 0;
 191
 192         if (tbl->it_type & TCE_PCI_SWINV_FREE)
 193                 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
 194 }
 195
 196 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
 197 {
 198         __be64 *tcep;
 199
 200         tcep = ((__be64 *)tbl->it_base) + index;
 201
 202         return be64_to_cpu(*tcep);
 203 }
 204
 205 static void tce_free_pSeriesLP(unsigned long liobn, long, long);
 206 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
 207
 208 static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift,
 209                                 long npages, unsigned long uaddr,
 210                                 enum dma_data_direction direction,
 211                                 struct dma_attrs *attrs)
 212 {
 213         u64 rc = 0;
 214         u64 proto_tce, tce;
 215         u64 rpn;
 216         int ret = 0;
 217         long tcenum_start = tcenum, npages_start = npages;
 218
 219         rpn = __pa(uaddr) >> tceshift;
 220         proto_tce = TCE_PCI_READ;
 221         if (direction != DMA_TO_DEVICE)
 222                 proto_tce |= TCE_PCI_WRITE;
 223
 224         while (npages--) {
 225                 tce = proto_tce | (rpn & TCE_RPN_MASK) << tceshift;
 226                 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce);
 227
 228                 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 229                         ret = (int)rc;
 230                         tce_free_pSeriesLP(liobn, tcenum_start,
 231                                            (npages_start - (npages + 1)));
 232                         break;
 233                 }
 234
 235                 if (rc && printk_ratelimit()) {
 236                         printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 237                         printk("\tindex   = 0x%llx\n", (u64)liobn);
 238                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 239                         printk("\ttce val = 0x%llx\n", tce );
 240                         dump_stack();
 241                 }
 242
 243                 tcenum++;
 244                 rpn++;
 245         }
 246         return ret;
 247 }
 248
 249 static DEFINE_PER_CPU(__be64 *, tce_page);
 250
 251 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
 252                                      long npages, unsigned long uaddr,
 253                                      enum dma_data_direction direction,
 254                                      struct dma_attrs *attrs)
 255 {
 256         u64 rc = 0;
 257         u64 proto_tce;
 258         __be64 *tcep;
 259         u64 rpn;
 260         long l, limit;
 261         long tcenum_start = tcenum, npages_start = npages;
 262         int ret = 0;
 263         unsigned long flags;
 264
 265         if ((npages == 1) || !firmware_has_feature(FW_FEATURE_MULTITCE)) {
 266                 return tce_build_pSeriesLP(tbl->it_index, tcenum,
 267                                            tbl->it_page_shift, npages, uaddr,
 268                                            direction, attrs);
 269         }
 270
 271         local_irq_save(flags);  /* to protect tcep and the page behind it */
 272
 273         tcep = __this_cpu_read(tce_page);
 274
 275         /* This is safe to do since interrupts are off when we're called
 276          * from iommu_alloc{,_sg}()
 277          */
 278         if (!tcep) {
 279                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 280                 /* If allocation fails, fall back to the loop implementation */
 281                 if (!tcep) {
 282                         local_irq_restore(flags);
 283                         return tce_build_pSeriesLP(tbl->it_index, tcenum,
 284                                         tbl->it_page_shift,
 285                                         npages, uaddr, direction, attrs);
 286                 }
 287                 __this_cpu_write(tce_page, tcep);
 288         }
 289
 290         rpn = __pa(uaddr) >> TCE_SHIFT;
 291         proto_tce = TCE_PCI_READ;
 292         if (direction != DMA_TO_DEVICE)
 293                 proto_tce |= TCE_PCI_WRITE;
 294
 295         /* We can map max one pageful of TCEs at a time */
 296         do {
 297                 /*
 298                  * Set up the page with TCE data, looping through and setting
 299                  * the values.
 300                  */
 301                 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
 302
 303                 for (l = 0; l < limit; l++) {
 304                         tcep[l] = cpu_to_be64(proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT);
 305                         rpn++;
 306                 }
 307
 308                 rc = plpar_tce_put_indirect((u64)tbl->it_index,
 309                                             (u64)tcenum << 12,
 310                                             (u64)__pa(tcep),
 311                                             limit);
 312
 313                 npages -= limit;
 314                 tcenum += limit;
 315         } while (npages > 0 && !rc);
 316
 317         local_irq_restore(flags);
 318
 319         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
 320                 ret = (int)rc;
 321                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
 322                                         (npages_start - (npages + limit)));
 323                 return ret;
 324         }
 325
 326         if (rc && printk_ratelimit()) {
 327                 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 328                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 329                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 330                 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
 331                 dump_stack();
 332         }
 333         return ret;
 334 }
 335
 336 static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long npages)
 337 {
 338         u64 rc;
 339
 340         while (npages--) {
 341                 rc = plpar_tce_put((u64)liobn, (u64)tcenum << 12, 0);
 342
 343                 if (rc && printk_ratelimit()) {
 344                         printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
 345                         printk("\tindex   = 0x%llx\n", (u64)liobn);
 346                         printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 347                         dump_stack();
 348                 }
 349
 350                 tcenum++;
 351         }
 352 }
 353
 354
 355 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
 356 {
 357         u64 rc;
 358
 359         if (!firmware_has_feature(FW_FEATURE_MULTITCE))
 360                 return tce_free_pSeriesLP(tbl->it_index, tcenum, npages);
 361
 362         rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
 363
 364         if (rc && printk_ratelimit()) {
 365                 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
 366                 printk("\trc      = %lld\n", rc);
 367                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 368                 printk("\tnpages  = 0x%llx\n", (u64)npages);
 369                 dump_stack();
 370         }
 371 }
 372
 373 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
 374 {
 375         u64 rc;
 376         unsigned long tce_ret;
 377
 378         rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
 379
 380         if (rc && printk_ratelimit()) {
 381                 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
 382                 printk("\tindex   = 0x%llx\n", (u64)tbl->it_index);
 383                 printk("\ttcenum  = 0x%llx\n", (u64)tcenum);
 384                 dump_stack();
 385         }
 386
 387         return tce_ret;
 388 }
 389
 390 /* this is compatible with cells for the device tree property */
 391 struct dynamic_dma_window_prop {
 392         __be32  liobn;          /* tce table number */
 393         __be64  dma_base;       /* address hi,lo */
 394         __be32  tce_shift;      /* ilog2(tce_page_size) */
 395         __be32  window_shift;   /* ilog2(tce_window_size) */
 396 };
 397
 398 struct direct_window {
 399         struct device_node *device;
 400         const struct dynamic_dma_window_prop *prop;
 401         struct list_head list;
 402 };
 403
 404 /* Dynamic DMA Window support */
 405 struct ddw_query_response {
 406         u32 windows_available;
 407         u32 largest_available_block;
 408         u32 page_size;
 409         u32 migration_capable;
 410 };
 411
 412 struct ddw_create_response {
 413         u32 liobn;
 414         u32 addr_hi;
 415         u32 addr_lo;
 416 };
 417
 418 static LIST_HEAD(direct_window_list);
 419 /* prevents races between memory on/offline and window creation */
 420 static DEFINE_SPINLOCK(direct_window_list_lock);
 421 /* protects initializing window twice for same device */
 422 static DEFINE_MUTEX(direct_window_init_mutex);
 423 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
 424
 425 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
 426                                         unsigned long num_pfn, const void *arg)
 427 {
 428         const struct dynamic_dma_window_prop *maprange = arg;
 429         int rc;
 430         u64 tce_size, num_tce, dma_offset, next;
 431         u32 tce_shift;
 432         long limit;
 433
 434         tce_shift = be32_to_cpu(maprange->tce_shift);
 435         tce_size = 1ULL << tce_shift;
 436         next = start_pfn << PAGE_SHIFT;
 437         num_tce = num_pfn << PAGE_SHIFT;
 438
 439         /* round back to the beginning of the tce page size */
 440         num_tce += next & (tce_size - 1);
 441         next &= ~(tce_size - 1);
 442
 443         /* covert to number of tces */
 444         num_tce |= tce_size - 1;
 445         num_tce >>= tce_shift;
 446
 447         do {
 448                 /*
 449                  * Set up the page with TCE data, looping through and setting
 450                  * the values.
 451                  */
 452                 limit = min_t(long, num_tce, 512);
 453                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 454
 455                 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
 456                                              dma_offset,
 457                                              0, limit);
 458                 next += limit * tce_size;
 459                 num_tce -= limit;
 460         } while (num_tce > 0 && !rc);
 461
 462         return rc;
 463 }
 464
 465 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
 466                                         unsigned long num_pfn, const void *arg)
 467 {
 468         const struct dynamic_dma_window_prop *maprange = arg;
 469         u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn;
 470         __be64 *tcep;
 471         u32 tce_shift;
 472         u64 rc = 0;
 473         long l, limit;
 474
 475         if (!firmware_has_feature(FW_FEATURE_MULTITCE)) {
 476                 unsigned long tceshift = be32_to_cpu(maprange->tce_shift);
 477                 unsigned long dmastart = (start_pfn << PAGE_SHIFT) +
 478                                 be64_to_cpu(maprange->dma_base);
 479                 unsigned long tcenum = dmastart >> tceshift;
 480                 unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift;
 481                 void *uaddr = __va(start_pfn << PAGE_SHIFT);
 482
 483                 return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn),
 484                                 tcenum, tceshift, npages, (unsigned long) uaddr,
 485                                 DMA_BIDIRECTIONAL, 0);
 486         }
 487
 488         local_irq_disable();    /* to protect tcep and the page behind it */
 489         tcep = __this_cpu_read(tce_page);
 490
 491         if (!tcep) {
 492                 tcep = (__be64 *)__get_free_page(GFP_ATOMIC);
 493                 if (!tcep) {
 494                         local_irq_enable();
 495                         return -ENOMEM;
 496                 }
 497                 __this_cpu_write(tce_page, tcep);
 498         }
 499
 500         proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
 501
 502         liobn = (u64)be32_to_cpu(maprange->liobn);
 503         tce_shift = be32_to_cpu(maprange->tce_shift);
 504         tce_size = 1ULL << tce_shift;
 505         next = start_pfn << PAGE_SHIFT;
 506         num_tce = num_pfn << PAGE_SHIFT;
 507
 508         /* round back to the beginning of the tce page size */
 509         num_tce += next & (tce_size - 1);
 510         next &= ~(tce_size - 1);
 511
 512         /* covert to number of tces */
 513         num_tce |= tce_size - 1;
 514         num_tce >>= tce_shift;
 515
 516         /* We can map max one pageful of TCEs at a time */
 517         do {
 518                 /*
 519                  * Set up the page with TCE data, looping through and setting
 520                  * the values.
 521                  */
 522                 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
 523                 dma_offset = next + be64_to_cpu(maprange->dma_base);
 524
 525                 for (l = 0; l < limit; l++) {
 526                         tcep[l] = cpu_to_be64(proto_tce | next);
 527                         next += tce_size;
 528                 }
 529
 530                 rc = plpar_tce_put_indirect(liobn,
 531                                             dma_offset,
 532                                             (u64)__pa(tcep),
 533                                             limit);
 534
 535                 num_tce -= limit;
 536         } while (num_tce > 0 && !rc);
 537
 538         /* error cleanup: caller will clear whole range */
 539
 540         local_irq_enable();
 541         return rc;
 542 }
 543
 544 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
 545                 unsigned long num_pfn, void *arg)
 546 {
 547         return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
 548 }
 549
 550 static void iommu_table_setparms(struct pci_controller *phb,
 551                                  struct device_node *dn,
 552                                  struct iommu_table *tbl)
 553 {
 554         struct device_node *node;
 555         const unsigned long *basep, *sw_inval;
 556         const u32 *sizep;
 557
 558         node = phb->dn;
 559
 560         basep = of_get_property(node, "linux,tce-base", NULL);
 561         sizep = of_get_property(node, "linux,tce-size", NULL);
 562         if (basep == NULL || sizep == NULL) {
 563                 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
 564                                 "missing tce entries !\n", dn->full_name);
 565                 return;
 566         }
 567
 568         tbl->it_base = (unsigned long)__va(*basep);
 569
 570         if (!is_kdump_kernel())
 571                 memset((void *)tbl->it_base, 0, *sizep);
 572
 573         tbl->it_busno = phb->bus->number;
 574         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 575
 576         /* Units of tce entries */
 577         tbl->it_offset = phb->dma_window_base_cur >> tbl->it_page_shift;
 578
 579         /* Test if we are going over 2GB of DMA space */
 580         if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
 581                 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 582                 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
 583         }
 584
 585         phb->dma_window_base_cur += phb->dma_window_size;
 586
 587         /* Set the tce table size - measured in entries */
 588         tbl->it_size = phb->dma_window_size >> tbl->it_page_shift;
 589
 590         tbl->it_index = 0;
 591         tbl->it_blocksize = 16;
 592         tbl->it_type = TCE_PCI;
 593
 594         sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
 595         if (sw_inval) {
 596                 /*
 597                  * This property contains information on how to
 598                  * invalidate the TCE entry.  The first property is
 599                  * the base MMIO address used to invalidate entries.
 600                  * The second property tells us the format of the TCE
 601                  * invalidate (whether it needs to be shifted) and
 602                  * some magic routing info to add to our invalidate
 603                  * command.
 604                  */
 605                 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
 606                 tbl->it_busno = sw_inval[1]; /* overload this with magic */
 607                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 608         }
 609 }
 610
 611 /*
 612  * iommu_table_setparms_lpar
 613  *
 614  * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
 615  */
 616 static void iommu_table_setparms_lpar(struct pci_controller *phb,
 617                                       struct device_node *dn,
 618                                       struct iommu_table *tbl,
 619                                       const __be32 *dma_window)
 620 {
 621         unsigned long offset, size;
 622
 623         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 624
 625         tbl->it_busno = phb->bus->number;
 626         tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
 627         tbl->it_base   = 0;
 628         tbl->it_blocksize  = 16;
 629         tbl->it_type = TCE_PCI;
 630         tbl->it_offset = offset >> tbl->it_page_shift;
 631         tbl->it_size = size >> tbl->it_page_shift;
 632 }
 633
 634 struct iommu_table_ops iommu_table_pseries_ops = {
 635         .set = tce_build_pSeries,
 636         .clear = tce_free_pSeries,
 637         .get = tce_get_pseries
 638 };
 639
 640 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 641 {
 642         struct device_node *dn;
 643         struct iommu_table *tbl;
 644         struct device_node *isa_dn, *isa_dn_orig;
 645         struct device_node *tmp;
 646         struct pci_dn *pci;
 647         int children;
 648
 649         dn = pci_bus_to_OF_node(bus);
 650
 651         pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
 652
 653         if (bus->self) {
 654                 /* This is not a root bus, any setup will be done for the
 655                  * device-side of the bridge in iommu_dev_setup_pSeries().
 656                  */
 657                 return;
 658         }
 659         pci = PCI_DN(dn);
 660
 661         /* Check if the ISA bus on the system is under
 662          * this PHB.
 663          */
 664         isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
 665
 666         while (isa_dn && isa_dn != dn)
 667                 isa_dn = isa_dn->parent;
 668
 669         of_node_put(isa_dn_orig);
 670
 671         /* Count number of direct PCI children of the PHB. */
 672         for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
 673                 children++;
 674
 675         pr_debug("Children: %d\n", children);
 676
 677         /* Calculate amount of DMA window per slot. Each window must be
 678          * a power of two (due to pci_alloc_consistent requirements).
 679          *
 680          * Keep 256MB aside for PHBs with ISA.
 681          */
 682
 683         if (!isa_dn) {
 684                 /* No ISA/IDE - just set window size and return */
 685                 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
 686
 687                 while (pci->phb->dma_window_size * children > 0x80000000ul)
 688                         pci->phb->dma_window_size >>= 1;
 689                 pr_debug("No ISA/IDE, window size is 0x%llx\n",
 690                          pci->phb->dma_window_size);
 691                 pci->phb->dma_window_base_cur = 0;
 692
 693                 return;
 694         }
 695
 696         /* If we have ISA, then we probably have an IDE
 697          * controller too. Allocate a 128MB table but
 698          * skip the first 128MB to avoid stepping on ISA
 699          * space.
 700          */
 701         pci->phb->dma_window_size = 0x8000000ul;
 702         pci->phb->dma_window_base_cur = 0x8000000ul;
 703
 704         pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
 705         tbl = pci->table_group->tables[0];
 706
 707         iommu_table_setparms(pci->phb, dn, tbl);
 708         tbl->it_ops = &iommu_table_pseries_ops;
 709         iommu_init_table(tbl, pci->phb->node);
 710         iommu_register_group(pci->table_group, pci_domain_nr(bus), 0);
 711
 712         /* Divide the rest (1.75GB) among the children */
 713         pci->phb->dma_window_size = 0x80000000ul;
 714         while (pci->phb->dma_window_size * children > 0x70000000ul)
 715                 pci->phb->dma_window_size >>= 1;
 716
 717         pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 718 }
 719
 720 struct iommu_table_ops iommu_table_lpar_multi_ops = {
 721         .set = tce_buildmulti_pSeriesLP,
 722         .clear = tce_freemulti_pSeriesLP,
 723         .get = tce_get_pSeriesLP
 724 };
 725
 726 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
 727 {
 728         struct iommu_table *tbl;
 729         struct device_node *dn, *pdn;
 730         struct pci_dn *ppci;
 731         const __be32 *dma_window = NULL;
 732
 733         dn = pci_bus_to_OF_node(bus);
 734
 735         pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
 736                  dn->full_name);
 737
 738         /* Find nearest ibm,dma-window, walking up the device tree */
 739         for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
 740                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
 741                 if (dma_window != NULL)
 742                         break;
 743         }
 744
 745         if (dma_window == NULL) {
 746                 pr_debug("  no ibm,dma-window property !\n");
 747                 return;
 748         }
 749
 750         ppci = PCI_DN(pdn);
 751
 752         pr_debug("  parent is %s, iommu_table: 0x%p\n",
 753                  pdn->full_name, ppci->table_group);
 754
 755         if (!ppci->table_group) {
 756                 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node);
 757                 tbl = ppci->table_group->tables[0];
 758                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
 759                 tbl->it_ops = &iommu_table_lpar_multi_ops;
 760                 iommu_init_table(tbl, ppci->phb->node);
 761                 iommu_register_group(ppci->table_group,
 762                                 pci_domain_nr(bus), 0);
 763                 pr_debug("  created table: %p\n", ppci->table_group);
 764         }
 765 }
 766
 767
 768 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
 769 {
 770         struct device_node *dn;
 771         struct iommu_table *tbl;
 772
 773         pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
 774
 775         dn = dev->dev.of_node;
 776
 777         /* If we're the direct child of a root bus, then we need to allocate
 778          * an iommu table ourselves. The bus setup code should have setup
 779          * the window sizes already.
 780          */
 781         if (!dev->bus->self) {
 782                 struct pci_controller *phb = PCI_DN(dn)->phb;
 783
 784                 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
 785                 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node);
 786                 tbl = PCI_DN(dn)->table_group->tables[0];
 787                 iommu_table_setparms(phb, dn, tbl);
 788                 tbl->it_ops = &iommu_table_pseries_ops;
 789                 iommu_init_table(tbl, phb->node);
 790                 iommu_register_group(PCI_DN(dn)->table_group,
 791                                 pci_domain_nr(phb->bus), 0);
 792                 set_iommu_table_base(&dev->dev, tbl);
 793                 iommu_add_device(&dev->dev);
 794                 return;
 795         }
 796
 797         /* If this device is further down the bus tree, search upwards until
 798          * an already allocated iommu table is found and use that.
 799          */
 800
 801         while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL)
 802                 dn = dn->parent;
 803
 804         if (dn && PCI_DN(dn)) {
 805                 set_iommu_table_base(&dev->dev,
 806                                 PCI_DN(dn)->table_group->tables[0]);
 807                 iommu_add_device(&dev->dev);
 808         } else
 809                 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
 810                        pci_name(dev));
 811 }
 812
 813 static int __read_mostly disable_ddw;
 814
 815 static int __init disable_ddw_setup(char *str)
 816 {
 817         disable_ddw = 1;
 818         printk(KERN_INFO "ppc iommu: disabling ddw.\n");
 819
 820         return 0;
 821 }
 822
 823 early_param("disable_ddw", disable_ddw_setup);
 824
 825 static void remove_ddw(struct device_node *np, bool remove_prop)
 826 {
 827         struct dynamic_dma_window_prop *dwp;
 828         struct property *win64;
 829         u32 ddw_avail[3];
 830         u64 liobn;
 831         int ret = 0;
 832
 833         ret = of_property_read_u32_array(np, "ibm,ddw-applicable",
 834                                          &ddw_avail[0], 3);
 835
 836         win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
 837         if (!win64)
 838                 return;
 839
 840         if (ret || win64->length < sizeof(*dwp))
 841                 goto delprop;
 842
 843         dwp = win64->value;
 844         liobn = (u64)be32_to_cpu(dwp->liobn);
 845
 846         /* clear the whole window, note the arg is in kernel pages */
 847         ret = tce_clearrange_multi_pSeriesLP(0,
 848                 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
 849         if (ret)
 850                 pr_warning("%s failed to clear tces in window.\n",
 851                          np->full_name);
 852         else
 853                 pr_debug("%s successfully cleared tces in window.\n",
 854                          np->full_name);
 855
 856         ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
 857         if (ret)
 858                 pr_warning("%s: failed to remove direct window: rtas returned "
 859                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 860                         np->full_name, ret, ddw_avail[2], liobn);
 861         else
 862                 pr_debug("%s: successfully removed direct window: rtas returned "
 863                         "%d to ibm,remove-pe-dma-window(%x) %llx\n",
 864                         np->full_name, ret, ddw_avail[2], liobn);
 865
 866 delprop:
 867         if (remove_prop)
 868                 ret = of_remove_property(np, win64);
 869         if (ret)
 870                 pr_warning("%s: failed to remove direct window property: %d\n",
 871                         np->full_name, ret);
 872 }
 873
 874 static u64 find_existing_ddw(struct device_node *pdn)
 875 {
 876         struct direct_window *window;
 877         const struct dynamic_dma_window_prop *direct64;
 878         u64 dma_addr = 0;
 879
 880         spin_lock(&direct_window_list_lock);
 881         /* check if we already created a window and dupe that config if so */
 882         list_for_each_entry(window, &direct_window_list, list) {
 883                 if (window->device == pdn) {
 884                         direct64 = window->prop;
 885                         dma_addr = be64_to_cpu(direct64->dma_base);
 886                         break;
 887                 }
 888         }
 889         spin_unlock(&direct_window_list_lock);
 890
 891         return dma_addr;
 892 }
 893
 894 static int find_existing_ddw_windows(void)
 895 {
 896         int len;
 897         struct device_node *pdn;
 898         struct direct_window *window;
 899         const struct dynamic_dma_window_prop *direct64;
 900
 901         if (!firmware_has_feature(FW_FEATURE_LPAR))
 902                 return 0;
 903
 904         for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
 905                 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
 906                 if (!direct64)
 907                         continue;
 908
 909                 window = kzalloc(sizeof(*window), GFP_KERNEL);
 910                 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
 911                         kfree(window);
 912                         remove_ddw(pdn, true);
 913                         continue;
 914                 }
 915
 916                 window->device = pdn;
 917                 window->prop = direct64;
 918                 spin_lock(&direct_window_list_lock);
 919                 list_add(&window->list, &direct_window_list);
 920                 spin_unlock(&direct_window_list_lock);
 921         }
 922
 923         return 0;
 924 }
 925 machine_arch_initcall(pseries, find_existing_ddw_windows);
 926
 927 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 928                         struct ddw_query_response *query)
 929 {
 930         struct device_node *dn;
 931         struct pci_dn *pdn;
 932         u32 cfg_addr;
 933         u64 buid;
 934         int ret;
 935
 936         /*
 937          * Get the config address and phb buid of the PE window.
 938          * Rely on eeh to retrieve this for us.
 939          * Retrieve them from the pci device, not the node with the
 940          * dma-window property
 941          */
 942         dn = pci_device_to_OF_node(dev);
 943         pdn = PCI_DN(dn);
 944         buid = pdn->phb->buid;
 945         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 946
 947         ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
 948                   cfg_addr, BUID_HI(buid), BUID_LO(buid));
 949         dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
 950                 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
 951                 BUID_LO(buid), ret);
 952         return ret;
 953 }
 954
 955 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
 956                         struct ddw_create_response *create, int page_shift,
 957                         int window_shift)
 958 {
 959         struct device_node *dn;
 960         struct pci_dn *pdn;
 961         u32 cfg_addr;
 962         u64 buid;
 963         int ret;
 964
 965         /*
 966          * Get the config address and phb buid of the PE window.
 967          * Rely on eeh to retrieve this for us.
 968          * Retrieve them from the pci device, not the node with the
 969          * dma-window property
 970          */
 971         dn = pci_device_to_OF_node(dev);
 972         pdn = PCI_DN(dn);
 973         buid = pdn->phb->buid;
 974         cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8));
 975
 976         do {
 977                 /* extra outputs are LIOBN and dma-addr (hi, lo) */
 978                 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create,
 979                                 cfg_addr, BUID_HI(buid), BUID_LO(buid),
 980                                 page_shift, window_shift);
 981         } while (rtas_busy_delay(ret));
 982         dev_info(&dev->dev,
 983                 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
 984                 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
 985                  cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
 986                  window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
 987
 988         return ret;
 989 }
 990
 991 struct failed_ddw_pdn {
 992         struct device_node *pdn;
 993         struct list_head list;
 994 };
 995
 996 static LIST_HEAD(failed_ddw_pdn_list);
 997
 998 /*
 999  * If the PE supports dynamic dma windows, and there is space for a table
1000  * that can map all pages in a linear offset, then setup such a table,
1001  * and record the dma-offset in the struct device.
1002  *
1003  * dev: the pci device we are checking
1004  * pdn: the parent pe node with the ibm,dma_window property
1005  * Future: also check if we can remap the base window for our base page size
1006  *
1007  * returns the dma offset for use by dma_set_mask
1008  */
1009 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
1010 {
1011         int len, ret;
1012         struct ddw_query_response query;
1013         struct ddw_create_response create;
1014         int page_shift;
1015         u64 dma_addr, max_addr;
1016         struct device_node *dn;
1017         u32 ddw_avail[3];
1018         struct direct_window *window;
1019         struct property *win64;
1020         struct dynamic_dma_window_prop *ddwprop;
1021         struct failed_ddw_pdn *fpdn;
1022
1023         mutex_lock(&direct_window_init_mutex);
1024
1025         dma_addr = find_existing_ddw(pdn);
1026         if (dma_addr != 0)
1027                 goto out_unlock;
1028
1029         /*
1030          * If we already went through this for a previous function of
1031          * the same device and failed, we don't want to muck with the
1032          * DMA window again, as it will race with in-flight operations
1033          * and can lead to EEHs. The above mutex protects access to the
1034          * list.
1035          */
1036         list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
1037                 if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
1038                         goto out_unlock;
1039         }
1040
1041         /*
1042          * the ibm,ddw-applicable property holds the tokens for:
1043          * ibm,query-pe-dma-window
1044          * ibm,create-pe-dma-window
1045          * ibm,remove-pe-dma-window
1046          * for the given node in that order.
1047          * the property is actually in the parent, not the PE
1048          */
1049         ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable",
1050                                          &ddw_avail[0], 3);
1051         if (ret)
1052                 goto out_failed;
1053
1054        /*
1055          * Query if there is a second window of size to map the
1056          * whole partition.  Query returns number of windows, largest
1057          * block assigned to PE (partition endpoint), and two bitmasks
1058          * of page sizes: supported and supported for migrate-dma.
1059          */
1060         dn = pci_device_to_OF_node(dev);
1061         ret = query_ddw(dev, ddw_avail, &query);
1062         if (ret != 0)
1063                 goto out_failed;
1064
1065         if (query.windows_available == 0) {
1066                 /*
1067                  * no additional windows are available for this device.
1068                  * We might be able to reallocate the existing window,
1069                  * trading in for a larger page size.
1070                  */
1071                 dev_dbg(&dev->dev, "no free dynamic windows");
1072                 goto out_failed;
1073         }
1074         if (query.page_size & 4) {
1075                 page_shift = 24; /* 16MB */
1076         } else if (query.page_size & 2) {
1077                 page_shift = 16; /* 64kB */
1078         } else if (query.page_size & 1) {
1079                 page_shift = 12; /* 4kB */
1080         } else {
1081                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1082                           query.page_size);
1083                 goto out_failed;
1084         }
1085         /* verify the window * number of ptes will map the partition */
1086         /* check largest block * page size > max memory hotplug addr */
1087         max_addr = memory_hotplug_max();
1088         if (query.largest_available_block < (max_addr >> page_shift)) {
1089                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1090                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
1091                           1ULL << page_shift);
1092                 goto out_failed;
1093         }
1094         len = order_base_2(max_addr);
1095         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1096         if (!win64) {
1097                 dev_info(&dev->dev,
1098                         "couldn't allocate property for 64bit dma window\n");
1099                 goto out_failed;
1100         }
1101         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1102         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1103         win64->length = sizeof(*ddwprop);
1104         if (!win64->name || !win64->value) {
1105                 dev_info(&dev->dev,
1106                         "couldn't allocate property name and value\n");
1107                 goto out_free_prop;
1108         }
1109
1110         ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1111         if (ret != 0)
1112                 goto out_free_prop;
1113
1114         ddwprop->liobn = cpu_to_be32(create.liobn);
1115         ddwprop->dma_base = cpu_to_be64(((u64)create.addr_hi << 32) |
1116                         create.addr_lo);
1117         ddwprop->tce_shift = cpu_to_be32(page_shift);
1118         ddwprop->window_shift = cpu_to_be32(len);
1119
1120         dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1121                   create.liobn, dn->full_name);
1122
1123         window = kzalloc(sizeof(*window), GFP_KERNEL);
1124         if (!window)
1125                 goto out_clear_window;
1126
1127         ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1128                         win64->value, tce_setrange_multi_pSeriesLP_walk);
1129         if (ret) {
1130                 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1131                          dn->full_name, ret);
1132                 goto out_free_window;
1133         }
1134
1135         ret = of_add_property(pdn, win64);
1136         if (ret) {
1137                 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1138                          pdn->full_name, ret);
1139                 goto out_free_window;
1140         }
1141
1142         window->device = pdn;
1143         window->prop = ddwprop;
1144         spin_lock(&direct_window_list_lock);
1145         list_add(&window->list, &direct_window_list);
1146         spin_unlock(&direct_window_list_lock);
1147
1148         dma_addr = be64_to_cpu(ddwprop->dma_base);
1149         goto out_unlock;
1150
1151 out_free_window:
1152         kfree(window);
1153
1154 out_clear_window:
1155         remove_ddw(pdn, true);
1156
1157 out_free_prop:
1158         kfree(win64->name);
1159         kfree(win64->value);
1160         kfree(win64);
1161
1162 out_failed:
1163
1164         fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
1165         if (!fpdn)
1166                 goto out_unlock;
1167         fpdn->pdn = pdn;
1168         list_add(&fpdn->list, &failed_ddw_pdn_list);
1169
1170 out_unlock:
1171         mutex_unlock(&direct_window_init_mutex);
1172         return dma_addr;
1173 }
1174
1175 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1176 {
1177         struct device_node *pdn, *dn;
1178         struct iommu_table *tbl;
1179         const __be32 *dma_window = NULL;
1180         struct pci_dn *pci;
1181
1182         pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1183
1184         /* dev setup for LPAR is a little tricky, since the device tree might
1185          * contain the dma-window properties per-device and not necessarily
1186          * for the bus. So we need to search upwards in the tree until we
1187          * either hit a dma-window property, OR find a parent with a table
1188          * already allocated.
1189          */
1190         dn = pci_device_to_OF_node(dev);
1191         pr_debug("  node is %s\n", dn->full_name);
1192
1193         for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1194              pdn = pdn->parent) {
1195                 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1196                 if (dma_window)
1197                         break;
1198         }
1199
1200         if (!pdn || !PCI_DN(pdn)) {
1201                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1202                        "no DMA window found for pci dev=%s dn=%s\n",
1203                                  pci_name(dev), of_node_full_name(dn));
1204                 return;
1205         }
1206         pr_debug("  parent is %s\n", pdn->full_name);
1207
1208         pci = PCI_DN(pdn);
1209         if (!pci->table_group) {
1210                 pci->table_group = iommu_pseries_alloc_group(pci->phb->node);
1211                 tbl = pci->table_group->tables[0];
1212                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1213                 tbl->it_ops = &iommu_table_lpar_multi_ops;
1214                 iommu_init_table(tbl, pci->phb->node);
1215                 iommu_register_group(pci->table_group,
1216                                 pci_domain_nr(pci->phb->bus), 0);
1217                 pr_debug("  created table: %p\n", pci->table_group);
1218         } else {
1219                 pr_debug("  found DMA window, table: %p\n", pci->table_group);
1220         }
1221
1222         set_iommu_table_base(&dev->dev, pci->table_group->tables[0]);
1223         iommu_add_device(&dev->dev);
1224 }
1225
1226 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1227 {
1228         bool ddw_enabled = false;
1229         struct device_node *pdn, *dn;
1230         struct pci_dev *pdev;
1231         const __be32 *dma_window = NULL;
1232         u64 dma_offset;
1233
1234         if (!dev->dma_mask)
1235                 return -EIO;
1236
1237         if (!dev_is_pci(dev))
1238                 goto check_mask;
1239
1240         pdev = to_pci_dev(dev);
1241
1242         /* only attempt to use a new window if 64-bit DMA is requested */
1243         if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1244                 dn = pci_device_to_OF_node(pdev);
1245                 dev_dbg(dev, "node is %s\n", dn->full_name);
1246
1247                 /*
1248                  * the device tree might contain the dma-window properties
1249                  * per-device and not necessarily for the bus. So we need to
1250                  * search upwards in the tree until we either hit a dma-window
1251                  * property, OR find a parent with a table already allocated.
1252                  */
1253                 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->table_group;
1254                                 pdn = pdn->parent) {
1255                         dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1256                         if (dma_window)
1257                                 break;
1258                 }
1259                 if (pdn && PCI_DN(pdn)) {
1260                         dma_offset = enable_ddw(pdev, pdn);
1261                         if (dma_offset != 0) {
1262                                 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1263                                 set_dma_offset(dev, dma_offset);
1264                                 set_dma_ops(dev, &dma_direct_ops);
1265                                 ddw_enabled = true;
1266                         }
1267                 }
1268         }
1269
1270         /* fall back on iommu ops */
1271         if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1272                 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1273                 set_dma_ops(dev, &dma_iommu_ops);
1274         }
1275
1276 check_mask:
1277         if (!dma_supported(dev, dma_mask))
1278                 return -EIO;
1279
1280         *dev->dma_mask = dma_mask;
1281         return 0;
1282 }
1283
1284 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1285 {
1286         if (!dev->dma_mask)
1287                 return 0;
1288
1289         if (!disable_ddw && dev_is_pci(dev)) {
1290                 struct pci_dev *pdev = to_pci_dev(dev);
1291                 struct device_node *dn;
1292
1293                 dn = pci_device_to_OF_node(pdev);
1294
1295                 /* search upwards for ibm,dma-window */
1296                 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->table_group;
1297                                 dn = dn->parent)
1298                         if (of_get_property(dn, "ibm,dma-window", NULL))
1299                                 break;
1300                 /* if there is a ibm,ddw-applicable property require 64 bits */
1301                 if (dn && PCI_DN(dn) &&
1302                                 of_get_property(dn, "ibm,ddw-applicable", NULL))
1303                         return DMA_BIT_MASK(64);
1304         }
1305
1306         return dma_iommu_ops.get_required_mask(dev);
1307 }
1308
1309 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1310                 void *data)
1311 {
1312         struct direct_window *window;
1313         struct memory_notify *arg = data;
1314         int ret = 0;
1315
1316         switch (action) {
1317         case MEM_GOING_ONLINE:
1318                 spin_lock(&direct_window_list_lock);
1319                 list_for_each_entry(window, &direct_window_list, list) {
1320                         ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1321                                         arg->nr_pages, window->prop);
1322                         /* XXX log error */
1323                 }
1324                 spin_unlock(&direct_window_list_lock);
1325                 break;
1326         case MEM_CANCEL_ONLINE:
1327         case MEM_OFFLINE:
1328                 spin_lock(&direct_window_list_lock);
1329                 list_for_each_entry(window, &direct_window_list, list) {
1330                         ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1331                                         arg->nr_pages, window->prop);
1332                         /* XXX log error */
1333                 }
1334                 spin_unlock(&direct_window_list_lock);
1335                 break;
1336         default:
1337                 break;
1338         }
1339         if (ret && action != MEM_CANCEL_ONLINE)
1340                 return NOTIFY_BAD;
1341
1342         return NOTIFY_OK;
1343 }
1344
1345 static struct notifier_block iommu_mem_nb = {
1346         .notifier_call = iommu_mem_notifier,
1347 };
1348
1349 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
1350 {
1351         int err = NOTIFY_OK;
1352         struct of_reconfig_data *rd = data;
1353         struct device_node *np = rd->dn;
1354         struct pci_dn *pci = PCI_DN(np);
1355         struct direct_window *window;
1356
1357         switch (action) {
1358         case OF_RECONFIG_DETACH_NODE:
1359                 /*
1360                  * Removing the property will invoke the reconfig
1361                  * notifier again, which causes dead-lock on the
1362                  * read-write semaphore of the notifier chain. So
1363                  * we have to remove the property when releasing
1364                  * the device node.
1365                  */
1366                 remove_ddw(np, false);
1367                 if (pci && pci->table_group)
1368                         iommu_pseries_free_group(pci->table_group,
1369                                         np->full_name);
1370
1371                 spin_lock(&direct_window_list_lock);
1372                 list_for_each_entry(window, &direct_window_list, list) {
1373                         if (window->device == np) {
1374                                 list_del(&window->list);
1375                                 kfree(window);
1376                                 break;
1377                         }
1378                 }
1379                 spin_unlock(&direct_window_list_lock);
1380                 break;
1381         default:
1382                 err = NOTIFY_DONE;
1383                 break;
1384         }
1385         return err;
1386 }
1387
1388 static struct notifier_block iommu_reconfig_nb = {
1389         .notifier_call = iommu_reconfig_notifier,
1390 };
1391
1392 /* These are called very early. */
1393 void iommu_init_early_pSeries(void)
1394 {
1395         if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1396                 return;
1397
1398         if (firmware_has_feature(FW_FEATURE_LPAR)) {
1399                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1400                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1401                 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1402                 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1403         } else {
1404                 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1405                 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1406         }
1407
1408
1409         of_reconfig_notifier_register(&iommu_reconfig_nb);
1410         register_memory_notifier(&iommu_mem_nb);
1411
1412         set_pci_dma_ops(&dma_iommu_ops);
1413 }
1414
1415 static int __init disable_multitce(char *str)
1416 {
1417         if (strcmp(str, "off") == 0 &&
1418             firmware_has_feature(FW_FEATURE_LPAR) &&
1419             firmware_has_feature(FW_FEATURE_MULTITCE)) {
1420                 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1421                 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1422         }
1423         return 1;
1424 }
1425
1426 __setup("multitce=", disable_multitce);
1427
1428 machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);