2 * PS3 Platform spu routines.
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/mmzone.h>
25 #include <linux/export.h>
30 #include <asm/spu_priv1.h>
31 #include <asm/lv1call.h>
34 #include "../cell/spufs/spufs.h"
37 /* spu_management_ops */
40 * enum spe_type - Type of spe to create.
41 * @spe_type_logical: Standard logical spe.
43 * For use with lv1_construct_logical_spe(). The current HV does not support
44 * any types other than those listed.
52 * struct spe_shadow - logical spe shadow register area.
54 * Read-only shadow of spe registers.
58 u8 padding_0140[0x0140];
59 u64 int_status_class0_RW; /* 0x0140 */
60 u64 int_status_class1_RW; /* 0x0148 */
61 u64 int_status_class2_RW; /* 0x0150 */
62 u8 padding_0158[0x0610-0x0158];
63 u64 mfc_dsisr_RW; /* 0x0610 */
64 u8 padding_0618[0x0620-0x0618];
65 u64 mfc_dar_RW; /* 0x0620 */
66 u8 padding_0628[0x0800-0x0628];
67 u64 mfc_dsipr_R; /* 0x0800 */
68 u8 padding_0808[0x0810-0x0808];
69 u64 mfc_lscrr_R; /* 0x0810 */
70 u8 padding_0818[0x0c00-0x0818];
71 u64 mfc_cer_R; /* 0x0c00 */
72 u8 padding_0c08[0x0f00-0x0c08];
73 u64 spe_execution_status; /* 0x0f00 */
74 u8 padding_0f08[0x1000-0x0f08];
78 * enum spe_ex_state - Logical spe execution state.
79 * @spe_ex_state_unexecutable: Uninitialized.
80 * @spe_ex_state_executable: Enabled, not ready.
81 * @spe_ex_state_executed: Ready for use.
83 * The execution state (status) of the logical spe as reported in
84 * struct spe_shadow:spe_execution_status.
88 SPE_EX_STATE_UNEXECUTABLE = 0,
89 SPE_EX_STATE_EXECUTABLE = 2,
90 SPE_EX_STATE_EXECUTED = 3,
94 * struct priv1_cache - Cached values of priv1 registers.
95 * @masks[]: Array of cached spe interrupt masks, indexed by class.
96 * @sr1: Cached mfc_sr1 register.
97 * @tclass_id: Cached mfc_tclass_id register.
107 * struct spu_pdata - Platform state variables.
108 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
109 * @resource_id: HV spe resource id returned by
110 * ps3_repository_read_spe_resource_id().
111 * @priv2_addr: lpar address of spe priv2 area returned by
112 * lv1_construct_logical_spe().
113 * @shadow_addr: lpar address of spe register shadow area returned by
114 * lv1_construct_logical_spe().
115 * @shadow: Virtual (ioremap) address of spe register shadow area.
116 * @cache: Cached values of priv1 registers.
124 struct spe_shadow __iomem *shadow;
125 struct priv1_cache cache;
128 static struct spu_pdata *spu_pdata(struct spu *spu)
133 #define dump_areas(_a, _b, _c, _d, _e) \
134 _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
135 static void _dump_areas(unsigned int spe_id, unsigned long priv2,
136 unsigned long problem, unsigned long ls, unsigned long shadow,
137 const char* func, int line)
139 pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
140 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
141 pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
142 pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
143 pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
146 u64 ps3_get_spe_id(void *arg)
148 return spu_pdata(arg)->spe_id;
150 EXPORT_SYMBOL_GPL(ps3_get_spe_id);
152 static unsigned long get_vas_id(void)
156 lv1_get_logical_ppe_id(&id);
157 lv1_get_virtual_address_space_id_of_ppe(&id);
162 static int __init construct_spu(struct spu *spu)
167 u64 local_store_phys;
169 result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
170 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
171 &spu_pdata(spu)->priv2_addr, &problem_phys,
172 &local_store_phys, &unused,
173 &spu_pdata(spu)->shadow_addr,
174 &spu_pdata(spu)->spe_id);
175 spu->problem_phys = problem_phys;
176 spu->local_store_phys = local_store_phys;
179 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
180 __func__, __LINE__, ps3_result(result));
187 static void spu_unmap(struct spu *spu)
190 iounmap(spu->problem);
191 iounmap((__force u8 __iomem *)spu->local_store);
192 iounmap(spu_pdata(spu)->shadow);
196 * setup_areas - Map the spu regions into the address space.
198 * The current HV requires the spu shadow regs to be mapped with the
199 * PTE page protection bits set as read-only (PP=3). This implementation
200 * uses the low level __ioremap() to bypass the page protection settings
201 * inforced by ioremap_prot() to get the needed PTE bits set for the
205 static int __init setup_areas(struct spu *spu)
207 struct table {char* name; unsigned long addr; unsigned long size;};
208 unsigned long shadow_flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL_RO));
210 spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
211 sizeof(struct spe_shadow),
213 if (!spu_pdata(spu)->shadow) {
214 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
218 spu->local_store = (__force void *)ioremap_prot(spu->local_store_phys,
219 LS_SIZE, pgprot_val(pgprot_noncached_wc(__pgprot(0))));
221 if (!spu->local_store) {
222 pr_debug("%s:%d: ioremap local_store failed\n",
227 spu->problem = ioremap(spu->problem_phys,
228 sizeof(struct spu_problem));
231 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
235 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
236 sizeof(struct spu_priv2));
239 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
243 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
244 spu->problem_phys, spu->local_store_phys,
245 spu_pdata(spu)->shadow_addr);
246 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
247 (unsigned long)spu->problem, (unsigned long)spu->local_store,
248 (unsigned long)spu_pdata(spu)->shadow);
258 static int __init setup_interrupts(struct spu *spu)
262 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
268 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
274 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
283 ps3_spe_irq_destroy(spu->irqs[1]);
285 ps3_spe_irq_destroy(spu->irqs[0]);
287 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
291 static int __init enable_spu(struct spu *spu)
295 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
296 spu_pdata(spu)->resource_id);
299 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
300 __func__, __LINE__, ps3_result(result));
304 result = setup_areas(spu);
309 result = setup_interrupts(spu);
312 goto fail_interrupts;
319 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
324 static int ps3_destroy_spu(struct spu *spu)
328 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
330 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
333 ps3_spe_irq_destroy(spu->irqs[2]);
334 ps3_spe_irq_destroy(spu->irqs[1]);
335 ps3_spe_irq_destroy(spu->irqs[0]);
337 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
341 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
350 static int __init ps3_create_spu(struct spu *spu, void *data)
354 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
356 spu->pdata = kzalloc(sizeof(struct spu_pdata),
364 spu_pdata(spu)->resource_id = (unsigned long)data;
366 /* Init cached reg values to HV defaults. */
368 spu_pdata(spu)->cache.sr1 = 0x33;
370 result = construct_spu(spu);
375 /* For now, just go ahead and enable it. */
377 result = enable_spu(spu);
382 /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
384 /* need something better here!!! */
385 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
386 != SPE_EX_STATE_EXECUTED)
393 ps3_destroy_spu(spu);
398 static int __init ps3_enumerate_spus(int (*fn)(void *data))
401 unsigned int num_resource_id;
404 result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
406 pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
410 * For now, just create logical spus equal to the number
411 * of physical spus reserved for the partition.
414 for (i = 0; i < num_resource_id; i++) {
415 enum ps3_spu_resource_type resource_type;
416 unsigned int resource_id;
418 result = ps3_repository_read_spu_resource_id(i,
419 &resource_type, &resource_id);
424 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
425 result = fn((void*)(unsigned long)resource_id);
433 printk(KERN_WARNING "%s:%d: Error initializing spus\n",
438 return num_resource_id;
441 static int ps3_init_affinity(void)
447 * ps3_enable_spu - Enable SPU run control.
449 * An outstanding enhancement for the PS3 would be to add a guard to check
450 * for incorrect access to the spu problem state when the spu context is
451 * disabled. This check could be implemented with a flag added to the spu
452 * context that would inhibit mapping problem state pages, and a routine
453 * to unmap spu problem state pages. When the spu is enabled with
454 * ps3_enable_spu() the flag would be set allowing pages to be mapped,
455 * and when the spu is disabled with ps3_disable_spu() the flag would be
456 * cleared and the mapped problem state pages would be unmapped.
459 static void ps3_enable_spu(struct spu_context *ctx)
463 static void ps3_disable_spu(struct spu_context *ctx)
465 ctx->ops->runcntl_stop(ctx);
468 const struct spu_management_ops spu_management_ps3_ops = {
469 .enumerate_spus = ps3_enumerate_spus,
470 .create_spu = ps3_create_spu,
471 .destroy_spu = ps3_destroy_spu,
472 .enable_spu = ps3_enable_spu,
473 .disable_spu = ps3_disable_spu,
474 .init_affinity = ps3_init_affinity,
479 static void int_mask_and(struct spu *spu, int class, u64 mask)
483 /* are these serialized by caller??? */
484 old_mask = spu_int_mask_get(spu, class);
485 spu_int_mask_set(spu, class, old_mask & mask);
488 static void int_mask_or(struct spu *spu, int class, u64 mask)
492 old_mask = spu_int_mask_get(spu, class);
493 spu_int_mask_set(spu, class, old_mask | mask);
496 static void int_mask_set(struct spu *spu, int class, u64 mask)
498 spu_pdata(spu)->cache.masks[class] = mask;
499 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
500 spu_pdata(spu)->cache.masks[class]);
503 static u64 int_mask_get(struct spu *spu, int class)
505 return spu_pdata(spu)->cache.masks[class];
508 static void int_stat_clear(struct spu *spu, int class, u64 stat)
510 /* Note that MFC_DSISR will be cleared when class1[MF] is set. */
512 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
516 static u64 int_stat_get(struct spu *spu, int class)
520 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
524 static void cpu_affinity_set(struct spu *spu, int cpu)
529 static u64 mfc_dar_get(struct spu *spu)
531 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
534 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
536 /* Nothing to do, cleared in int_stat_clear(). */
539 static u64 mfc_dsisr_get(struct spu *spu)
541 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
544 static void mfc_sdr_setup(struct spu *spu)
549 static void mfc_sr1_set(struct spu *spu, u64 sr1)
551 /* Check bits allowed by HV. */
553 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
554 | MFC_STATE1_PROBLEM_STATE_MASK);
556 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
558 spu_pdata(spu)->cache.sr1 = sr1;
559 lv1_set_spe_privilege_state_area_1_register(
560 spu_pdata(spu)->spe_id,
561 offsetof(struct spu_priv1, mfc_sr1_RW),
562 spu_pdata(spu)->cache.sr1);
565 static u64 mfc_sr1_get(struct spu *spu)
567 return spu_pdata(spu)->cache.sr1;
570 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
572 spu_pdata(spu)->cache.tclass_id = tclass_id;
573 lv1_set_spe_privilege_state_area_1_register(
574 spu_pdata(spu)->spe_id,
575 offsetof(struct spu_priv1, mfc_tclass_id_RW),
576 spu_pdata(spu)->cache.tclass_id);
579 static u64 mfc_tclass_id_get(struct spu *spu)
581 return spu_pdata(spu)->cache.tclass_id;
584 static void tlb_invalidate(struct spu *spu)
589 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
594 static u64 resource_allocation_groupID_get(struct spu *spu)
596 return 0; /* No support. */
599 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
604 static u64 resource_allocation_enable_get(struct spu *spu)
606 return 0; /* No support. */
609 const struct spu_priv1_ops spu_priv1_ps3_ops = {
610 .int_mask_and = int_mask_and,
611 .int_mask_or = int_mask_or,
612 .int_mask_set = int_mask_set,
613 .int_mask_get = int_mask_get,
614 .int_stat_clear = int_stat_clear,
615 .int_stat_get = int_stat_get,
616 .cpu_affinity_set = cpu_affinity_set,
617 .mfc_dar_get = mfc_dar_get,
618 .mfc_dsisr_set = mfc_dsisr_set,
619 .mfc_dsisr_get = mfc_dsisr_get,
620 .mfc_sdr_setup = mfc_sdr_setup,
621 .mfc_sr1_set = mfc_sr1_set,
622 .mfc_sr1_get = mfc_sr1_get,
623 .mfc_tclass_id_set = mfc_tclass_id_set,
624 .mfc_tclass_id_get = mfc_tclass_id_get,
625 .tlb_invalidate = tlb_invalidate,
626 .resource_allocation_groupID_set = resource_allocation_groupID_set,
627 .resource_allocation_groupID_get = resource_allocation_groupID_get,
628 .resource_allocation_enable_set = resource_allocation_enable_set,
629 .resource_allocation_enable_get = resource_allocation_enable_get,
632 void ps3_spu_set_platform(void)
634 spu_priv1_ops = &spu_priv1_ps3_ops;
635 spu_management_ops = &spu_management_ps3_ops;