1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011 IBM Corp.
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_buf.h>
21 #include <linux/seq_file.h>
23 #include <linux/of_fdt.h>
24 #include <linux/interrupt.h>
25 #include <linux/bug.h>
26 #include <linux/pci.h>
27 #include <linux/cpufreq.h>
28 #include <linux/memblock.h>
30 #include <asm/machdep.h>
31 #include <asm/firmware.h>
35 #include <asm/kexec.h>
38 #include <asm/setup.h>
39 #include <asm/security_features.h>
44 static bool __init fw_feature_is(const char *state, const char *name,
45 struct device_node *fw_features)
47 struct device_node *np;
50 np = of_get_child_by_name(fw_features, name);
52 rc = of_property_read_bool(np, state);
59 static void __init init_fw_feat_flags(struct device_node *np)
61 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
62 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
64 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
65 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
67 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
68 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
70 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
71 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
73 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
74 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
76 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
77 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
79 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
80 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
82 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
83 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
86 * The features below are enabled by default, so we instead look to see
87 * if firmware has *disabled* them, and clear them if so.
89 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
90 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
92 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
93 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
95 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
96 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
98 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
99 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
101 if (fw_feature_is("enabled", "no-need-l1d-flush-msr-pr-1-to-0", np))
102 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
104 if (fw_feature_is("enabled", "no-need-l1d-flush-kernel-on-user-access", np))
105 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
107 if (fw_feature_is("enabled", "no-need-store-drain-on-priv-state-switch", np))
108 security_ftr_clear(SEC_FTR_STF_BARRIER);
111 static void __init pnv_setup_security_mitigations(void)
113 struct device_node *np, *fw_features;
114 enum l1d_flush_type type;
117 /* Default to fallback in case fw-features are not available */
118 type = L1D_FLUSH_FALLBACK;
120 np = of_find_node_by_name(NULL, "ibm,opal");
121 fw_features = of_get_child_by_name(np, "fw-features");
125 init_fw_feat_flags(fw_features);
126 of_node_put(fw_features);
128 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
129 type = L1D_FLUSH_MTTRIG;
131 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
132 type = L1D_FLUSH_ORI;
136 * The issues addressed by the entry and uaccess flush don't affect P7
137 * or P8, so on bare metal disable them explicitly in case firmware does
138 * not include the features to disable them. POWER9 and newer processors
139 * should have the appropriate firmware flags.
141 if (pvr_version_is(PVR_POWER7) || pvr_version_is(PVR_POWER7p) ||
142 pvr_version_is(PVR_POWER8E) || pvr_version_is(PVR_POWER8NVL) ||
143 pvr_version_is(PVR_POWER8)) {
144 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
145 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
148 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
149 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
150 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
152 setup_rfi_flush(type, enable);
153 setup_count_cache_flush();
155 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
156 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
157 setup_entry_flush(enable);
159 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
160 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
161 setup_uaccess_flush(enable);
166 static void __init pnv_check_guarded_cores(void)
168 struct device_node *dn;
171 for_each_node_by_type(dn, "cpu") {
172 if (of_property_match_string(dn, "status", "bad") >= 0)
177 printk(" _ _______________\n");
178 pr_cont(" | | / \\\n");
179 pr_cont(" | | | WARNING! |\n");
180 pr_cont(" | | | |\n");
181 pr_cont(" | | | It looks like |\n");
182 pr_cont(" |_| | you have %*d |\n", 3, bad_count);
183 pr_cont(" _ | guarded cores |\n");
184 pr_cont(" (_) \\_______________/\n");
188 static void __init pnv_setup_arch(void)
190 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
192 pnv_setup_security_mitigations();
197 /* Setup RTC and NVRAM callbacks */
198 if (firmware_has_feature(FW_FEATURE_OPAL))
201 /* Enable NAP mode */
204 pnv_check_guarded_cores();
211 static void __init pnv_add_hw_description(void)
213 struct device_node *dn;
216 dn = of_find_node_by_path("/ibm,opal/firmware");
220 if (of_property_read_string(dn, "version", &s) == 0 ||
221 of_property_read_string(dn, "git-id", &s) == 0)
222 seq_buf_printf(&ppc_hw_desc, "opal:%s ", s);
224 if (of_property_read_string(dn, "mi-version", &s) == 0)
225 seq_buf_printf(&ppc_hw_desc, "mi:%s ", s);
230 static void __init pnv_init(void)
232 pnv_add_hw_description();
235 * Initialize the LPC bus now so that legacy serial
236 * ports can be found on it
240 #ifdef CONFIG_HVC_OPAL
241 if (firmware_has_feature(FW_FEATURE_OPAL))
242 hvc_opal_init_early();
245 add_preferred_console("hvc", 0, NULL);
247 #ifdef CONFIG_PPC_64S_HASH_MMU
248 if (!radix_enabled()) {
249 size_t size = sizeof(struct slb_entry) * mmu_slb_size;
252 /* Allocate per cpu area to save old slb contents during MCE */
253 for_each_possible_cpu(i) {
254 paca_ptrs[i]->mce_faulty_slbs =
255 memblock_alloc_node(size,
256 __alignof__(struct slb_entry),
263 static void __init pnv_init_IRQ(void)
265 /* Try using a XIVE if available, otherwise use a XICS */
266 if (!xive_native_init())
269 WARN_ON(!ppc_md.get_irq);
272 static void pnv_show_cpuinfo(struct seq_file *m)
274 struct device_node *root;
275 const char *model = "";
277 root = of_find_node_by_path("/");
279 model = of_get_property(root, "model", NULL);
280 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
281 if (firmware_has_feature(FW_FEATURE_OPAL))
282 seq_printf(m, "firmware\t: OPAL\n");
284 seq_printf(m, "firmware\t: BML\n");
287 seq_printf(m, "MMU\t\t: Radix\n");
289 seq_printf(m, "MMU\t\t: Hash\n");
292 static void pnv_prepare_going_down(void)
295 * Disable all notifiers from OPAL, we can't
296 * service interrupts anymore anyway
298 opal_event_shutdown();
300 /* Print flash update message if one is scheduled. */
301 opal_flash_update_print_message();
308 static void __noreturn pnv_restart(char *cmd)
312 pnv_prepare_going_down();
315 if (!cmd || !strlen(cmd))
316 rc = opal_cec_reboot();
317 else if (strcmp(cmd, "full") == 0)
318 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
319 else if (strcmp(cmd, "mpipl") == 0)
320 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
321 else if (strcmp(cmd, "error") == 0)
322 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
323 else if (strcmp(cmd, "fast") == 0)
324 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
326 rc = OPAL_UNSUPPORTED;
328 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
329 /* Opal is busy wait for some time and retry */
330 opal_poll_events(NULL);
333 } else if (cmd && rc) {
334 /* Unknown error while issuing reboot */
335 if (rc == OPAL_UNSUPPORTED)
336 pr_err("Unsupported '%s' reboot.\n", cmd);
338 pr_err("Unable to issue '%s' reboot. Err=%ld\n",
340 pr_info("Forcing a cec-reboot\n");
344 } else if (rc != OPAL_SUCCESS) {
345 /* Unknown error while issuing cec-reboot */
346 pr_err("Unable to reboot. Err=%ld\n", rc);
349 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
352 opal_poll_events(NULL);
355 static void __noreturn pnv_power_off(void)
359 pnv_prepare_going_down();
361 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
362 rc = opal_cec_power_down(0);
363 if (rc == OPAL_BUSY_EVENT)
364 opal_poll_events(NULL);
369 opal_poll_events(NULL);
372 static void __noreturn pnv_halt(void)
377 static void pnv_progress(char *s, unsigned short hex)
381 static void pnv_shutdown(void)
383 /* Let the PCI code clear up IODA tables */
387 * Stop OPAL activity: Unregister all OPAL interrupts so they
388 * don't fire up while we kexec and make sure all potentially
389 * DMA'ing ops are complete (such as dump retrieval).
394 #ifdef CONFIG_KEXEC_CORE
395 static void pnv_kexec_wait_secondaries_down(void)
397 int my_cpu, i, notified = -1;
401 for_each_online_cpu(i) {
403 int64_t rc, timeout = 1000;
409 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
411 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
415 printk(KERN_INFO "kexec: waiting for cpu %d "
416 "(physical %d) to enter OPAL\n",
417 i, paca_ptrs[i]->hw_cpu_id);
422 * On crash secondaries might be unreachable or hung,
423 * so timeout if we've waited too long
426 if (timeout-- == 0) {
427 printk(KERN_ERR "kexec: timed out waiting for "
428 "cpu %d (physical %d) to enter OPAL\n",
429 i, paca_ptrs[i]->hw_cpu_id);
436 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
443 xics_kexec_teardown_cpu(secondary);
445 /* On OPAL, we return all CPUs to firmware */
446 if (!firmware_has_feature(FW_FEATURE_OPAL))
450 /* Return secondary CPUs to firmware on OPAL v3 */
452 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
455 /* Return the CPU to OPAL */
458 /* Primary waits for the secondaries to have reached OPAL */
459 pnv_kexec_wait_secondaries_down();
461 /* Switch XIVE back to emulation mode */
466 * We might be running as little-endian - now that interrupts
467 * are disabled, reset the HILE bit to big-endian so we don't
468 * take interrupts in the wrong endian later
470 * We reinit to enable both radix and hash on P9 to ensure
471 * the mode used by the next kernel is always supported.
473 reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
474 if (cpu_has_feature(CPU_FTR_ARCH_300))
475 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
476 OPAL_REINIT_CPUS_MMU_HASH;
477 opal_reinit_cpus(reinit_flags);
480 #endif /* CONFIG_KEXEC_CORE */
482 #ifdef CONFIG_MEMORY_HOTPLUG
483 static unsigned long pnv_memory_block_size(void)
485 return memory_block_size;
489 static void __init pnv_setup_machdep_opal(void)
491 ppc_md.get_boot_time = opal_get_boot_time;
492 ppc_md.restart = pnv_restart;
493 pm_power_off = pnv_power_off;
494 ppc_md.halt = pnv_halt;
495 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
496 ppc_md.machine_check_exception = opal_machine_check;
497 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
498 if (opal_check_token(OPAL_HANDLE_HMI2))
499 ppc_md.hmi_exception_early = opal_hmi_exception_early2;
501 ppc_md.hmi_exception_early = opal_hmi_exception_early;
502 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
505 static int __init pnv_probe(void)
507 if (firmware_has_feature(FW_FEATURE_OPAL))
508 pnv_setup_machdep_opal();
510 pr_debug("PowerNV detected !\n");
517 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
518 void __init pnv_tm_init(void)
520 if (!firmware_has_feature(FW_FEATURE_OPAL) ||
521 !pvr_version_is(PVR_POWER9) ||
522 early_cpu_has_feature(CPU_FTR_TM))
525 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
528 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
529 cur_cpu_spec->cpu_features |= CPU_FTR_TM;
530 /* Make sure "normal" HTM is off (it should be) */
531 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
532 /* Turn on no suspend mode, and HTM no SC */
533 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
534 PPC_FEATURE2_HTM_NOSC;
535 tm_suspend_disabled = true;
537 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
540 * Returns the cpu frequency for 'cpu' in Hz. This is used by
543 static unsigned long pnv_get_proc_freq(unsigned int cpu)
545 unsigned long ret_freq;
547 ret_freq = cpufreq_get(cpu) * 1000ul;
550 * If the backend cpufreq driver does not exist,
551 * then fallback to old way of reporting the clockrate.
554 ret_freq = ppc_proc_freq;
558 static long pnv_machine_check_early(struct pt_regs *regs)
562 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
563 handled = cur_cpu_spec->machine_check_early(regs);
568 define_machine(powernv) {
570 .compatible = "ibm,powernv",
572 .setup_arch = pnv_setup_arch,
573 .init_IRQ = pnv_init_IRQ,
574 .show_cpuinfo = pnv_show_cpuinfo,
575 .get_proc_freq = pnv_get_proc_freq,
576 .discover_phbs = pnv_pci_init,
577 .progress = pnv_progress,
578 .machine_shutdown = pnv_shutdown,
580 .machine_check_early = pnv_machine_check_early,
581 #ifdef CONFIG_KEXEC_CORE
582 .kexec_cpu_down = pnv_kexec_cpu_down,
584 #ifdef CONFIG_MEMORY_HOTPLUG
585 .memory_block_size = pnv_memory_block_size,