1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __POWERNV_PCI_H
3 #define __POWERNV_PCI_H
5 #include <linux/iommu.h>
7 #include <asm/msi_bitmap.h>
11 /* Maximum possible number of ATSD MMIO registers per NPU */
12 #define NV_NMMU_ATSD_REGS 8
17 PNV_PHB_NPU_NVLINK = 2,
18 PNV_PHB_NPU_OCAPI = 3,
21 /* Precise PHB model for error management */
23 PNV_PHB_MODEL_UNKNOWN,
30 #define PNV_PCI_DIAG_BUF_SIZE 8192
31 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
32 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
33 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
34 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
35 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
36 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
38 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
39 #define PNV_IODA_STOPPED_STATE 0x8000000000000000
41 /* Data associated with a PE, including IOMMU tracking etc.. */
48 /* A PE can be associated with a single device or an
49 * entire bus (& children). In the former case, pdev
50 * is populated, in the later case, pbus is.
53 struct pci_dev *parent_dev;
58 /* Effective RID (device RID for a device PE and base bus
59 * RID with devfn 0 for a bus PE)
64 unsigned int pe_number;
66 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
67 struct iommu_table_group table_group;
69 /* 64-bit TCE bypass region */
70 bool tce_bypass_enabled;
71 uint64_t tce_bypass_base;
73 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
74 * and -1 if not supported. (It's actually identical to the
79 /* PEs in compound case */
80 struct pnv_ioda_pe *master;
81 struct list_head slaves;
84 int p2p_initiator_count;
86 /* Link in list of PE#s */
87 struct list_head list;
90 #define PNV_PHB_FLAG_EEH (1 << 0)
93 struct pci_controller *hose;
94 enum pnv_phb_type type;
95 enum pnv_phb_model model;
104 #ifdef CONFIG_DEBUG_FS
106 struct dentry *dbgfs;
109 #ifdef CONFIG_PCI_MSI
110 unsigned int msi_base;
111 unsigned int msi32_support;
112 struct msi_bitmap msi_bmp;
114 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
115 unsigned int hwirq, unsigned int virq,
116 unsigned int is_64, struct msi_msg *msg);
117 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
118 void (*fixup_phb)(struct pci_controller *hose);
119 int (*init_m64)(struct pnv_phb *phb);
120 void (*reserve_m64_pe)(struct pci_bus *bus,
121 unsigned long *pe_bitmap, bool all);
122 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
123 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
124 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
125 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
128 /* Global bridge info */
129 unsigned int total_pe_num;
130 unsigned int reserved_pe_idx;
131 unsigned int root_pe_idx;
132 bool root_pe_populated;
134 /* 32-bit MMIO window */
135 unsigned int m32_size;
136 unsigned int m32_segsize;
137 unsigned int m32_pci_base;
139 /* 64-bit MMIO window */
140 unsigned int m64_bar_idx;
141 unsigned long m64_size;
142 unsigned long m64_segsize;
143 unsigned long m64_base;
144 unsigned long m64_bar_alloc;
147 unsigned int io_size;
148 unsigned int io_segsize;
149 unsigned int io_pci_base;
152 struct mutex pe_alloc_mutex;
153 unsigned long *pe_alloc;
154 struct pnv_ioda_pe *pe_array;
156 /* M32 & IO segment maps */
157 unsigned int *m64_segmap;
158 unsigned int *m32_segmap;
159 unsigned int *io_segmap;
161 /* DMA32 segment maps - IODA1 only */
162 unsigned int dma32_count;
163 unsigned int *dma32_segmap;
167 struct irq_chip irq_chip;
169 /* Sorted list of used PE's based
170 * on the sequence of creation
172 struct list_head pe_list;
173 struct mutex pe_list_mutex;
175 /* Reverse map of PEs, indexed by {bus, devfn} */
176 unsigned int pe_rmap[0x10000];
179 /* PHB and hub diagnostics */
180 unsigned int diag_data_size;
186 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
187 unsigned int mmio_atsd_count;
189 /* Bitmask for MMIO register usage */
190 unsigned long mmio_atsd_usage;
192 /* Do we need to explicitly flush the nest mmu? */
196 int p2p_target_count;
199 extern struct pci_ops pnv_pci_ops;
201 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
202 unsigned char *log_buff);
203 int pnv_pci_cfg_read(struct pci_dn *pdn,
204 int where, int size, u32 *val);
205 int pnv_pci_cfg_write(struct pci_dn *pdn,
206 int where, int size, u32 val);
207 extern struct iommu_table *pnv_pci_table_alloc(int nid);
209 extern void pnv_pci_init_ioda_hub(struct device_node *np);
210 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
211 extern void pnv_pci_init_npu_phb(struct device_node *np);
212 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
213 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
214 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
216 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
217 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
218 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
219 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
220 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
221 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
222 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
223 extern int pnv_eeh_post_init(void);
225 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
226 const char *fmt, ...);
227 #define pe_err(pe, fmt, ...) \
228 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
229 #define pe_warn(pe, fmt, ...) \
230 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
231 #define pe_info(pe, fmt, ...) \
232 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
234 /* Nvlink functions */
235 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
236 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
237 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
238 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
239 struct iommu_table *tbl);
240 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
241 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
242 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
243 extern int pnv_npu2_init(struct pnv_phb *phb);
246 #define POWERNV_IOMMU_DEFAULT_LEVELS 2
247 #define POWERNV_IOMMU_MAX_LEVELS 5
249 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
250 unsigned long uaddr, enum dma_data_direction direction,
251 unsigned long attrs);
252 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
253 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
254 unsigned long *hpa, enum dma_data_direction *direction,
256 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
258 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
260 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
261 __u32 page_shift, __u64 window_size, __u32 levels,
262 bool alloc_userspace_copy, struct iommu_table *tbl);
263 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
265 extern long pnv_pci_link_table_and_group(int node, int num,
266 struct iommu_table *tbl,
267 struct iommu_table_group *table_group);
268 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
269 struct iommu_table_group *table_group);
270 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
271 void *tce_mem, u64 tce_size,
272 u64 dma_offset, unsigned int page_shift);
274 #endif /* __POWERNV_PCI_H */