2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/pci.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
22 #include <asm/sections.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/msi_bitmap.h>
28 #include <asm/ppc-pci.h>
29 #include <asm/pnv-pci.h>
31 #include <asm/iommu.h>
33 #include <asm/firmware.h>
34 #include <asm/eeh_event.h>
40 static DEFINE_MUTEX(p2p_mutex);
42 int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id)
44 struct device_node *parent = np;
49 ret = of_property_read_u32(np, "reg", &bdfn);
53 bdfn = ((bdfn & 0x00ffff00) >> 8);
54 while ((parent = of_get_parent(parent))) {
55 if (!PCI_DN(parent)) {
60 if (!of_device_is_compatible(parent, "ibm,ioda2-phb")) {
65 ret = of_property_read_u64(parent, "ibm,opal-phbid", &phbid);
71 *id = PCI_SLOT_ID(phbid, bdfn);
77 EXPORT_SYMBOL_GPL(pnv_pci_get_slot_id);
79 int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len)
83 if (!opal_check_token(OPAL_GET_DEVICE_TREE))
86 rc = opal_get_device_tree(phandle, (uint64_t)buf, len);
87 if (rc < OPAL_SUCCESS)
92 EXPORT_SYMBOL_GPL(pnv_pci_get_device_tree);
94 int pnv_pci_get_presence_state(uint64_t id, uint8_t *state)
98 if (!opal_check_token(OPAL_PCI_GET_PRESENCE_STATE))
101 rc = opal_pci_get_presence_state(id, (uint64_t)state);
102 if (rc != OPAL_SUCCESS)
107 EXPORT_SYMBOL_GPL(pnv_pci_get_presence_state);
109 int pnv_pci_get_power_state(uint64_t id, uint8_t *state)
113 if (!opal_check_token(OPAL_PCI_GET_POWER_STATE))
116 rc = opal_pci_get_power_state(id, (uint64_t)state);
117 if (rc != OPAL_SUCCESS)
122 EXPORT_SYMBOL_GPL(pnv_pci_get_power_state);
124 int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg)
130 if (!opal_check_token(OPAL_PCI_SET_POWER_STATE))
133 token = opal_async_get_token_interruptible();
134 if (unlikely(token < 0))
137 rc = opal_pci_set_power_state(token, id, (uint64_t)&state);
138 if (rc == OPAL_SUCCESS) {
141 } else if (rc != OPAL_ASYNC_COMPLETION) {
146 ret = opal_async_wait_response(token, &m);
152 memcpy(msg, &m, sizeof(m));
156 opal_async_release_token(token);
159 EXPORT_SYMBOL_GPL(pnv_pci_set_power_state);
161 #ifdef CONFIG_PCI_MSI
162 int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
164 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
165 struct pnv_phb *phb = hose->private_data;
166 struct msi_desc *entry;
172 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
175 if (pdev->no_64bit_msi && !phb->msi32_support)
178 for_each_pci_msi_entry(entry, pdev) {
179 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
180 pr_warn("%s: Supports only 64-bit MSIs\n",
184 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
186 pr_warn("%s: Failed to find a free MSI\n",
190 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
192 pr_warn("%s: Failed to map MSI to linux irq\n",
194 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
197 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
198 virq, entry->msi_attrib.is_64, &msg);
200 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
201 irq_dispose_mapping(virq);
202 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
205 irq_set_msi_desc(virq, entry);
206 pci_write_msi_msg(virq, &msg);
211 void pnv_teardown_msi_irqs(struct pci_dev *pdev)
213 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
214 struct pnv_phb *phb = hose->private_data;
215 struct msi_desc *entry;
216 irq_hw_number_t hwirq;
221 for_each_pci_msi_entry(entry, pdev) {
224 hwirq = virq_to_hw(entry->irq);
225 irq_set_msi_desc(entry->irq, NULL);
226 irq_dispose_mapping(entry->irq);
227 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1);
230 #endif /* CONFIG_PCI_MSI */
232 /* Nicely print the contents of the PE State Tables (PEST). */
233 static void pnv_pci_dump_pest(__be64 pestA[], __be64 pestB[], int pest_size)
235 __be64 prevA = ULONG_MAX, prevB = ULONG_MAX;
239 for (i = 0; i < pest_size; i++) {
240 __be64 peA = be64_to_cpu(pestA[i]);
241 __be64 peB = be64_to_cpu(pestB[i]);
243 if (peA != prevA || peB != prevB) {
245 pr_info("PE[..%03x] A/B: as above\n", i-1);
250 if (peA & PNV_IODA_STOPPED_STATE ||
251 peB & PNV_IODA_STOPPED_STATE)
252 pr_info("PE[%03x] A/B: %016llx %016llx\n",
254 } else if (!dup && (peA & PNV_IODA_STOPPED_STATE ||
255 peB & PNV_IODA_STOPPED_STATE)) {
261 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
262 struct OpalIoPhbErrorCommon *common)
264 struct OpalIoP7IOCPhbErrorData *data;
266 data = (struct OpalIoP7IOCPhbErrorData *)common;
267 pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n",
268 hose->global_number, be32_to_cpu(common->version));
271 pr_info("brdgCtl: %08x\n",
272 be32_to_cpu(data->brdgCtl));
273 if (data->portStatusReg || data->rootCmplxStatus ||
274 data->busAgentStatus)
275 pr_info("UtlSts: %08x %08x %08x\n",
276 be32_to_cpu(data->portStatusReg),
277 be32_to_cpu(data->rootCmplxStatus),
278 be32_to_cpu(data->busAgentStatus));
279 if (data->deviceStatus || data->slotStatus ||
280 data->linkStatus || data->devCmdStatus ||
282 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
283 be32_to_cpu(data->deviceStatus),
284 be32_to_cpu(data->slotStatus),
285 be32_to_cpu(data->linkStatus),
286 be32_to_cpu(data->devCmdStatus),
287 be32_to_cpu(data->devSecStatus));
288 if (data->rootErrorStatus || data->uncorrErrorStatus ||
289 data->corrErrorStatus)
290 pr_info("RootErrSts: %08x %08x %08x\n",
291 be32_to_cpu(data->rootErrorStatus),
292 be32_to_cpu(data->uncorrErrorStatus),
293 be32_to_cpu(data->corrErrorStatus));
294 if (data->tlpHdr1 || data->tlpHdr2 ||
295 data->tlpHdr3 || data->tlpHdr4)
296 pr_info("RootErrLog: %08x %08x %08x %08x\n",
297 be32_to_cpu(data->tlpHdr1),
298 be32_to_cpu(data->tlpHdr2),
299 be32_to_cpu(data->tlpHdr3),
300 be32_to_cpu(data->tlpHdr4));
301 if (data->sourceId || data->errorClass ||
303 pr_info("RootErrLog1: %08x %016llx %016llx\n",
304 be32_to_cpu(data->sourceId),
305 be64_to_cpu(data->errorClass),
306 be64_to_cpu(data->correlator));
307 if (data->p7iocPlssr || data->p7iocCsr)
308 pr_info("PhbSts: %016llx %016llx\n",
309 be64_to_cpu(data->p7iocPlssr),
310 be64_to_cpu(data->p7iocCsr));
312 pr_info("Lem: %016llx %016llx %016llx\n",
313 be64_to_cpu(data->lemFir),
314 be64_to_cpu(data->lemErrorMask),
315 be64_to_cpu(data->lemWOF));
316 if (data->phbErrorStatus)
317 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
318 be64_to_cpu(data->phbErrorStatus),
319 be64_to_cpu(data->phbFirstErrorStatus),
320 be64_to_cpu(data->phbErrorLog0),
321 be64_to_cpu(data->phbErrorLog1));
322 if (data->mmioErrorStatus)
323 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
324 be64_to_cpu(data->mmioErrorStatus),
325 be64_to_cpu(data->mmioFirstErrorStatus),
326 be64_to_cpu(data->mmioErrorLog0),
327 be64_to_cpu(data->mmioErrorLog1));
328 if (data->dma0ErrorStatus)
329 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
330 be64_to_cpu(data->dma0ErrorStatus),
331 be64_to_cpu(data->dma0FirstErrorStatus),
332 be64_to_cpu(data->dma0ErrorLog0),
333 be64_to_cpu(data->dma0ErrorLog1));
334 if (data->dma1ErrorStatus)
335 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
336 be64_to_cpu(data->dma1ErrorStatus),
337 be64_to_cpu(data->dma1FirstErrorStatus),
338 be64_to_cpu(data->dma1ErrorLog0),
339 be64_to_cpu(data->dma1ErrorLog1));
341 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_P7IOC_NUM_PEST_REGS);
344 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
345 struct OpalIoPhbErrorCommon *common)
347 struct OpalIoPhb3ErrorData *data;
349 data = (struct OpalIoPhb3ErrorData*)common;
350 pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n",
351 hose->global_number, be32_to_cpu(common->version));
353 pr_info("brdgCtl: %08x\n",
354 be32_to_cpu(data->brdgCtl));
355 if (data->portStatusReg || data->rootCmplxStatus ||
356 data->busAgentStatus)
357 pr_info("UtlSts: %08x %08x %08x\n",
358 be32_to_cpu(data->portStatusReg),
359 be32_to_cpu(data->rootCmplxStatus),
360 be32_to_cpu(data->busAgentStatus));
361 if (data->deviceStatus || data->slotStatus ||
362 data->linkStatus || data->devCmdStatus ||
364 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
365 be32_to_cpu(data->deviceStatus),
366 be32_to_cpu(data->slotStatus),
367 be32_to_cpu(data->linkStatus),
368 be32_to_cpu(data->devCmdStatus),
369 be32_to_cpu(data->devSecStatus));
370 if (data->rootErrorStatus || data->uncorrErrorStatus ||
371 data->corrErrorStatus)
372 pr_info("RootErrSts: %08x %08x %08x\n",
373 be32_to_cpu(data->rootErrorStatus),
374 be32_to_cpu(data->uncorrErrorStatus),
375 be32_to_cpu(data->corrErrorStatus));
376 if (data->tlpHdr1 || data->tlpHdr2 ||
377 data->tlpHdr3 || data->tlpHdr4)
378 pr_info("RootErrLog: %08x %08x %08x %08x\n",
379 be32_to_cpu(data->tlpHdr1),
380 be32_to_cpu(data->tlpHdr2),
381 be32_to_cpu(data->tlpHdr3),
382 be32_to_cpu(data->tlpHdr4));
383 if (data->sourceId || data->errorClass ||
385 pr_info("RootErrLog1: %08x %016llx %016llx\n",
386 be32_to_cpu(data->sourceId),
387 be64_to_cpu(data->errorClass),
388 be64_to_cpu(data->correlator));
390 pr_info("nFir: %016llx %016llx %016llx\n",
391 be64_to_cpu(data->nFir),
392 be64_to_cpu(data->nFirMask),
393 be64_to_cpu(data->nFirWOF));
394 if (data->phbPlssr || data->phbCsr)
395 pr_info("PhbSts: %016llx %016llx\n",
396 be64_to_cpu(data->phbPlssr),
397 be64_to_cpu(data->phbCsr));
399 pr_info("Lem: %016llx %016llx %016llx\n",
400 be64_to_cpu(data->lemFir),
401 be64_to_cpu(data->lemErrorMask),
402 be64_to_cpu(data->lemWOF));
403 if (data->phbErrorStatus)
404 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
405 be64_to_cpu(data->phbErrorStatus),
406 be64_to_cpu(data->phbFirstErrorStatus),
407 be64_to_cpu(data->phbErrorLog0),
408 be64_to_cpu(data->phbErrorLog1));
409 if (data->mmioErrorStatus)
410 pr_info("OutErr: %016llx %016llx %016llx %016llx\n",
411 be64_to_cpu(data->mmioErrorStatus),
412 be64_to_cpu(data->mmioFirstErrorStatus),
413 be64_to_cpu(data->mmioErrorLog0),
414 be64_to_cpu(data->mmioErrorLog1));
415 if (data->dma0ErrorStatus)
416 pr_info("InAErr: %016llx %016llx %016llx %016llx\n",
417 be64_to_cpu(data->dma0ErrorStatus),
418 be64_to_cpu(data->dma0FirstErrorStatus),
419 be64_to_cpu(data->dma0ErrorLog0),
420 be64_to_cpu(data->dma0ErrorLog1));
421 if (data->dma1ErrorStatus)
422 pr_info("InBErr: %016llx %016llx %016llx %016llx\n",
423 be64_to_cpu(data->dma1ErrorStatus),
424 be64_to_cpu(data->dma1FirstErrorStatus),
425 be64_to_cpu(data->dma1ErrorLog0),
426 be64_to_cpu(data->dma1ErrorLog1));
428 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB3_NUM_PEST_REGS);
431 static void pnv_pci_dump_phb4_diag_data(struct pci_controller *hose,
432 struct OpalIoPhbErrorCommon *common)
434 struct OpalIoPhb4ErrorData *data;
436 data = (struct OpalIoPhb4ErrorData*)common;
437 pr_info("PHB4 PHB#%d Diag-data (Version: %d)\n",
438 hose->global_number, be32_to_cpu(common->version));
440 pr_info("brdgCtl: %08x\n",
441 be32_to_cpu(data->brdgCtl));
442 if (data->deviceStatus || data->slotStatus ||
443 data->linkStatus || data->devCmdStatus ||
445 pr_info("RootSts: %08x %08x %08x %08x %08x\n",
446 be32_to_cpu(data->deviceStatus),
447 be32_to_cpu(data->slotStatus),
448 be32_to_cpu(data->linkStatus),
449 be32_to_cpu(data->devCmdStatus),
450 be32_to_cpu(data->devSecStatus));
451 if (data->rootErrorStatus || data->uncorrErrorStatus ||
452 data->corrErrorStatus)
453 pr_info("RootErrSts: %08x %08x %08x\n",
454 be32_to_cpu(data->rootErrorStatus),
455 be32_to_cpu(data->uncorrErrorStatus),
456 be32_to_cpu(data->corrErrorStatus));
457 if (data->tlpHdr1 || data->tlpHdr2 ||
458 data->tlpHdr3 || data->tlpHdr4)
459 pr_info("RootErrLog: %08x %08x %08x %08x\n",
460 be32_to_cpu(data->tlpHdr1),
461 be32_to_cpu(data->tlpHdr2),
462 be32_to_cpu(data->tlpHdr3),
463 be32_to_cpu(data->tlpHdr4));
465 pr_info("sourceId: %08x\n", be32_to_cpu(data->sourceId));
467 pr_info("nFir: %016llx %016llx %016llx\n",
468 be64_to_cpu(data->nFir),
469 be64_to_cpu(data->nFirMask),
470 be64_to_cpu(data->nFirWOF));
471 if (data->phbPlssr || data->phbCsr)
472 pr_info("PhbSts: %016llx %016llx\n",
473 be64_to_cpu(data->phbPlssr),
474 be64_to_cpu(data->phbCsr));
476 pr_info("Lem: %016llx %016llx %016llx\n",
477 be64_to_cpu(data->lemFir),
478 be64_to_cpu(data->lemErrorMask),
479 be64_to_cpu(data->lemWOF));
480 if (data->phbErrorStatus)
481 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n",
482 be64_to_cpu(data->phbErrorStatus),
483 be64_to_cpu(data->phbFirstErrorStatus),
484 be64_to_cpu(data->phbErrorLog0),
485 be64_to_cpu(data->phbErrorLog1));
486 if (data->phbTxeErrorStatus)
487 pr_info("PhbTxeErr: %016llx %016llx %016llx %016llx\n",
488 be64_to_cpu(data->phbTxeErrorStatus),
489 be64_to_cpu(data->phbTxeFirstErrorStatus),
490 be64_to_cpu(data->phbTxeErrorLog0),
491 be64_to_cpu(data->phbTxeErrorLog1));
492 if (data->phbRxeArbErrorStatus)
493 pr_info("RxeArbErr: %016llx %016llx %016llx %016llx\n",
494 be64_to_cpu(data->phbRxeArbErrorStatus),
495 be64_to_cpu(data->phbRxeArbFirstErrorStatus),
496 be64_to_cpu(data->phbRxeArbErrorLog0),
497 be64_to_cpu(data->phbRxeArbErrorLog1));
498 if (data->phbRxeMrgErrorStatus)
499 pr_info("RxeMrgErr: %016llx %016llx %016llx %016llx\n",
500 be64_to_cpu(data->phbRxeMrgErrorStatus),
501 be64_to_cpu(data->phbRxeMrgFirstErrorStatus),
502 be64_to_cpu(data->phbRxeMrgErrorLog0),
503 be64_to_cpu(data->phbRxeMrgErrorLog1));
504 if (data->phbRxeTceErrorStatus)
505 pr_info("RxeTceErr: %016llx %016llx %016llx %016llx\n",
506 be64_to_cpu(data->phbRxeTceErrorStatus),
507 be64_to_cpu(data->phbRxeTceFirstErrorStatus),
508 be64_to_cpu(data->phbRxeTceErrorLog0),
509 be64_to_cpu(data->phbRxeTceErrorLog1));
511 if (data->phbPblErrorStatus)
512 pr_info("PblErr: %016llx %016llx %016llx %016llx\n",
513 be64_to_cpu(data->phbPblErrorStatus),
514 be64_to_cpu(data->phbPblFirstErrorStatus),
515 be64_to_cpu(data->phbPblErrorLog0),
516 be64_to_cpu(data->phbPblErrorLog1));
517 if (data->phbPcieDlpErrorStatus)
518 pr_info("PcieDlp: %016llx %016llx %016llx\n",
519 be64_to_cpu(data->phbPcieDlpErrorLog1),
520 be64_to_cpu(data->phbPcieDlpErrorLog2),
521 be64_to_cpu(data->phbPcieDlpErrorStatus));
522 if (data->phbRegbErrorStatus)
523 pr_info("RegbErr: %016llx %016llx %016llx %016llx\n",
524 be64_to_cpu(data->phbRegbErrorStatus),
525 be64_to_cpu(data->phbRegbFirstErrorStatus),
526 be64_to_cpu(data->phbRegbErrorLog0),
527 be64_to_cpu(data->phbRegbErrorLog1));
530 pnv_pci_dump_pest(data->pestA, data->pestB, OPAL_PHB4_NUM_PEST_REGS);
533 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
534 unsigned char *log_buff)
536 struct OpalIoPhbErrorCommon *common;
538 if (!hose || !log_buff)
541 common = (struct OpalIoPhbErrorCommon *)log_buff;
542 switch (be32_to_cpu(common->ioType)) {
543 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
544 pnv_pci_dump_p7ioc_diag_data(hose, common);
546 case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
547 pnv_pci_dump_phb3_diag_data(hose, common);
549 case OPAL_PHB_ERROR_DATA_TYPE_PHB4:
550 pnv_pci_dump_phb4_diag_data(hose, common);
553 pr_warn("%s: Unrecognized ioType %d\n",
554 __func__, be32_to_cpu(common->ioType));
558 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
560 unsigned long flags, rc;
561 int has_diag, ret = 0;
563 spin_lock_irqsave(&phb->lock, flags);
565 /* Fetch PHB diag-data */
566 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
567 phb->diag_data_size);
568 has_diag = (rc == OPAL_SUCCESS);
570 /* If PHB supports compound PE, to handle it */
571 if (phb->unfreeze_pe) {
572 ret = phb->unfreeze_pe(phb,
574 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
576 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
578 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
580 pr_warn("%s: Failure %ld clearing frozen "
582 __func__, rc, phb->hose->global_number,
589 * For now, let's only display the diag buffer when we fail to clear
590 * the EEH status. We'll do more sensible things later when we have
591 * proper EEH support. We need to make sure we don't pollute ourselves
592 * with the normal errors generated when probing empty slots
595 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
597 spin_unlock_irqrestore(&phb->lock, flags);
600 static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
602 struct pnv_phb *phb = pdn->phb->private_data;
609 * Get the PE#. During the PCI probe stage, we might not
610 * setup that yet. So all ER errors should be mapped to
613 pe_no = pdn->pe_number;
614 if (pe_no == IODA_INVALID_PE) {
615 pe_no = phb->ioda.reserved_pe_idx;
619 * Fetch frozen state. If the PHB support compound PE,
620 * we need handle that case.
622 if (phb->get_pe_state) {
623 fstate = phb->get_pe_state(phb, pe_no);
625 rc = opal_pci_eeh_freeze_status(phb->opal_id,
631 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n",
632 __func__, rc, phb->hose->global_number, pe_no);
637 pr_devel(" -> EEH check, bdfn=%04x PE#%x fstate=%x\n",
638 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
640 /* Clear the frozen state if applicable */
641 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
642 fstate == OPAL_EEH_STOPPED_DMA_FREEZE ||
643 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) {
645 * If PHB supports compound PE, freeze it for
649 phb->freeze_pe(phb, pe_no);
651 pnv_pci_handle_eeh_config(phb, pe_no);
655 int pnv_pci_cfg_read(struct pci_dn *pdn,
656 int where, int size, u32 *val)
658 struct pnv_phb *phb = pdn->phb->private_data;
659 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
665 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
666 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
671 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
673 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
678 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
679 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
683 return PCIBIOS_FUNC_NOT_SUPPORTED;
686 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
687 __func__, pdn->busno, pdn->devfn, where, size, *val);
688 return PCIBIOS_SUCCESSFUL;
691 int pnv_pci_cfg_write(struct pci_dn *pdn,
692 int where, int size, u32 val)
694 struct pnv_phb *phb = pdn->phb->private_data;
695 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
697 pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
698 __func__, pdn->busno, pdn->devfn, where, size, val);
701 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
704 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
707 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
710 return PCIBIOS_FUNC_NOT_SUPPORTED;
713 return PCIBIOS_SUCCESSFUL;
717 static bool pnv_pci_cfg_check(struct pci_dn *pdn)
719 struct eeh_dev *edev = NULL;
720 struct pnv_phb *phb = pdn->phb->private_data;
722 /* EEH not enabled ? */
723 if (!(phb->flags & PNV_PHB_FLAG_EEH))
726 /* PE reset or device removed ? */
730 (edev->pe->state & EEH_PE_CFG_BLOCKED))
733 if (edev->mode & EEH_DEV_REMOVED)
740 static inline pnv_pci_cfg_check(struct pci_dn *pdn)
744 #endif /* CONFIG_EEH */
746 static int pnv_pci_read_config(struct pci_bus *bus,
748 int where, int size, u32 *val)
755 pdn = pci_get_pdn_by_devfn(bus, devfn);
757 return PCIBIOS_DEVICE_NOT_FOUND;
759 if (!pnv_pci_cfg_check(pdn))
760 return PCIBIOS_DEVICE_NOT_FOUND;
762 ret = pnv_pci_cfg_read(pdn, where, size, val);
763 phb = pdn->phb->private_data;
764 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) {
765 if (*val == EEH_IO_ERROR_VALUE(size) &&
766 eeh_dev_check_failure(pdn->edev))
767 return PCIBIOS_DEVICE_NOT_FOUND;
769 pnv_pci_config_check_eeh(pdn);
775 static int pnv_pci_write_config(struct pci_bus *bus,
777 int where, int size, u32 val)
783 pdn = pci_get_pdn_by_devfn(bus, devfn);
785 return PCIBIOS_DEVICE_NOT_FOUND;
787 if (!pnv_pci_cfg_check(pdn))
788 return PCIBIOS_DEVICE_NOT_FOUND;
790 ret = pnv_pci_cfg_write(pdn, where, size, val);
791 phb = pdn->phb->private_data;
792 if (!(phb->flags & PNV_PHB_FLAG_EEH))
793 pnv_pci_config_check_eeh(pdn);
798 struct pci_ops pnv_pci_ops = {
799 .read = pnv_pci_read_config,
800 .write = pnv_pci_write_config,
803 static __be64 *pnv_tce(struct iommu_table *tbl, long idx)
805 __be64 *tmp = ((__be64 *)tbl->it_base);
806 int level = tbl->it_indirect_levels;
807 const long shift = ilog2(tbl->it_level_size);
808 unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
811 int n = (idx & mask) >> (level * shift);
812 unsigned long tce = be64_to_cpu(tmp[n]);
814 tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
823 int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
824 unsigned long uaddr, enum dma_data_direction direction,
827 u64 proto_tce = iommu_direction_to_tce_perm(direction);
828 u64 rpn = __pa(uaddr) >> tbl->it_page_shift;
831 if (proto_tce & TCE_PCI_WRITE)
832 proto_tce |= TCE_PCI_READ;
834 for (i = 0; i < npages; i++) {
835 unsigned long newtce = proto_tce |
836 ((rpn + i) << tbl->it_page_shift);
837 unsigned long idx = index - tbl->it_offset + i;
839 *(pnv_tce(tbl, idx)) = cpu_to_be64(newtce);
845 #ifdef CONFIG_IOMMU_API
846 int pnv_tce_xchg(struct iommu_table *tbl, long index,
847 unsigned long *hpa, enum dma_data_direction *direction)
849 u64 proto_tce = iommu_direction_to_tce_perm(*direction);
850 unsigned long newtce = *hpa | proto_tce, oldtce;
851 unsigned long idx = index - tbl->it_offset;
853 BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));
855 if (newtce & TCE_PCI_WRITE)
856 newtce |= TCE_PCI_READ;
858 oldtce = be64_to_cpu(xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce)));
859 *hpa = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
860 *direction = iommu_tce_direction(oldtce);
866 void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
870 for (i = 0; i < npages; i++) {
871 unsigned long idx = index - tbl->it_offset + i;
873 *(pnv_tce(tbl, idx)) = cpu_to_be64(0);
877 unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
879 return be64_to_cpu(*(pnv_tce(tbl, index - tbl->it_offset)));
882 struct iommu_table *pnv_pci_table_alloc(int nid)
884 struct iommu_table *tbl;
886 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid);
890 INIT_LIST_HEAD_RCU(&tbl->it_group_list);
891 kref_init(&tbl->it_kref);
896 long pnv_pci_link_table_and_group(int node, int num,
897 struct iommu_table *tbl,
898 struct iommu_table_group *table_group)
900 struct iommu_table_group_link *tgl = NULL;
902 if (WARN_ON(!tbl || !table_group))
905 tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL,
910 tgl->table_group = table_group;
911 list_add_rcu(&tgl->next, &tbl->it_group_list);
913 table_group->tables[num] = tbl;
918 static void pnv_iommu_table_group_link_free(struct rcu_head *head)
920 struct iommu_table_group_link *tgl = container_of(head,
921 struct iommu_table_group_link, rcu);
926 void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
927 struct iommu_table_group *table_group)
931 struct iommu_table_group_link *tgl;
933 if (!tbl || !table_group)
936 /* Remove link to a group from table's list of attached groups */
938 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
939 if (tgl->table_group == table_group) {
940 list_del_rcu(&tgl->next);
941 call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free);
949 /* Clean a pointer to iommu_table in iommu_table_group::tables[] */
951 for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
952 if (table_group->tables[i] == tbl) {
953 table_group->tables[i] = NULL;
961 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
962 void *tce_mem, u64 tce_size,
963 u64 dma_offset, unsigned page_shift)
965 tbl->it_blocksize = 16;
966 tbl->it_base = (unsigned long)tce_mem;
967 tbl->it_page_shift = page_shift;
968 tbl->it_offset = dma_offset >> tbl->it_page_shift;
970 tbl->it_size = tce_size >> 3;
972 tbl->it_type = TCE_PCI;
975 void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
977 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
978 struct pnv_phb *phb = hose->private_data;
979 #ifdef CONFIG_PCI_IOV
980 struct pnv_ioda_pe *pe;
982 /* Fix the VF pdn PE number */
983 if (pdev->is_virtfn) {
984 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
985 if (pe->rid == ((pdev->bus->number << 8) |
986 (pdev->devfn & 0xff))) {
992 #endif /* CONFIG_PCI_IOV */
994 if (phb && phb->dma_dev_setup)
995 phb->dma_dev_setup(phb, pdev);
998 void pnv_pci_dma_bus_setup(struct pci_bus *bus)
1000 struct pci_controller *hose = bus->sysdata;
1001 struct pnv_phb *phb = hose->private_data;
1002 struct pnv_ioda_pe *pe;
1004 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
1005 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
1011 if (bus->number == ((pe->rid >> 8) & 0xFF)) {
1018 int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target, u64 desc)
1020 struct pci_controller *hose;
1021 struct pnv_phb *phb_init, *phb_target;
1022 struct pnv_ioda_pe *pe_init;
1025 if (!opal_check_token(OPAL_PCI_SET_P2P))
1028 hose = pci_bus_to_host(initiator->bus);
1029 phb_init = hose->private_data;
1031 hose = pci_bus_to_host(target->bus);
1032 phb_target = hose->private_data;
1034 pe_init = pnv_ioda_get_pe(initiator);
1039 * Configuring the initiator's PHB requires to adjust its
1040 * TVE#1 setting. Since the same device can be an initiator
1041 * several times for different target devices, we need to keep
1042 * a reference count to know when we can restore the default
1043 * bypass setting on its TVE#1 when disabling. Opal is not
1044 * tracking PE states, so we add a reference count on the PE
1047 * For the target, the configuration is per PHB, so we keep a
1048 * target reference count on the PHB.
1050 mutex_lock(&p2p_mutex);
1052 if (desc & OPAL_PCI_P2P_ENABLE) {
1053 /* always go to opal to validate the configuration */
1054 rc = opal_pci_set_p2p(phb_init->opal_id, phb_target->opal_id,
1055 desc, pe_init->pe_number);
1057 if (rc != OPAL_SUCCESS) {
1062 pe_init->p2p_initiator_count++;
1063 phb_target->p2p_target_count++;
1065 if (!pe_init->p2p_initiator_count ||
1066 !phb_target->p2p_target_count) {
1071 if (--pe_init->p2p_initiator_count == 0)
1072 pnv_pci_ioda2_set_bypass(pe_init, true);
1074 if (--phb_target->p2p_target_count == 0) {
1075 rc = opal_pci_set_p2p(phb_init->opal_id,
1076 phb_target->opal_id, desc,
1077 pe_init->pe_number);
1078 if (rc != OPAL_SUCCESS) {
1086 mutex_unlock(&p2p_mutex);
1089 EXPORT_SYMBOL_GPL(pnv_pci_set_p2p);
1091 void pnv_pci_shutdown(void)
1093 struct pci_controller *hose;
1095 list_for_each_entry(hose, &hose_list, list_node)
1096 if (hose->controller_ops.shutdown)
1097 hose->controller_ops.shutdown(hose);
1100 /* Fixup wrong class code in p7ioc and p8 root complex */
1101 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
1103 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
1105 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
1107 void __init pnv_pci_init(void)
1109 struct device_node *np;
1111 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
1113 /* If we don't have OPAL, eg. in sim, just skip PCI probe */
1114 if (!firmware_has_feature(FW_FEATURE_OPAL))
1117 #ifdef CONFIG_PCIEPORTBUS
1119 * On PowerNV PCIe devices are (currently) managed in cooperation
1120 * with firmware. This isn't *strictly* required, but there's enough
1121 * assumptions baked into both firmware and the platform code that
1122 * it's unwise to allow the portbus services to be used.
1124 * We need to fix this eventually, but for now set this flag to disable
1125 * the portbus driver. The AER service isn't required since that AER
1126 * events are handled via EEH. The pciehp hotplug driver can't work
1127 * without kernel changes (and portbus binding breaks pnv_php). The
1128 * other services also require some thinking about how we're going
1129 * to integrate them.
1131 pcie_ports_disabled = true;
1134 /* Look for IODA IO-Hubs. */
1135 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
1136 pnv_pci_init_ioda_hub(np);
1139 /* Look for ioda2 built-in PHB3's */
1140 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
1141 pnv_pci_init_ioda2_phb(np);
1143 /* Look for ioda3 built-in PHB4's, we treat them as IODA2 */
1144 for_each_compatible_node(np, NULL, "ibm,ioda3-phb")
1145 pnv_pci_init_ioda2_phb(np);
1147 /* Look for NPU PHBs */
1148 for_each_compatible_node(np, NULL, "ibm,ioda2-npu-phb")
1149 pnv_pci_init_npu_phb(np);
1152 * Look for NPU2 PHBs which we treat mostly as NPU PHBs with
1153 * the exception of TCE kill which requires an OPAL call.
1155 for_each_compatible_node(np, NULL, "ibm,ioda2-npu2-phb")
1156 pnv_pci_init_npu_phb(np);
1158 /* Configure IOMMU DMA hooks */
1159 set_pci_dma_ops(&dma_iommu_ops);
1162 machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init);