arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24 #include <linux/memblock.h>
  25 #include <linux/iommu.h>
  26 #include <linux/rculist.h>
  27 #include <linux/sizes.h>
  28
  29 #include <asm/sections.h>
  30 #include <asm/io.h>
  31 #include <asm/prom.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/machdep.h>
  34 #include <asm/msi_bitmap.h>
  35 #include <asm/ppc-pci.h>
  36 #include <asm/opal.h>
  37 #include <asm/iommu.h>
  38 #include <asm/tce.h>
  39 #include <asm/xics.h>
  40 #include <asm/debugfs.h>
  41 #include <asm/firmware.h>
  42 #include <asm/pnv-pci.h>
  43 #include <asm/mmzone.h>
  44
  45 #include <misc/cxl-base.h>
  46
  47 #include "powernv.h"
  48 #include "pci.h"
  49 #include "../../../../drivers/pci/pci.h"
  50
  51 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  52 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  54
  55 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
  56                                               "NPU_OCAPI" };
  57
  58 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  59                             const char *fmt, ...)
  60 {
  61         struct va_format vaf;
  62         va_list args;
  63         char pfix[32];
  64
  65         va_start(args, fmt);
  66
  67         vaf.fmt = fmt;
  68         vaf.va = &args;
  69
  70         if (pe->flags & PNV_IODA_PE_DEV)
  71                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  72         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  73                 sprintf(pfix, "%04x:%02x     ",
  74                         pci_domain_nr(pe->pbus), pe->pbus->number);
  75 #ifdef CONFIG_PCI_IOV
  76         else if (pe->flags & PNV_IODA_PE_VF)
  77                 sprintf(pfix, "%04x:%02x:%2x.%d",
  78                         pci_domain_nr(pe->parent_dev->bus),
  79                         (pe->rid & 0xff00) >> 8,
  80                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  81 #endif /* CONFIG_PCI_IOV*/
  82
  83         printk("%spci %s: [PE# %.2x] %pV",
  84                level, pfix, pe->pe_number, &vaf);
  85
  86         va_end(args);
  87 }
  88
  89 static bool pnv_iommu_bypass_disabled __read_mostly;
  90 static bool pci_reset_phbs __read_mostly;
  91
  92 static int __init iommu_setup(char *str)
  93 {
  94         if (!str)
  95                 return -EINVAL;
  96
  97         while (*str) {
  98                 if (!strncmp(str, "nobypass", 8)) {
  99                         pnv_iommu_bypass_disabled = true;
 100                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 101                         break;
 102                 }
 103                 str += strcspn(str, ",");
 104                 if (*str == ',')
 105                         str++;
 106         }
 107
 108         return 0;
 109 }
 110 early_param("iommu", iommu_setup);
 111
 112 static int __init pci_reset_phbs_setup(char *str)
 113 {
 114         pci_reset_phbs = true;
 115         return 0;
 116 }
 117
 118 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
 119
 120 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 121 {
 122         /*
 123          * WARNING: We cannot rely on the resource flags. The Linux PCI
 124          * allocation code sometimes decides to put a 64-bit prefetchable
 125          * BAR in the 32-bit window, so we have to compare the addresses.
 126          *
 127          * For simplicity we only test resource start.
 128          */
 129         return (r->start >= phb->ioda.m64_base &&
 130                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 131 }
 132
 133 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 134 {
 135         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 136
 137         return (resource_flags & flags) == flags;
 138 }
 139
 140 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 141 {
 142         s64 rc;
 143
 144         phb->ioda.pe_array[pe_no].phb = phb;
 145         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 146
 147         /*
 148          * Clear the PE frozen state as it might be put into frozen state
 149          * in the last PCI remove path. It's not harmful to do so when the
 150          * PE is already in unfrozen state.
 151          */
 152         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 153                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 154         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 155                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 156                         __func__, rc, phb->hose->global_number, pe_no);
 157
 158         return &phb->ioda.pe_array[pe_no];
 159 }
 160
 161 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 162 {
 163         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 164                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 165                         __func__, pe_no, phb->hose->global_number);
 166                 return;
 167         }
 168
 169         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 170                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 171                          __func__, pe_no, phb->hose->global_number);
 172
 173         pnv_ioda_init_pe(phb, pe_no);
 174 }
 175
 176 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 177 {
 178         long pe;
 179
 180         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 181                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 182                         return pnv_ioda_init_pe(phb, pe);
 183         }
 184
 185         return NULL;
 186 }
 187
 188 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 189 {
 190         struct pnv_phb *phb = pe->phb;
 191         unsigned int pe_num = pe->pe_number;
 192
 193         WARN_ON(pe->pdev);
 194
 195         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 196         clear_bit(pe_num, phb->ioda.pe_alloc);
 197 }
 198
 199 /* The default M64 BAR is shared by all PEs */
 200 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 201 {
 202         const char *desc;
 203         struct resource *r;
 204         s64 rc;
 205
 206         /* Configure the default M64 BAR */
 207         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 208                                          OPAL_M64_WINDOW_TYPE,
 209                                          phb->ioda.m64_bar_idx,
 210                                          phb->ioda.m64_base,
 211                                          0, /* unused */
 212                                          phb->ioda.m64_size);
 213         if (rc != OPAL_SUCCESS) {
 214                 desc = "configuring";
 215                 goto fail;
 216         }
 217
 218         /* Enable the default M64 BAR */
 219         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 220                                       OPAL_M64_WINDOW_TYPE,
 221                                       phb->ioda.m64_bar_idx,
 222                                       OPAL_ENABLE_M64_SPLIT);
 223         if (rc != OPAL_SUCCESS) {
 224                 desc = "enabling";
 225                 goto fail;
 226         }
 227
 228         /*
 229          * Exclude the segments for reserved and root bus PE, which
 230          * are first or last two PEs.
 231          */
 232         r = &phb->hose->mem_resources[1];
 233         if (phb->ioda.reserved_pe_idx == 0)
 234                 r->start += (2 * phb->ioda.m64_segsize);
 235         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 236                 r->end -= (2 * phb->ioda.m64_segsize);
 237         else
 238                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 239                         phb->ioda.reserved_pe_idx);
 240
 241         return 0;
 242
 243 fail:
 244         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 245                 rc, desc, phb->ioda.m64_bar_idx);
 246         opal_pci_phb_mmio_enable(phb->opal_id,
 247                                  OPAL_M64_WINDOW_TYPE,
 248                                  phb->ioda.m64_bar_idx,
 249                                  OPAL_DISABLE_M64);
 250         return -EIO;
 251 }
 252
 253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 254                                          unsigned long *pe_bitmap)
 255 {
 256         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 257         struct pnv_phb *phb = hose->private_data;
 258         struct resource *r;
 259         resource_size_t base, sgsz, start, end;
 260         int segno, i;
 261
 262         base = phb->ioda.m64_base;
 263         sgsz = phb->ioda.m64_segsize;
 264         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 265                 r = &pdev->resource[i];
 266                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 267                         continue;
 268
 269                 start = _ALIGN_DOWN(r->start - base, sgsz);
 270                 end = _ALIGN_UP(r->end - base, sgsz);
 271                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 272                         if (pe_bitmap)
 273                                 set_bit(segno, pe_bitmap);
 274                         else
 275                                 pnv_ioda_reserve_pe(phb, segno);
 276                 }
 277         }
 278 }
 279
 280 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 281 {
 282         struct resource *r;
 283         int index;
 284
 285         /*
 286          * There are 16 M64 BARs, each of which has 8 segments. So
 287          * there are as many M64 segments as the maximum number of
 288          * PEs, which is 128.
 289          */
 290         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 291                 unsigned long base, segsz = phb->ioda.m64_segsize;
 292                 int64_t rc;
 293
 294                 base = phb->ioda.m64_base +
 295                        index * PNV_IODA1_M64_SEGS * segsz;
 296                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 297                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 298                                 PNV_IODA1_M64_SEGS * segsz);
 299                 if (rc != OPAL_SUCCESS) {
 300                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 301                                 rc, phb->hose->global_number, index);
 302                         goto fail;
 303                 }
 304
 305                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 306                                 OPAL_M64_WINDOW_TYPE, index,
 307                                 OPAL_ENABLE_M64_SPLIT);
 308                 if (rc != OPAL_SUCCESS) {
 309                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 310                                 rc, phb->hose->global_number, index);
 311                         goto fail;
 312                 }
 313         }
 314
 315         /*
 316          * Exclude the segments for reserved and root bus PE, which
 317          * are first or last two PEs.
 318          */
 319         r = &phb->hose->mem_resources[1];
 320         if (phb->ioda.reserved_pe_idx == 0)
 321                 r->start += (2 * phb->ioda.m64_segsize);
 322         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 323                 r->end -= (2 * phb->ioda.m64_segsize);
 324         else
 325                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 326                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 327
 328         return 0;
 329
 330 fail:
 331         for ( ; index >= 0; index--)
 332                 opal_pci_phb_mmio_enable(phb->opal_id,
 333                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 334
 335         return -EIO;
 336 }
 337
 338 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 339                                     unsigned long *pe_bitmap,
 340                                     bool all)
 341 {
 342         struct pci_dev *pdev;
 343
 344         list_for_each_entry(pdev, &bus->devices, bus_list) {
 345                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 346
 347                 if (all && pdev->subordinate)
 348                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 349                                                 pe_bitmap, all);
 350         }
 351 }
 352
 353 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 354 {
 355         struct pci_controller *hose = pci_bus_to_host(bus);
 356         struct pnv_phb *phb = hose->private_data;
 357         struct pnv_ioda_pe *master_pe, *pe;
 358         unsigned long size, *pe_alloc;
 359         int i;
 360
 361         /* Root bus shouldn't use M64 */
 362         if (pci_is_root_bus(bus))
 363                 return NULL;
 364
 365         /* Allocate bitmap */
 366         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 367         pe_alloc = kzalloc(size, GFP_KERNEL);
 368         if (!pe_alloc) {
 369                 pr_warn("%s: Out of memory !\n",
 370                         __func__);
 371                 return NULL;
 372         }
 373
 374         /* Figure out reserved PE numbers by the PE */
 375         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 376
 377         /*
 378          * the current bus might not own M64 window and that's all
 379          * contributed by its child buses. For the case, we needn't
 380          * pick M64 dependent PE#.
 381          */
 382         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 383                 kfree(pe_alloc);
 384                 return NULL;
 385         }
 386
 387         /*
 388          * Figure out the master PE and put all slave PEs to master
 389          * PE's list to form compound PE.
 390          */
 391         master_pe = NULL;
 392         i = -1;
 393         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 394                 phb->ioda.total_pe_num) {
 395                 pe = &phb->ioda.pe_array[i];
 396
 397                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 398                 if (!master_pe) {
 399                         pe->flags |= PNV_IODA_PE_MASTER;
 400                         INIT_LIST_HEAD(&pe->slaves);
 401                         master_pe = pe;
 402                 } else {
 403                         pe->flags |= PNV_IODA_PE_SLAVE;
 404                         pe->master = master_pe;
 405                         list_add_tail(&pe->list, &master_pe->slaves);
 406                 }
 407
 408                 /*
 409                  * P7IOC supports M64DT, which helps mapping M64 segment
 410                  * to one particular PE#. However, PHB3 has fixed mapping
 411                  * between M64 segment and PE#. In order to have same logic
 412                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 413                  * segment and PE# on P7IOC.
 414                  */
 415                 if (phb->type == PNV_PHB_IODA1) {
 416                         int64_t rc;
 417
 418                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 419                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 420                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 421                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 422                         if (rc != OPAL_SUCCESS)
 423                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 424                                         __func__, rc, phb->hose->global_number,
 425                                         pe->pe_number);
 426                 }
 427         }
 428
 429         kfree(pe_alloc);
 430         return master_pe;
 431 }
 432
 433 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 434 {
 435         struct pci_controller *hose = phb->hose;
 436         struct device_node *dn = hose->dn;
 437         struct resource *res;
 438         u32 m64_range[2], i;
 439         const __be32 *r;
 440         u64 pci_addr;
 441
 442         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 443                 pr_info("  Not support M64 window\n");
 444                 return;
 445         }
 446
 447         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 448                 pr_info("  Firmware too old to support M64 window\n");
 449                 return;
 450         }
 451
 452         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 453         if (!r) {
 454                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 455                         dn);
 456                 return;
 457         }
 458
 459         /*
 460          * Find the available M64 BAR range and pickup the last one for
 461          * covering the whole 64-bits space. We support only one range.
 462          */
 463         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 464                                        m64_range, 2)) {
 465                 /* In absence of the property, assume 0..15 */
 466                 m64_range[0] = 0;
 467                 m64_range[1] = 16;
 468         }
 469         /* We only support 64 bits in our allocator */
 470         if (m64_range[1] > 63) {
 471                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 472                         __func__, m64_range[1], phb->hose->global_number);
 473                 m64_range[1] = 63;
 474         }
 475         /* Empty range, no m64 */
 476         if (m64_range[1] <= m64_range[0]) {
 477                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 478                         __func__, phb->hose->global_number);
 479                 return;
 480         }
 481
 482         /* Configure M64 informations */
 483         res = &hose->mem_resources[1];
 484         res->name = dn->full_name;
 485         res->start = of_translate_address(dn, r + 2);
 486         res->end = res->start + of_read_number(r + 4, 2) - 1;
 487         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 488         pci_addr = of_read_number(r, 2);
 489         hose->mem_offset[1] = res->start - pci_addr;
 490
 491         phb->ioda.m64_size = resource_size(res);
 492         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 493         phb->ioda.m64_base = pci_addr;
 494
 495         /* This lines up nicely with the display from processing OF ranges */
 496         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 497                 res->start, res->end, pci_addr, m64_range[0],
 498                 m64_range[0] + m64_range[1] - 1);
 499
 500         /* Mark all M64 used up by default */
 501         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 502
 503         /* Use last M64 BAR to cover M64 window */
 504         m64_range[1]--;
 505         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 506
 507         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 508
 509         /* Mark remaining ones free */
 510         for (i = m64_range[0]; i < m64_range[1]; i++)
 511                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 512
 513         /*
 514          * Setup init functions for M64 based on IODA version, IODA3 uses
 515          * the IODA2 code.
 516          */
 517         if (phb->type == PNV_PHB_IODA1)
 518                 phb->init_m64 = pnv_ioda1_init_m64;
 519         else
 520                 phb->init_m64 = pnv_ioda2_init_m64;
 521         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 522         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 523 }
 524
 525 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 526 {
 527         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 528         struct pnv_ioda_pe *slave;
 529         s64 rc;
 530
 531         /* Fetch master PE */
 532         if (pe->flags & PNV_IODA_PE_SLAVE) {
 533                 pe = pe->master;
 534                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 535                         return;
 536
 537                 pe_no = pe->pe_number;
 538         }
 539
 540         /* Freeze master PE */
 541         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 542                                      pe_no,
 543                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 544         if (rc != OPAL_SUCCESS) {
 545                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 546                         __func__, rc, phb->hose->global_number, pe_no);
 547                 return;
 548         }
 549
 550         /* Freeze slave PEs */
 551         if (!(pe->flags & PNV_IODA_PE_MASTER))
 552                 return;
 553
 554         list_for_each_entry(slave, &pe->slaves, list) {
 555                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 556                                              slave->pe_number,
 557                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 558                 if (rc != OPAL_SUCCESS)
 559                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 560                                 __func__, rc, phb->hose->global_number,
 561                                 slave->pe_number);
 562         }
 563 }
 564
 565 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 566 {
 567         struct pnv_ioda_pe *pe, *slave;
 568         s64 rc;
 569
 570         /* Find master PE */
 571         pe = &phb->ioda.pe_array[pe_no];
 572         if (pe->flags & PNV_IODA_PE_SLAVE) {
 573                 pe = pe->master;
 574                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 575                 pe_no = pe->pe_number;
 576         }
 577
 578         /* Clear frozen state for master PE */
 579         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 580         if (rc != OPAL_SUCCESS) {
 581                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 582                         __func__, rc, opt, phb->hose->global_number, pe_no);
 583                 return -EIO;
 584         }
 585
 586         if (!(pe->flags & PNV_IODA_PE_MASTER))
 587                 return 0;
 588
 589         /* Clear frozen state for slave PEs */
 590         list_for_each_entry(slave, &pe->slaves, list) {
 591                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 592                                              slave->pe_number,
 593                                              opt);
 594                 if (rc != OPAL_SUCCESS) {
 595                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 596                                 __func__, rc, opt, phb->hose->global_number,
 597                                 slave->pe_number);
 598                         return -EIO;
 599                 }
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 606 {
 607         struct pnv_ioda_pe *slave, *pe;
 608         u8 fstate = 0, state;
 609         __be16 pcierr = 0;
 610         s64 rc;
 611
 612         /* Sanity check on PE number */
 613         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 614                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 615
 616         /*
 617          * Fetch the master PE and the PE instance might be
 618          * not initialized yet.
 619          */
 620         pe = &phb->ioda.pe_array[pe_no];
 621         if (pe->flags & PNV_IODA_PE_SLAVE) {
 622                 pe = pe->master;
 623                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 624                 pe_no = pe->pe_number;
 625         }
 626
 627         /* Check the master PE */
 628         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 629                                         &state, &pcierr, NULL);
 630         if (rc != OPAL_SUCCESS) {
 631                 pr_warn("%s: Failure %lld getting "
 632                         "PHB#%x-PE#%x state\n",
 633                         __func__, rc,
 634                         phb->hose->global_number, pe_no);
 635                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 636         }
 637
 638         /* Check the slave PE */
 639         if (!(pe->flags & PNV_IODA_PE_MASTER))
 640                 return state;
 641
 642         list_for_each_entry(slave, &pe->slaves, list) {
 643                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 644                                                 slave->pe_number,
 645                                                 &fstate,
 646                                                 &pcierr,
 647                                                 NULL);
 648                 if (rc != OPAL_SUCCESS) {
 649                         pr_warn("%s: Failure %lld getting "
 650                                 "PHB#%x-PE#%x state\n",
 651                                 __func__, rc,
 652                                 phb->hose->global_number, slave->pe_number);
 653                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 654                 }
 655
 656                 /*
 657                  * Override the result based on the ascending
 658                  * priority.
 659                  */
 660                 if (fstate > state)
 661                         state = fstate;
 662         }
 663
 664         return state;
 665 }
 666
 667 /* Currently those 2 are only used when MSIs are enabled, this will change
 668  * but in the meantime, we need to protect them to avoid warnings
 669  */
 670 #ifdef CONFIG_PCI_MSI
 671 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 672 {
 673         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 674         struct pnv_phb *phb = hose->private_data;
 675         struct pci_dn *pdn = pci_get_pdn(dev);
 676
 677         if (!pdn)
 678                 return NULL;
 679         if (pdn->pe_number == IODA_INVALID_PE)
 680                 return NULL;
 681         return &phb->ioda.pe_array[pdn->pe_number];
 682 }
 683 #endif /* CONFIG_PCI_MSI */
 684
 685 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 686                                   struct pnv_ioda_pe *parent,
 687                                   struct pnv_ioda_pe *child,
 688                                   bool is_add)
 689 {
 690         const char *desc = is_add ? "adding" : "removing";
 691         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 692                               OPAL_REMOVE_PE_FROM_DOMAIN;
 693         struct pnv_ioda_pe *slave;
 694         long rc;
 695
 696         /* Parent PE affects child PE */
 697         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 698                                 child->pe_number, op);
 699         if (rc != OPAL_SUCCESS) {
 700                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 701                         rc, desc);
 702                 return -ENXIO;
 703         }
 704
 705         if (!(child->flags & PNV_IODA_PE_MASTER))
 706                 return 0;
 707
 708         /* Compound case: parent PE affects slave PEs */
 709         list_for_each_entry(slave, &child->slaves, list) {
 710                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 711                                         slave->pe_number, op);
 712                 if (rc != OPAL_SUCCESS) {
 713                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 714                                 rc, desc);
 715                         return -ENXIO;
 716                 }
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 723                               struct pnv_ioda_pe *pe,
 724                               bool is_add)
 725 {
 726         struct pnv_ioda_pe *slave;
 727         struct pci_dev *pdev = NULL;
 728         int ret;
 729
 730         /*
 731          * Clear PE frozen state. If it's master PE, we need
 732          * clear slave PE frozen state as well.
 733          */
 734         if (is_add) {
 735                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 736                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 737                 if (pe->flags & PNV_IODA_PE_MASTER) {
 738                         list_for_each_entry(slave, &pe->slaves, list)
 739                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 740                                                           slave->pe_number,
 741                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 742                 }
 743         }
 744
 745         /*
 746          * Associate PE in PELT. We need add the PE into the
 747          * corresponding PELT-V as well. Otherwise, the error
 748          * originated from the PE might contribute to other
 749          * PEs.
 750          */
 751         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 752         if (ret)
 753                 return ret;
 754
 755         /* For compound PEs, any one affects all of them */
 756         if (pe->flags & PNV_IODA_PE_MASTER) {
 757                 list_for_each_entry(slave, &pe->slaves, list) {
 758                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 759                         if (ret)
 760                                 return ret;
 761                 }
 762         }
 763
 764         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 765                 pdev = pe->pbus->self;
 766         else if (pe->flags & PNV_IODA_PE_DEV)
 767                 pdev = pe->pdev->bus->self;
 768 #ifdef CONFIG_PCI_IOV
 769         else if (pe->flags & PNV_IODA_PE_VF)
 770                 pdev = pe->parent_dev;
 771 #endif /* CONFIG_PCI_IOV */
 772         while (pdev) {
 773                 struct pci_dn *pdn = pci_get_pdn(pdev);
 774                 struct pnv_ioda_pe *parent;
 775
 776                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 777                         parent = &phb->ioda.pe_array[pdn->pe_number];
 778                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 779                         if (ret)
 780                                 return ret;
 781                 }
 782
 783                 pdev = pdev->bus->self;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 790 {
 791         struct pci_dev *parent;
 792         uint8_t bcomp, dcomp, fcomp;
 793         int64_t rc;
 794         long rid_end, rid;
 795
 796         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 797         if (pe->pbus) {
 798                 int count;
 799
 800                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 801                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 802                 parent = pe->pbus->self;
 803                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 804                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 805                 else
 806                         count = 1;
 807
 808                 switch(count) {
 809                 case  1: bcomp = OpalPciBusAll;         break;
 810                 case  2: bcomp = OpalPciBus7Bits;       break;
 811                 case  4: bcomp = OpalPciBus6Bits;       break;
 812                 case  8: bcomp = OpalPciBus5Bits;       break;
 813                 case 16: bcomp = OpalPciBus4Bits;       break;
 814                 case 32: bcomp = OpalPciBus3Bits;       break;
 815                 default:
 816                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 817                                 count);
 818                         /* Do an exact match only */
 819                         bcomp = OpalPciBusAll;
 820                 }
 821                 rid_end = pe->rid + (count << 8);
 822         } else {
 823 #ifdef CONFIG_PCI_IOV
 824                 if (pe->flags & PNV_IODA_PE_VF)
 825                         parent = pe->parent_dev;
 826                 else
 827 #endif
 828                         parent = pe->pdev->bus->self;
 829                 bcomp = OpalPciBusAll;
 830                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 831                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 832                 rid_end = pe->rid + 1;
 833         }
 834
 835         /* Clear the reverse map */
 836         for (rid = pe->rid; rid < rid_end; rid++)
 837                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 838
 839         /* Release from all parents PELT-V */
 840         while (parent) {
 841                 struct pci_dn *pdn = pci_get_pdn(parent);
 842                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 843                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 844                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 845                         /* XXX What to do in case of error ? */
 846                 }
 847                 parent = parent->bus->self;
 848         }
 849
 850         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 851                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 852
 853         /* Disassociate PE in PELT */
 854         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 855                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 856         if (rc)
 857                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 858         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 859                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 860         if (rc)
 861                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 862
 863         pe->pbus = NULL;
 864         pe->pdev = NULL;
 865 #ifdef CONFIG_PCI_IOV
 866         pe->parent_dev = NULL;
 867 #endif
 868
 869         return 0;
 870 }
 871
 872 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 873 {
 874         struct pci_dev *parent;
 875         uint8_t bcomp, dcomp, fcomp;
 876         long rc, rid_end, rid;
 877
 878         /* Bus validation ? */
 879         if (pe->pbus) {
 880                 int count;
 881
 882                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 883                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 884                 parent = pe->pbus->self;
 885                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 886                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 887                 else
 888                         count = 1;
 889
 890                 switch(count) {
 891                 case  1: bcomp = OpalPciBusAll;         break;
 892                 case  2: bcomp = OpalPciBus7Bits;       break;
 893                 case  4: bcomp = OpalPciBus6Bits;       break;
 894                 case  8: bcomp = OpalPciBus5Bits;       break;
 895                 case 16: bcomp = OpalPciBus4Bits;       break;
 896                 case 32: bcomp = OpalPciBus3Bits;       break;
 897                 default:
 898                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 899                                 count);
 900                         /* Do an exact match only */
 901                         bcomp = OpalPciBusAll;
 902                 }
 903                 rid_end = pe->rid + (count << 8);
 904         } else {
 905 #ifdef CONFIG_PCI_IOV
 906                 if (pe->flags & PNV_IODA_PE_VF)
 907                         parent = pe->parent_dev;
 908                 else
 909 #endif /* CONFIG_PCI_IOV */
 910                         parent = pe->pdev->bus->self;
 911                 bcomp = OpalPciBusAll;
 912                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 913                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 914                 rid_end = pe->rid + 1;
 915         }
 916
 917         /*
 918          * Associate PE in PELT. We need add the PE into the
 919          * corresponding PELT-V as well. Otherwise, the error
 920          * originated from the PE might contribute to other
 921          * PEs.
 922          */
 923         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 924                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 925         if (rc) {
 926                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 927                 return -ENXIO;
 928         }
 929
 930         /*
 931          * Configure PELTV. NPUs don't have a PELTV table so skip
 932          * configuration on them.
 933          */
 934         if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
 935                 pnv_ioda_set_peltv(phb, pe, true);
 936
 937         /* Setup reverse map */
 938         for (rid = pe->rid; rid < rid_end; rid++)
 939                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 940
 941         /* Setup one MVTs on IODA1 */
 942         if (phb->type != PNV_PHB_IODA1) {
 943                 pe->mve_number = 0;
 944                 goto out;
 945         }
 946
 947         pe->mve_number = pe->pe_number;
 948         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 949         if (rc != OPAL_SUCCESS) {
 950                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 951                        rc, pe->mve_number);
 952                 pe->mve_number = -1;
 953         } else {
 954                 rc = opal_pci_set_mve_enable(phb->opal_id,
 955                                              pe->mve_number, OPAL_ENABLE_MVE);
 956                 if (rc) {
 957                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 958                                rc, pe->mve_number);
 959                         pe->mve_number = -1;
 960                 }
 961         }
 962
 963 out:
 964         return 0;
 965 }
 966
 967 #ifdef CONFIG_PCI_IOV
 968 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 969 {
 970         struct pci_dn *pdn = pci_get_pdn(dev);
 971         int i;
 972         struct resource *res, res2;
 973         resource_size_t size;
 974         u16 num_vfs;
 975
 976         if (!dev->is_physfn)
 977                 return -EINVAL;
 978
 979         /*
 980          * "offset" is in VFs.  The M64 windows are sized so that when they
 981          * are segmented, each segment is the same size as the IOV BAR.
 982          * Each segment is in a separate PE, and the high order bits of the
 983          * address are the PE number.  Therefore, each VF's BAR is in a
 984          * separate PE, and changing the IOV BAR start address changes the
 985          * range of PEs the VFs are in.
 986          */
 987         num_vfs = pdn->num_vfs;
 988         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 989                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 990                 if (!res->flags || !res->parent)
 991                         continue;
 992
 993                 /*
 994                  * The actual IOV BAR range is determined by the start address
 995                  * and the actual size for num_vfs VFs BAR.  This check is to
 996                  * make sure that after shifting, the range will not overlap
 997                  * with another device.
 998                  */
 999                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1000                 res2.flags = res->flags;
1001                 res2.start = res->start + (size * offset);
1002                 res2.end = res2.start + (size * num_vfs) - 1;
1003
1004                 if (res2.end > res->end) {
1005                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1006                                 i, &res2, res, num_vfs, offset);
1007                         return -EBUSY;
1008                 }
1009         }
1010
1011         /*
1012          * Since M64 BAR shares segments among all possible 256 PEs,
1013          * we have to shift the beginning of PF IOV BAR to make it start from
1014          * the segment which belongs to the PE number assigned to the first VF.
1015          * This creates a "hole" in the /proc/iomem which could be used for
1016          * allocating other resources so we reserve this area below and
1017          * release when IOV is released.
1018          */
1019         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1020                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1021                 if (!res->flags || !res->parent)
1022                         continue;
1023
1024                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1025                 res2 = *res;
1026                 res->start += size * offset;
1027
1028                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1029                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1030                          num_vfs, offset);
1031
1032                 if (offset < 0) {
1033                         devm_release_resource(&dev->dev, &pdn->holes[i]);
1034                         memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1035                 }
1036
1037                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1038
1039                 if (offset > 0) {
1040                         pdn->holes[i].start = res2.start;
1041                         pdn->holes[i].end = res2.start + size * offset - 1;
1042                         pdn->holes[i].flags = IORESOURCE_BUS;
1043                         pdn->holes[i].name = "pnv_iov_reserved";
1044                         devm_request_resource(&dev->dev, res->parent,
1045                                         &pdn->holes[i]);
1046                 }
1047         }
1048         return 0;
1049 }
1050 #endif /* CONFIG_PCI_IOV */
1051
1052 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1053 {
1054         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1055         struct pnv_phb *phb = hose->private_data;
1056         struct pci_dn *pdn = pci_get_pdn(dev);
1057         struct pnv_ioda_pe *pe;
1058
1059         if (!pdn) {
1060                 pr_err("%s: Device tree node not associated properly\n",
1061                            pci_name(dev));
1062                 return NULL;
1063         }
1064         if (pdn->pe_number != IODA_INVALID_PE)
1065                 return NULL;
1066
1067         pe = pnv_ioda_alloc_pe(phb);
1068         if (!pe) {
1069                 pr_warn("%s: Not enough PE# available, disabling device\n",
1070                         pci_name(dev));
1071                 return NULL;
1072         }
1073
1074         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1075          * pointer in the PE data structure, both should be destroyed at the
1076          * same time. However, this needs to be looked at more closely again
1077          * once we actually start removing things (Hotplug, SR-IOV, ...)
1078          *
1079          * At some point we want to remove the PDN completely anyways
1080          */
1081         pci_dev_get(dev);
1082         pdn->pe_number = pe->pe_number;
1083         pe->flags = PNV_IODA_PE_DEV;
1084         pe->pdev = dev;
1085         pe->pbus = NULL;
1086         pe->mve_number = -1;
1087         pe->rid = dev->bus->number << 8 | pdn->devfn;
1088
1089         pe_info(pe, "Associated device to PE\n");
1090
1091         if (pnv_ioda_configure_pe(phb, pe)) {
1092                 /* XXX What do we do here ? */
1093                 pnv_ioda_free_pe(pe);
1094                 pdn->pe_number = IODA_INVALID_PE;
1095                 pe->pdev = NULL;
1096                 pci_dev_put(dev);
1097                 return NULL;
1098         }
1099
1100         /* Put PE to the list */
1101         list_add_tail(&pe->list, &phb->ioda.pe_list);
1102
1103         return pe;
1104 }
1105
1106 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1107 {
1108         struct pci_dev *dev;
1109
1110         list_for_each_entry(dev, &bus->devices, bus_list) {
1111                 struct pci_dn *pdn = pci_get_pdn(dev);
1112
1113                 if (pdn == NULL) {
1114                         pr_warn("%s: No device node associated with device !\n",
1115                                 pci_name(dev));
1116                         continue;
1117                 }
1118
1119                 /*
1120                  * In partial hotplug case, the PCI device might be still
1121                  * associated with the PE and needn't attach it to the PE
1122                  * again.
1123                  */
1124                 if (pdn->pe_number != IODA_INVALID_PE)
1125                         continue;
1126
1127                 pe->device_count++;
1128                 pdn->pe_number = pe->pe_number;
1129                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1130                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1131         }
1132 }
1133
1134 /*
1135  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1136  * single PCI bus. Another one that contains the primary PCI bus and its
1137  * subordinate PCI devices and buses. The second type of PE is normally
1138  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1139  */
1140 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1141 {
1142         struct pci_controller *hose = pci_bus_to_host(bus);
1143         struct pnv_phb *phb = hose->private_data;
1144         struct pnv_ioda_pe *pe = NULL;
1145         unsigned int pe_num;
1146
1147         /*
1148          * In partial hotplug case, the PE instance might be still alive.
1149          * We should reuse it instead of allocating a new one.
1150          */
1151         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1152         if (pe_num != IODA_INVALID_PE) {
1153                 pe = &phb->ioda.pe_array[pe_num];
1154                 pnv_ioda_setup_same_PE(bus, pe);
1155                 return NULL;
1156         }
1157
1158         /* PE number for root bus should have been reserved */
1159         if (pci_is_root_bus(bus) &&
1160             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1161                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1162
1163         /* Check if PE is determined by M64 */
1164         if (!pe && phb->pick_m64_pe)
1165                 pe = phb->pick_m64_pe(bus, all);
1166
1167         /* The PE number isn't pinned by M64 */
1168         if (!pe)
1169                 pe = pnv_ioda_alloc_pe(phb);
1170
1171         if (!pe) {
1172                 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1173                         __func__, pci_domain_nr(bus), bus->number);
1174                 return NULL;
1175         }
1176
1177         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1178         pe->pbus = bus;
1179         pe->pdev = NULL;
1180         pe->mve_number = -1;
1181         pe->rid = bus->busn_res.start << 8;
1182
1183         if (all)
1184                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1185                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1186         else
1187                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1188                         bus->busn_res.start, pe->pe_number);
1189
1190         if (pnv_ioda_configure_pe(phb, pe)) {
1191                 /* XXX What do we do here ? */
1192                 pnv_ioda_free_pe(pe);
1193                 pe->pbus = NULL;
1194                 return NULL;
1195         }
1196
1197         /* Associate it with all child devices */
1198         pnv_ioda_setup_same_PE(bus, pe);
1199
1200         /* Put PE to the list */
1201         list_add_tail(&pe->list, &phb->ioda.pe_list);
1202
1203         return pe;
1204 }
1205
1206 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1207 {
1208         int pe_num, found_pe = false, rc;
1209         long rid;
1210         struct pnv_ioda_pe *pe;
1211         struct pci_dev *gpu_pdev;
1212         struct pci_dn *npu_pdn;
1213         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1214         struct pnv_phb *phb = hose->private_data;
1215
1216         /*
1217          * Due to a hardware errata PE#0 on the NPU is reserved for
1218          * error handling. This means we only have three PEs remaining
1219          * which need to be assigned to four links, implying some
1220          * links must share PEs.
1221          *
1222          * To achieve this we assign PEs such that NPUs linking the
1223          * same GPU get assigned the same PE.
1224          */
1225         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1226         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1227                 pe = &phb->ioda.pe_array[pe_num];
1228                 if (!pe->pdev)
1229                         continue;
1230
1231                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1232                         /*
1233                          * This device has the same peer GPU so should
1234                          * be assigned the same PE as the existing
1235                          * peer NPU.
1236                          */
1237                         dev_info(&npu_pdev->dev,
1238                                 "Associating to existing PE %x\n", pe_num);
1239                         pci_dev_get(npu_pdev);
1240                         npu_pdn = pci_get_pdn(npu_pdev);
1241                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1242                         npu_pdn->pe_number = pe_num;
1243                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1244
1245                         /* Map the PE to this link */
1246                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1247                                         OpalPciBusAll,
1248                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1249                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1250                                         OPAL_MAP_PE);
1251                         WARN_ON(rc != OPAL_SUCCESS);
1252                         found_pe = true;
1253                         break;
1254                 }
1255         }
1256
1257         if (!found_pe)
1258                 /*
1259                  * Could not find an existing PE so allocate a new
1260                  * one.
1261                  */
1262                 return pnv_ioda_setup_dev_PE(npu_pdev);
1263         else
1264                 return pe;
1265 }
1266
1267 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1268 {
1269         struct pci_dev *pdev;
1270
1271         list_for_each_entry(pdev, &bus->devices, bus_list)
1272                 pnv_ioda_setup_npu_PE(pdev);
1273 }
1274
1275 static void pnv_pci_ioda_setup_PEs(void)
1276 {
1277         struct pci_controller *hose, *tmp;
1278         struct pnv_phb *phb;
1279         struct pci_bus *bus;
1280         struct pci_dev *pdev;
1281
1282         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1283                 phb = hose->private_data;
1284                 if (phb->type == PNV_PHB_NPU_NVLINK) {
1285                         /* PE#0 is needed for error reporting */
1286                         pnv_ioda_reserve_pe(phb, 0);
1287                         pnv_ioda_setup_npu_PEs(hose->bus);
1288                         if (phb->model == PNV_PHB_MODEL_NPU2)
1289                                 pnv_npu2_init(phb);
1290                 }
1291                 if (phb->type == PNV_PHB_NPU_OCAPI) {
1292                         bus = hose->bus;
1293                         list_for_each_entry(pdev, &bus->devices, bus_list)
1294                                 pnv_ioda_setup_dev_PE(pdev);
1295                 }
1296         }
1297 }
1298
1299 #ifdef CONFIG_PCI_IOV
1300 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1301 {
1302         struct pci_bus        *bus;
1303         struct pci_controller *hose;
1304         struct pnv_phb        *phb;
1305         struct pci_dn         *pdn;
1306         int                    i, j;
1307         int                    m64_bars;
1308
1309         bus = pdev->bus;
1310         hose = pci_bus_to_host(bus);
1311         phb = hose->private_data;
1312         pdn = pci_get_pdn(pdev);
1313
1314         if (pdn->m64_single_mode)
1315                 m64_bars = num_vfs;
1316         else
1317                 m64_bars = 1;
1318
1319         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1320                 for (j = 0; j < m64_bars; j++) {
1321                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1322                                 continue;
1323                         opal_pci_phb_mmio_enable(phb->opal_id,
1324                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1325                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1326                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1327                 }
1328
1329         kfree(pdn->m64_map);
1330         return 0;
1331 }
1332
1333 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1334 {
1335         struct pci_bus        *bus;
1336         struct pci_controller *hose;
1337         struct pnv_phb        *phb;
1338         struct pci_dn         *pdn;
1339         unsigned int           win;
1340         struct resource       *res;
1341         int                    i, j;
1342         int64_t                rc;
1343         int                    total_vfs;
1344         resource_size_t        size, start;
1345         int                    pe_num;
1346         int                    m64_bars;
1347
1348         bus = pdev->bus;
1349         hose = pci_bus_to_host(bus);
1350         phb = hose->private_data;
1351         pdn = pci_get_pdn(pdev);
1352         total_vfs = pci_sriov_get_totalvfs(pdev);
1353
1354         if (pdn->m64_single_mode)
1355                 m64_bars = num_vfs;
1356         else
1357                 m64_bars = 1;
1358
1359         pdn->m64_map = kmalloc_array(m64_bars,
1360                                      sizeof(*pdn->m64_map),
1361                                      GFP_KERNEL);
1362         if (!pdn->m64_map)
1363                 return -ENOMEM;
1364         /* Initialize the m64_map to IODA_INVALID_M64 */
1365         for (i = 0; i < m64_bars ; i++)
1366                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1367                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1368
1369
1370         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1371                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1372                 if (!res->flags || !res->parent)
1373                         continue;
1374
1375                 for (j = 0; j < m64_bars; j++) {
1376                         do {
1377                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1378                                                 phb->ioda.m64_bar_idx + 1, 0);
1379
1380                                 if (win >= phb->ioda.m64_bar_idx + 1)
1381                                         goto m64_failed;
1382                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1383
1384                         pdn->m64_map[j][i] = win;
1385
1386                         if (pdn->m64_single_mode) {
1387                                 size = pci_iov_resource_size(pdev,
1388                                                         PCI_IOV_RESOURCES + i);
1389                                 start = res->start + size * j;
1390                         } else {
1391                                 size = resource_size(res);
1392                                 start = res->start;
1393                         }
1394
1395                         /* Map the M64 here */
1396                         if (pdn->m64_single_mode) {
1397                                 pe_num = pdn->pe_num_map[j];
1398                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1399                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1400                                                 pdn->m64_map[j][i], 0);
1401                         }
1402
1403                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1404                                                  OPAL_M64_WINDOW_TYPE,
1405                                                  pdn->m64_map[j][i],
1406                                                  start,
1407                                                  0, /* unused */
1408                                                  size);
1409
1410
1411                         if (rc != OPAL_SUCCESS) {
1412                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1413                                         win, rc);
1414                                 goto m64_failed;
1415                         }
1416
1417                         if (pdn->m64_single_mode)
1418                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1419                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1420                         else
1421                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1422                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1423
1424                         if (rc != OPAL_SUCCESS) {
1425                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1426                                         win, rc);
1427                                 goto m64_failed;
1428                         }
1429                 }
1430         }
1431         return 0;
1432
1433 m64_failed:
1434         pnv_pci_vf_release_m64(pdev, num_vfs);
1435         return -EBUSY;
1436 }
1437
1438 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1439                 int num);
1440
1441 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1442 {
1443         struct iommu_table    *tbl;
1444         int64_t               rc;
1445
1446         tbl = pe->table_group.tables[0];
1447         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1448         if (rc)
1449                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1450
1451         pnv_pci_ioda2_set_bypass(pe, false);
1452         if (pe->table_group.group) {
1453                 iommu_group_put(pe->table_group.group);
1454                 BUG_ON(pe->table_group.group);
1455         }
1456         iommu_tce_table_put(tbl);
1457 }
1458
1459 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1460 {
1461         struct pci_bus        *bus;
1462         struct pci_controller *hose;
1463         struct pnv_phb        *phb;
1464         struct pnv_ioda_pe    *pe, *pe_n;
1465         struct pci_dn         *pdn;
1466
1467         bus = pdev->bus;
1468         hose = pci_bus_to_host(bus);
1469         phb = hose->private_data;
1470         pdn = pci_get_pdn(pdev);
1471
1472         if (!pdev->is_physfn)
1473                 return;
1474
1475         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1476                 if (pe->parent_dev != pdev)
1477                         continue;
1478
1479                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1480
1481                 /* Remove from list */
1482                 mutex_lock(&phb->ioda.pe_list_mutex);
1483                 list_del(&pe->list);
1484                 mutex_unlock(&phb->ioda.pe_list_mutex);
1485
1486                 pnv_ioda_deconfigure_pe(phb, pe);
1487
1488                 pnv_ioda_free_pe(pe);
1489         }
1490 }
1491
1492 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1493 {
1494         struct pci_bus        *bus;
1495         struct pci_controller *hose;
1496         struct pnv_phb        *phb;
1497         struct pnv_ioda_pe    *pe;
1498         struct pci_dn         *pdn;
1499         u16                    num_vfs, i;
1500
1501         bus = pdev->bus;
1502         hose = pci_bus_to_host(bus);
1503         phb = hose->private_data;
1504         pdn = pci_get_pdn(pdev);
1505         num_vfs = pdn->num_vfs;
1506
1507         /* Release VF PEs */
1508         pnv_ioda_release_vf_PE(pdev);
1509
1510         if (phb->type == PNV_PHB_IODA2) {
1511                 if (!pdn->m64_single_mode)
1512                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1513
1514                 /* Release M64 windows */
1515                 pnv_pci_vf_release_m64(pdev, num_vfs);
1516
1517                 /* Release PE numbers */
1518                 if (pdn->m64_single_mode) {
1519                         for (i = 0; i < num_vfs; i++) {
1520                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1521                                         continue;
1522
1523                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1524                                 pnv_ioda_free_pe(pe);
1525                         }
1526                 } else
1527                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1528                 /* Releasing pe_num_map */
1529                 kfree(pdn->pe_num_map);
1530         }
1531 }
1532
1533 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1534                                        struct pnv_ioda_pe *pe);
1535 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1536 {
1537         struct pci_bus        *bus;
1538         struct pci_controller *hose;
1539         struct pnv_phb        *phb;
1540         struct pnv_ioda_pe    *pe;
1541         int                    pe_num;
1542         u16                    vf_index;
1543         struct pci_dn         *pdn;
1544
1545         bus = pdev->bus;
1546         hose = pci_bus_to_host(bus);
1547         phb = hose->private_data;
1548         pdn = pci_get_pdn(pdev);
1549
1550         if (!pdev->is_physfn)
1551                 return;
1552
1553         /* Reserve PE for each VF */
1554         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1555                 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1556                 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1557                 struct pci_dn *vf_pdn;
1558
1559                 if (pdn->m64_single_mode)
1560                         pe_num = pdn->pe_num_map[vf_index];
1561                 else
1562                         pe_num = *pdn->pe_num_map + vf_index;
1563
1564                 pe = &phb->ioda.pe_array[pe_num];
1565                 pe->pe_number = pe_num;
1566                 pe->phb = phb;
1567                 pe->flags = PNV_IODA_PE_VF;
1568                 pe->pbus = NULL;
1569                 pe->parent_dev = pdev;
1570                 pe->mve_number = -1;
1571                 pe->rid = (vf_bus << 8) | vf_devfn;
1572
1573                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1574                         hose->global_number, pdev->bus->number,
1575                         PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1576
1577                 if (pnv_ioda_configure_pe(phb, pe)) {
1578                         /* XXX What do we do here ? */
1579                         pnv_ioda_free_pe(pe);
1580                         pe->pdev = NULL;
1581                         continue;
1582                 }
1583
1584                 /* Put PE to the list */
1585                 mutex_lock(&phb->ioda.pe_list_mutex);
1586                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1587                 mutex_unlock(&phb->ioda.pe_list_mutex);
1588
1589                 /* associate this pe to it's pdn */
1590                 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1591                         if (vf_pdn->busno == vf_bus &&
1592                             vf_pdn->devfn == vf_devfn) {
1593                                 vf_pdn->pe_number = pe_num;
1594                                 break;
1595                         }
1596                 }
1597
1598                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1599         }
1600 }
1601
1602 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1603 {
1604         struct pci_bus        *bus;
1605         struct pci_controller *hose;
1606         struct pnv_phb        *phb;
1607         struct pnv_ioda_pe    *pe;
1608         struct pci_dn         *pdn;
1609         int                    ret;
1610         u16                    i;
1611
1612         bus = pdev->bus;
1613         hose = pci_bus_to_host(bus);
1614         phb = hose->private_data;
1615         pdn = pci_get_pdn(pdev);
1616
1617         if (phb->type == PNV_PHB_IODA2) {
1618                 if (!pdn->vfs_expanded) {
1619                         dev_info(&pdev->dev, "don't support this SRIOV device"
1620                                 " with non 64bit-prefetchable IOV BAR\n");
1621                         return -ENOSPC;
1622                 }
1623
1624                 /*
1625                  * When M64 BARs functions in Single PE mode, the number of VFs
1626                  * could be enabled must be less than the number of M64 BARs.
1627                  */
1628                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1629                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1630                         return -EBUSY;
1631                 }
1632
1633                 /* Allocating pe_num_map */
1634                 if (pdn->m64_single_mode)
1635                         pdn->pe_num_map = kmalloc_array(num_vfs,
1636                                                         sizeof(*pdn->pe_num_map),
1637                                                         GFP_KERNEL);
1638                 else
1639                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1640
1641                 if (!pdn->pe_num_map)
1642                         return -ENOMEM;
1643
1644                 if (pdn->m64_single_mode)
1645                         for (i = 0; i < num_vfs; i++)
1646                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1647
1648                 /* Calculate available PE for required VFs */
1649                 if (pdn->m64_single_mode) {
1650                         for (i = 0; i < num_vfs; i++) {
1651                                 pe = pnv_ioda_alloc_pe(phb);
1652                                 if (!pe) {
1653                                         ret = -EBUSY;
1654                                         goto m64_failed;
1655                                 }
1656
1657                                 pdn->pe_num_map[i] = pe->pe_number;
1658                         }
1659                 } else {
1660                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1661                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1662                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1663                                 0, num_vfs, 0);
1664                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1665                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1666                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1667                                 kfree(pdn->pe_num_map);
1668                                 return -EBUSY;
1669                         }
1670                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1671                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1672                 }
1673                 pdn->num_vfs = num_vfs;
1674
1675                 /* Assign M64 window accordingly */
1676                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1677                 if (ret) {
1678                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1679                         goto m64_failed;
1680                 }
1681
1682                 /*
1683                  * When using one M64 BAR to map one IOV BAR, we need to shift
1684                  * the IOV BAR according to the PE# allocated to the VFs.
1685                  * Otherwise, the PE# for the VF will conflict with others.
1686                  */
1687                 if (!pdn->m64_single_mode) {
1688                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1689                         if (ret)
1690                                 goto m64_failed;
1691                 }
1692         }
1693
1694         /* Setup VF PEs */
1695         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1696
1697         return 0;
1698
1699 m64_failed:
1700         if (pdn->m64_single_mode) {
1701                 for (i = 0; i < num_vfs; i++) {
1702                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1703                                 continue;
1704
1705                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1706                         pnv_ioda_free_pe(pe);
1707                 }
1708         } else
1709                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1710
1711         /* Releasing pe_num_map */
1712         kfree(pdn->pe_num_map);
1713
1714         return ret;
1715 }
1716
1717 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1718 {
1719         pnv_pci_sriov_disable(pdev);
1720
1721         /* Release PCI data */
1722         remove_dev_pci_data(pdev);
1723         return 0;
1724 }
1725
1726 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1727 {
1728         /* Allocate PCI data */
1729         add_dev_pci_data(pdev);
1730
1731         return pnv_pci_sriov_enable(pdev, num_vfs);
1732 }
1733 #endif /* CONFIG_PCI_IOV */
1734
1735 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1736 {
1737         struct pci_dn *pdn = pci_get_pdn(pdev);
1738         struct pnv_ioda_pe *pe;
1739
1740         /*
1741          * The function can be called while the PE#
1742          * hasn't been assigned. Do nothing for the
1743          * case.
1744          */
1745         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1746                 return;
1747
1748         pe = &phb->ioda.pe_array[pdn->pe_number];
1749         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1750         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1751         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1752         /*
1753          * Note: iommu_add_device() will fail here as
1754          * for physical PE: the device is already added by now;
1755          * for virtual PE: sysfs entries are not ready yet and
1756          * tce_iommu_bus_notifier will add the device to a group later.
1757          */
1758 }
1759
1760 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1761 {
1762         unsigned short vendor = 0;
1763         struct pci_dev *pdev;
1764
1765         if (pe->device_count == 1)
1766                 return true;
1767
1768         /* pe->pdev should be set if it's a single device, pe->pbus if not */
1769         if (!pe->pbus)
1770                 return true;
1771
1772         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1773                 if (!vendor) {
1774                         vendor = pdev->vendor;
1775                         continue;
1776                 }
1777
1778                 if (pdev->vendor != vendor)
1779                         return false;
1780         }
1781
1782         return true;
1783 }
1784
1785 /*
1786  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1787  *
1788  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1789  * Devices can only access more than that if bit 59 of the PCI address is set
1790  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1791  * Many PCI devices are not capable of addressing that many bits, and as a
1792  * result are limited to the 4GB of virtual memory made available to 32-bit
1793  * devices in TVE#0.
1794  *
1795  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1796  * devices by configuring the virtual memory past the first 4GB inaccessible
1797  * by 64-bit DMAs.  This should only be used by devices that want more than
1798  * 4GB, and only on PEs that have no 32-bit devices.
1799  *
1800  * Currently this will only work on PHB3 (POWER8).
1801  */
1802 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1803 {
1804         u64 window_size, table_size, tce_count, addr;
1805         struct page *table_pages;
1806         u64 tce_order = 28; /* 256MB TCEs */
1807         __be64 *tces;
1808         s64 rc;
1809
1810         /*
1811          * Window size needs to be a power of two, but needs to account for
1812          * shifting memory by the 4GB offset required to skip 32bit space.
1813          */
1814         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1815         tce_count = window_size >> tce_order;
1816         table_size = tce_count << 3;
1817
1818         if (table_size < PAGE_SIZE)
1819                 table_size = PAGE_SIZE;
1820
1821         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1822                                        get_order(table_size));
1823         if (!table_pages)
1824                 goto err;
1825
1826         tces = page_address(table_pages);
1827         if (!tces)
1828                 goto err;
1829
1830         memset(tces, 0, table_size);
1831
1832         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1833                 tces[(addr + (1ULL << 32)) >> tce_order] =
1834                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1835         }
1836
1837         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1838                                         pe->pe_number,
1839                                         /* reconfigure window 0 */
1840                                         (pe->pe_number << 1) + 0,
1841                                         1,
1842                                         __pa(tces),
1843                                         table_size,
1844                                         1 << tce_order);
1845         if (rc == OPAL_SUCCESS) {
1846                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1847                 return 0;
1848         }
1849 err:
1850         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1851         return -EIO;
1852 }
1853
1854 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1855 {
1856         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1857         struct pnv_phb *phb = hose->private_data;
1858         struct pci_dn *pdn = pci_get_pdn(pdev);
1859         struct pnv_ioda_pe *pe;
1860         uint64_t top;
1861         bool bypass = false;
1862         s64 rc;
1863
1864         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1865                 return -ENODEV;
1866
1867         pe = &phb->ioda.pe_array[pdn->pe_number];
1868         if (pe->tce_bypass_enabled) {
1869                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1870                 bypass = (dma_mask >= top);
1871         }
1872
1873         if (bypass) {
1874                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1875                 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1876         } else {
1877                 /*
1878                  * If the device can't set the TCE bypass bit but still wants
1879                  * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1880                  * bypass the 32-bit region and be usable for 64-bit DMAs.
1881                  * The device needs to be able to address all of this space.
1882                  */
1883                 if (dma_mask >> 32 &&
1884                     dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1885                     pnv_pci_ioda_pe_single_vendor(pe) &&
1886                     phb->model == PNV_PHB_MODEL_PHB3) {
1887                         /* Configure the bypass mode */
1888                         rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1889                         if (rc)
1890                                 return rc;
1891                         /* 4GB offset bypasses 32-bit space */
1892                         set_dma_offset(&pdev->dev, (1ULL << 32));
1893                         set_dma_ops(&pdev->dev, &dma_nommu_ops);
1894                 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1895                         /*
1896                          * Fail the request if a DMA mask between 32 and 64 bits
1897                          * was requested but couldn't be fulfilled. Ideally we
1898                          * would do this for 64-bits but historically we have
1899                          * always fallen back to 32-bits.
1900                          */
1901                         return -ENOMEM;
1902                 } else {
1903                         dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1904                         set_dma_ops(&pdev->dev, &dma_iommu_ops);
1905                 }
1906         }
1907         *pdev->dev.dma_mask = dma_mask;
1908
1909         /* Update peer npu devices */
1910         pnv_npu_try_dma_set_bypass(pdev, bypass);
1911
1912         return 0;
1913 }
1914
1915 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1916 {
1917         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1918         struct pnv_phb *phb = hose->private_data;
1919         struct pci_dn *pdn = pci_get_pdn(pdev);
1920         struct pnv_ioda_pe *pe;
1921         u64 end, mask;
1922
1923         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1924                 return 0;
1925
1926         pe = &phb->ioda.pe_array[pdn->pe_number];
1927         if (!pe->tce_bypass_enabled)
1928                 return __dma_get_required_mask(&pdev->dev);
1929
1930
1931         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1932         mask = 1ULL << (fls64(end) - 1);
1933         mask += mask - 1;
1934
1935         return mask;
1936 }
1937
1938 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1939                                    struct pci_bus *bus,
1940                                    bool add_to_group)
1941 {
1942         struct pci_dev *dev;
1943
1944         list_for_each_entry(dev, &bus->devices, bus_list) {
1945                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1946                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1947                 if (add_to_group)
1948                         iommu_add_device(&dev->dev);
1949
1950                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1951                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1952                                         add_to_group);
1953         }
1954 }
1955
1956 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1957                                                      bool real_mode)
1958 {
1959         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1960                 (phb->regs + 0x210);
1961 }
1962
1963 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1964                 unsigned long index, unsigned long npages, bool rm)
1965 {
1966         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1967                         &tbl->it_group_list, struct iommu_table_group_link,
1968                         next);
1969         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1970                         struct pnv_ioda_pe, table_group);
1971         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1972         unsigned long start, end, inc;
1973
1974         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1975         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1976                         npages - 1);
1977
1978         /* p7ioc-style invalidation, 2 TCEs per write */
1979         start |= (1ull << 63);
1980         end |= (1ull << 63);
1981         inc = 16;
1982         end |= inc - 1; /* round up end to be different than start */
1983
1984         mb(); /* Ensure above stores are visible */
1985         while (start <= end) {
1986                 if (rm)
1987                         __raw_rm_writeq_be(start, invalidate);
1988                 else
1989                         __raw_writeq_be(start, invalidate);
1990
1991                 start += inc;
1992         }
1993
1994         /*
1995          * The iommu layer will do another mb() for us on build()
1996          * and we don't care on free()
1997          */
1998 }
1999
2000 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
2001                 long npages, unsigned long uaddr,
2002                 enum dma_data_direction direction,
2003                 unsigned long attrs)
2004 {
2005         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2006                         attrs);
2007
2008         if (!ret)
2009                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2010
2011         return ret;
2012 }
2013
2014 #ifdef CONFIG_IOMMU_API
2015 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
2016                 unsigned long *hpa, enum dma_data_direction *direction)
2017 {
2018         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2019
2020         if (!ret)
2021                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2022
2023         return ret;
2024 }
2025
2026 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2027                 unsigned long *hpa, enum dma_data_direction *direction)
2028 {
2029         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2030
2031         if (!ret)
2032                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2033
2034         return ret;
2035 }
2036 #endif
2037
2038 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2039                 long npages)
2040 {
2041         pnv_tce_free(tbl, index, npages);
2042
2043         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2044 }
2045
2046 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2047         .set = pnv_ioda1_tce_build,
2048 #ifdef CONFIG_IOMMU_API
2049         .exchange = pnv_ioda1_tce_xchg,
2050         .exchange_rm = pnv_ioda1_tce_xchg_rm,
2051         .useraddrptr = pnv_tce_useraddrptr,
2052 #endif
2053         .clear = pnv_ioda1_tce_free,
2054         .get = pnv_tce_get,
2055 };
2056
2057 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
2058 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
2059 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
2060
2061 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2062 {
2063         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2064         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2065
2066         mb(); /* Ensure previous TCE table stores are visible */
2067         if (rm)
2068                 __raw_rm_writeq_be(val, invalidate);
2069         else
2070                 __raw_writeq_be(val, invalidate);
2071 }
2072
2073 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2074 {
2075         /* 01xb - invalidate TCEs that match the specified PE# */
2076         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2077         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2078
2079         mb(); /* Ensure above stores are visible */
2080         __raw_writeq_be(val, invalidate);
2081 }
2082
2083 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2084                                         unsigned shift, unsigned long index,
2085                                         unsigned long npages)
2086 {
2087         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2088         unsigned long start, end, inc;
2089
2090         /* We'll invalidate DMA address in PE scope */
2091         start = PHB3_TCE_KILL_INVAL_ONE;
2092         start |= (pe->pe_number & 0xFF);
2093         end = start;
2094
2095         /* Figure out the start, end and step */
2096         start |= (index << shift);
2097         end |= ((index + npages - 1) << shift);
2098         inc = (0x1ull << shift);
2099         mb();
2100
2101         while (start <= end) {
2102                 if (rm)
2103                         __raw_rm_writeq_be(start, invalidate);
2104                 else
2105                         __raw_writeq_be(start, invalidate);
2106                 start += inc;
2107         }
2108 }
2109
2110 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2111 {
2112         struct pnv_phb *phb = pe->phb;
2113
2114         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2115                 pnv_pci_phb3_tce_invalidate_pe(pe);
2116         else
2117                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2118                                   pe->pe_number, 0, 0, 0);
2119 }
2120
2121 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2122                 unsigned long index, unsigned long npages, bool rm)
2123 {
2124         struct iommu_table_group_link *tgl;
2125
2126         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2127                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2128                                 struct pnv_ioda_pe, table_group);
2129                 struct pnv_phb *phb = pe->phb;
2130                 unsigned int shift = tbl->it_page_shift;
2131
2132                 /*
2133                  * NVLink1 can use the TCE kill register directly as
2134                  * it's the same as PHB3. NVLink2 is different and
2135                  * should go via the OPAL call.
2136                  */
2137                 if (phb->model == PNV_PHB_MODEL_NPU) {
2138                         /*
2139                          * The NVLink hardware does not support TCE kill
2140                          * per TCE entry so we have to invalidate
2141                          * the entire cache for it.
2142                          */
2143                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2144                         continue;
2145                 }
2146                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2147                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2148                                                     index, npages);
2149                 else
2150                         opal_pci_tce_kill(phb->opal_id,
2151                                           OPAL_PCI_TCE_KILL_PAGES,
2152                                           pe->pe_number, 1u << shift,
2153                                           index << shift, npages);
2154         }
2155 }
2156
2157 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2158 {
2159         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2160                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2161         else
2162                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2163 }
2164
2165 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2166                 long npages, unsigned long uaddr,
2167                 enum dma_data_direction direction,
2168                 unsigned long attrs)
2169 {
2170         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2171                         attrs);
2172
2173         if (!ret)
2174                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2175
2176         return ret;
2177 }
2178
2179 #ifdef CONFIG_IOMMU_API
2180 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2181                 unsigned long *hpa, enum dma_data_direction *direction)
2182 {
2183         long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2184
2185         if (!ret)
2186                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2187
2188         return ret;
2189 }
2190
2191 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2192                 unsigned long *hpa, enum dma_data_direction *direction)
2193 {
2194         long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2195
2196         if (!ret)
2197                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2198
2199         return ret;
2200 }
2201 #endif
2202
2203 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2204                 long npages)
2205 {
2206         pnv_tce_free(tbl, index, npages);
2207
2208         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2209 }
2210
2211 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2212         .set = pnv_ioda2_tce_build,
2213 #ifdef CONFIG_IOMMU_API
2214         .exchange = pnv_ioda2_tce_xchg,
2215         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2216         .useraddrptr = pnv_tce_useraddrptr,
2217 #endif
2218         .clear = pnv_ioda2_tce_free,
2219         .get = pnv_tce_get,
2220         .free = pnv_pci_ioda2_table_free_pages,
2221 };
2222
2223 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2224 {
2225         unsigned int *weight = (unsigned int *)data;
2226
2227         /* This is quite simplistic. The "base" weight of a device
2228          * is 10. 0 means no DMA is to be accounted for it.
2229          */
2230         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2231                 return 0;
2232
2233         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2234             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2235             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2236                 *weight += 3;
2237         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2238                 *weight += 15;
2239         else
2240                 *weight += 10;
2241
2242         return 0;
2243 }
2244
2245 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2246 {
2247         unsigned int weight = 0;
2248
2249         /* SRIOV VF has same DMA32 weight as its PF */
2250 #ifdef CONFIG_PCI_IOV
2251         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2252                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2253                 return weight;
2254         }
2255 #endif
2256
2257         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2258                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2259         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2260                 struct pci_dev *pdev;
2261
2262                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2263                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2264         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2265                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2266         }
2267
2268         return weight;
2269 }
2270
2271 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2272                                        struct pnv_ioda_pe *pe)
2273 {
2274
2275         struct page *tce_mem = NULL;
2276         struct iommu_table *tbl;
2277         unsigned int weight, total_weight = 0;
2278         unsigned int tce32_segsz, base, segs, avail, i;
2279         int64_t rc;
2280         void *addr;
2281
2282         /* XXX FIXME: Handle 64-bit only DMA devices */
2283         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2284         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2285         weight = pnv_pci_ioda_pe_dma_weight(pe);
2286         if (!weight)
2287                 return;
2288
2289         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2290                      &total_weight);
2291         segs = (weight * phb->ioda.dma32_count) / total_weight;
2292         if (!segs)
2293                 segs = 1;
2294
2295         /*
2296          * Allocate contiguous DMA32 segments. We begin with the expected
2297          * number of segments. With one more attempt, the number of DMA32
2298          * segments to be allocated is decreased by one until one segment
2299          * is allocated successfully.
2300          */
2301         do {
2302                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2303                         for (avail = 0, i = base; i < base + segs; i++) {
2304                                 if (phb->ioda.dma32_segmap[i] ==
2305                                     IODA_INVALID_PE)
2306                                         avail++;
2307                         }
2308
2309                         if (avail == segs)
2310                                 goto found;
2311                 }
2312         } while (--segs);
2313
2314         if (!segs) {
2315                 pe_warn(pe, "No available DMA32 segments\n");
2316                 return;
2317         }
2318
2319 found:
2320         tbl = pnv_pci_table_alloc(phb->hose->node);
2321         if (WARN_ON(!tbl))
2322                 return;
2323
2324         iommu_register_group(&pe->table_group, phb->hose->global_number,
2325                         pe->pe_number);
2326         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2327
2328         /* Grab a 32-bit TCE table */
2329         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2330                 weight, total_weight, base, segs);
2331         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2332                 base * PNV_IODA1_DMA32_SEGSIZE,
2333                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2334
2335         /* XXX Currently, we allocate one big contiguous table for the
2336          * TCEs. We only really need one chunk per 256M of TCE space
2337          * (ie per segment) but that's an optimization for later, it
2338          * requires some added smarts with our get/put_tce implementation
2339          *
2340          * Each TCE page is 4KB in size and each TCE entry occupies 8
2341          * bytes
2342          */
2343         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2344         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2345                                    get_order(tce32_segsz * segs));
2346         if (!tce_mem) {
2347                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2348                 goto fail;
2349         }
2350         addr = page_address(tce_mem);
2351         memset(addr, 0, tce32_segsz * segs);
2352
2353         /* Configure HW */
2354         for (i = 0; i < segs; i++) {
2355                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2356                                               pe->pe_number,
2357                                               base + i, 1,
2358                                               __pa(addr) + tce32_segsz * i,
2359                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2360                 if (rc) {
2361                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2362                                " err %ld\n", rc);
2363                         goto fail;
2364                 }
2365         }
2366
2367         /* Setup DMA32 segment mapping */
2368         for (i = base; i < base + segs; i++)
2369                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2370
2371         /* Setup linux iommu table */
2372         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2373                                   base * PNV_IODA1_DMA32_SEGSIZE,
2374                                   IOMMU_PAGE_SHIFT_4K);
2375
2376         tbl->it_ops = &pnv_ioda1_iommu_ops;
2377         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2378         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2379         iommu_init_table(tbl, phb->hose->node);
2380
2381         if (pe->flags & PNV_IODA_PE_DEV) {
2382                 /*
2383                  * Setting table base here only for carrying iommu_group
2384                  * further down to let iommu_add_device() do the job.
2385                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2386                  */
2387                 set_iommu_table_base(&pe->pdev->dev, tbl);
2388                 iommu_add_device(&pe->pdev->dev);
2389         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2390                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2391
2392         return;
2393  fail:
2394         /* XXX Failure: Try to fallback to 64-bit only ? */
2395         if (tce_mem)
2396                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2397         if (tbl) {
2398                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2399                 iommu_tce_table_put(tbl);
2400         }
2401 }
2402
2403 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2404                 int num, struct iommu_table *tbl)
2405 {
2406         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2407                         table_group);
2408         struct pnv_phb *phb = pe->phb;
2409         int64_t rc;
2410         const unsigned long size = tbl->it_indirect_levels ?
2411                         tbl->it_level_size : tbl->it_size;
2412         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2413         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2414
2415         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2416                         start_addr, start_addr + win_size - 1,
2417                         IOMMU_PAGE_SIZE(tbl));
2418
2419         /*
2420          * Map TCE table through TVT. The TVE index is the PE number
2421          * shifted by 1 bit for 32-bits DMA space.
2422          */
2423         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2424                         pe->pe_number,
2425                         (pe->pe_number << 1) + num,
2426                         tbl->it_indirect_levels + 1,
2427                         __pa(tbl->it_base),
2428                         size << 3,
2429                         IOMMU_PAGE_SIZE(tbl));
2430         if (rc) {
2431                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2432                 return rc;
2433         }
2434
2435         pnv_pci_link_table_and_group(phb->hose->node, num,
2436                         tbl, &pe->table_group);
2437         pnv_pci_ioda2_tce_invalidate_pe(pe);
2438
2439         return 0;
2440 }
2441
2442 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2443 {
2444         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2445         int64_t rc;
2446
2447         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2448         if (enable) {
2449                 phys_addr_t top = memblock_end_of_DRAM();
2450
2451                 top = roundup_pow_of_two(top);
2452                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2453                                                      pe->pe_number,
2454                                                      window_id,
2455                                                      pe->tce_bypass_base,
2456                                                      top);
2457         } else {
2458                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2459                                                      pe->pe_number,
2460                                                      window_id,
2461                                                      pe->tce_bypass_base,
2462                                                      0);
2463         }
2464         if (rc)
2465                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2466         else
2467                 pe->tce_bypass_enabled = enable;
2468 }
2469
2470 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2471                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2472                 bool alloc_userspace_copy, struct iommu_table **ptbl)
2473 {
2474         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2475                         table_group);
2476         int nid = pe->phb->hose->node;
2477         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2478         long ret;
2479         struct iommu_table *tbl;
2480
2481         tbl = pnv_pci_table_alloc(nid);
2482         if (!tbl)
2483                 return -ENOMEM;
2484
2485         tbl->it_ops = &pnv_ioda2_iommu_ops;
2486
2487         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2488                         bus_offset, page_shift, window_size,
2489                         levels, alloc_userspace_copy, tbl);
2490         if (ret) {
2491                 iommu_tce_table_put(tbl);
2492                 return ret;
2493         }
2494
2495         *ptbl = tbl;
2496
2497         return 0;
2498 }
2499
2500 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2501 {
2502         struct iommu_table *tbl = NULL;
2503         long rc;
2504
2505         /*
2506          * crashkernel= specifies the kdump kernel's maximum memory at
2507          * some offset and there is no guaranteed the result is a power
2508          * of 2, which will cause errors later.
2509          */
2510         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2511
2512         /*
2513          * In memory constrained environments, e.g. kdump kernel, the
2514          * DMA window can be larger than available memory, which will
2515          * cause errors later.
2516          */
2517         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2518
2519         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2520                         IOMMU_PAGE_SHIFT_4K,
2521                         window_size,
2522                         POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2523         if (rc) {
2524                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2525                                 rc);
2526                 return rc;
2527         }
2528
2529         iommu_init_table(tbl, pe->phb->hose->node);
2530
2531         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2532         if (rc) {
2533                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2534                                 rc);
2535                 iommu_tce_table_put(tbl);
2536                 return rc;
2537         }
2538
2539         if (!pnv_iommu_bypass_disabled)
2540                 pnv_pci_ioda2_set_bypass(pe, true);
2541
2542         /*
2543          * Setting table base here only for carrying iommu_group
2544          * further down to let iommu_add_device() do the job.
2545          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2546          */
2547         if (pe->flags & PNV_IODA_PE_DEV)
2548                 set_iommu_table_base(&pe->pdev->dev, tbl);
2549
2550         return 0;
2551 }
2552
2553 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2554 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2555                 int num)
2556 {
2557         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2558                         table_group);
2559         struct pnv_phb *phb = pe->phb;
2560         long ret;
2561
2562         pe_info(pe, "Removing DMA window #%d\n", num);
2563
2564         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2565                         (pe->pe_number << 1) + num,
2566                         0/* levels */, 0/* table address */,
2567                         0/* table size */, 0/* page size */);
2568         if (ret)
2569                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2570         else
2571                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2572
2573         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2574
2575         return ret;
2576 }
2577 #endif
2578
2579 #ifdef CONFIG_IOMMU_API
2580 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2581                 __u64 window_size, __u32 levels)
2582 {
2583         unsigned long bytes = 0;
2584         const unsigned window_shift = ilog2(window_size);
2585         unsigned entries_shift = window_shift - page_shift;
2586         unsigned table_shift = entries_shift + 3;
2587         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2588         unsigned long direct_table_size;
2589
2590         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2591                         !is_power_of_2(window_size))
2592                 return 0;
2593
2594         /* Calculate a direct table size from window_size and levels */
2595         entries_shift = (entries_shift + levels - 1) / levels;
2596         table_shift = entries_shift + 3;
2597         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2598         direct_table_size =  1UL << table_shift;
2599
2600         for ( ; levels; --levels) {
2601                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2602
2603                 tce_table_size /= direct_table_size;
2604                 tce_table_size <<= 3;
2605                 tce_table_size = max_t(unsigned long,
2606                                 tce_table_size, direct_table_size);
2607         }
2608
2609         return bytes + bytes; /* one for HW table, one for userspace copy */
2610 }
2611
2612 static long pnv_pci_ioda2_create_table_userspace(
2613                 struct iommu_table_group *table_group,
2614                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2615                 struct iommu_table **ptbl)
2616 {
2617         long ret = pnv_pci_ioda2_create_table(table_group,
2618                         num, page_shift, window_size, levels, true, ptbl);
2619
2620         if (!ret)
2621                 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2622                                 page_shift, window_size, levels);
2623         return ret;
2624 }
2625
2626 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2627 {
2628         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2629                                                 table_group);
2630         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2631         struct iommu_table *tbl = pe->table_group.tables[0];
2632
2633         pnv_pci_ioda2_set_bypass(pe, false);
2634         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2635         if (pe->pbus)
2636                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2637         iommu_tce_table_put(tbl);
2638 }
2639
2640 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2641 {
2642         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2643                                                 table_group);
2644
2645         pnv_pci_ioda2_setup_default_config(pe);
2646         if (pe->pbus)
2647                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2648 }
2649
2650 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2651         .get_table_size = pnv_pci_ioda2_get_table_size,
2652         .create_table = pnv_pci_ioda2_create_table_userspace,
2653         .set_window = pnv_pci_ioda2_set_window,
2654         .unset_window = pnv_pci_ioda2_unset_window,
2655         .take_ownership = pnv_ioda2_take_ownership,
2656         .release_ownership = pnv_ioda2_release_ownership,
2657 };
2658
2659 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2660 {
2661         struct pci_controller *hose;
2662         struct pnv_phb *phb;
2663         struct pnv_ioda_pe **ptmppe = opaque;
2664         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2665         struct pci_dn *pdn = pci_get_pdn(pdev);
2666
2667         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2668                 return 0;
2669
2670         hose = pci_bus_to_host(pdev->bus);
2671         phb = hose->private_data;
2672         if (phb->type != PNV_PHB_NPU_NVLINK)
2673                 return 0;
2674
2675         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2676
2677         return 1;
2678 }
2679
2680 /*
2681  * This returns PE of associated NPU.
2682  * This assumes that NPU is in the same IOMMU group with GPU and there is
2683  * no other PEs.
2684  */
2685 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2686                 struct iommu_table_group *table_group)
2687 {
2688         struct pnv_ioda_pe *npe = NULL;
2689         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2690                         gpe_table_group_to_npe_cb);
2691
2692         BUG_ON(!ret || !npe);
2693
2694         return npe;
2695 }
2696
2697 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2698                 int num, struct iommu_table *tbl)
2699 {
2700         struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2701         int num2 = (num == 0) ? 1 : 0;
2702         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2703
2704         if (ret)
2705                 return ret;
2706
2707         if (table_group->tables[num2])
2708                 pnv_npu_unset_window(npe, num2);
2709
2710         ret = pnv_npu_set_window(npe, num, tbl);
2711         if (ret) {
2712                 pnv_pci_ioda2_unset_window(table_group, num);
2713                 if (table_group->tables[num2])
2714                         pnv_npu_set_window(npe, num2,
2715                                         table_group->tables[num2]);
2716         }
2717
2718         return ret;
2719 }
2720
2721 static long pnv_pci_ioda2_npu_unset_window(
2722                 struct iommu_table_group *table_group,
2723                 int num)
2724 {
2725         struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2726         int num2 = (num == 0) ? 1 : 0;
2727         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2728
2729         if (ret)
2730                 return ret;
2731
2732         if (!npe->table_group.tables[num])
2733                 return 0;
2734
2735         ret = pnv_npu_unset_window(npe, num);
2736         if (ret)
2737                 return ret;
2738
2739         if (table_group->tables[num2])
2740                 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
2741
2742         return ret;
2743 }
2744
2745 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2746 {
2747         /*
2748          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2749          * the iommu_table if 32bit DMA is enabled.
2750          */
2751         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2752         pnv_ioda2_take_ownership(table_group);
2753 }
2754
2755 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2756         .get_table_size = pnv_pci_ioda2_get_table_size,
2757         .create_table = pnv_pci_ioda2_create_table_userspace,
2758         .set_window = pnv_pci_ioda2_npu_set_window,
2759         .unset_window = pnv_pci_ioda2_npu_unset_window,
2760         .take_ownership = pnv_ioda2_npu_take_ownership,
2761         .release_ownership = pnv_ioda2_release_ownership,
2762 };
2763
2764 static void pnv_pci_ioda_setup_iommu_api(void)
2765 {
2766         struct pci_controller *hose, *tmp;
2767         struct pnv_phb *phb;
2768         struct pnv_ioda_pe *pe, *gpe;
2769
2770         /*
2771          * Now we have all PHBs discovered, time to add NPU devices to
2772          * the corresponding IOMMU groups.
2773          */
2774         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2775                 phb = hose->private_data;
2776
2777                 if (phb->type != PNV_PHB_NPU_NVLINK)
2778                         continue;
2779
2780                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2781                         gpe = pnv_pci_npu_setup_iommu(pe);
2782                         if (gpe)
2783                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2784                 }
2785         }
2786 }
2787 #else /* !CONFIG_IOMMU_API */
2788 static void pnv_pci_ioda_setup_iommu_api(void) { };
2789 #endif
2790
2791 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2792 {
2793         struct pci_controller *hose = phb->hose;
2794         struct device_node *dn = hose->dn;
2795         unsigned long mask = 0;
2796         int i, rc, count;
2797         u32 val;
2798
2799         count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2800         if (count <= 0) {
2801                 mask = SZ_4K | SZ_64K;
2802                 /* Add 16M for POWER8 by default */
2803                 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2804                                 !cpu_has_feature(CPU_FTR_ARCH_300))
2805                         mask |= SZ_16M | SZ_256M;
2806                 return mask;
2807         }
2808
2809         for (i = 0; i < count; i++) {
2810                 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2811                                                 i, &val);
2812                 if (rc == 0)
2813                         mask |= 1ULL << val;
2814         }
2815
2816         return mask;
2817 }
2818
2819 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2820                                        struct pnv_ioda_pe *pe)
2821 {
2822         int64_t rc;
2823
2824         if (!pnv_pci_ioda_pe_dma_weight(pe))
2825                 return;
2826
2827         /* TVE #1 is selected by PCI address bit 59 */
2828         pe->tce_bypass_base = 1ull << 59;
2829
2830         iommu_register_group(&pe->table_group, phb->hose->global_number,
2831                         pe->pe_number);
2832
2833         /* The PE will reserve all possible 32-bits space */
2834         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2835                 phb->ioda.m32_pci_base);
2836
2837         /* Setup linux iommu table */
2838         pe->table_group.tce32_start = 0;
2839         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2840         pe->table_group.max_dynamic_windows_supported =
2841                         IOMMU_TABLE_GROUP_MAX_TABLES;
2842         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2843         pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2844 #ifdef CONFIG_IOMMU_API
2845         pe->table_group.ops = &pnv_pci_ioda2_ops;
2846 #endif
2847
2848         rc = pnv_pci_ioda2_setup_default_config(pe);
2849         if (rc)
2850                 return;
2851
2852         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2853                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2854 }
2855
2856 #ifdef CONFIG_PCI_MSI
2857 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2858 {
2859         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2860                                            ioda.irq_chip);
2861
2862         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2863 }
2864
2865 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2866 {
2867         int64_t rc;
2868         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2869         struct irq_chip *chip = irq_data_get_irq_chip(d);
2870
2871         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2872         WARN_ON_ONCE(rc);
2873
2874         icp_native_eoi(d);
2875 }
2876
2877
2878 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2879 {
2880         struct irq_data *idata;
2881         struct irq_chip *ichip;
2882
2883         /* The MSI EOI OPAL call is only needed on PHB3 */
2884         if (phb->model != PNV_PHB_MODEL_PHB3)
2885                 return;
2886
2887         if (!phb->ioda.irq_chip_init) {
2888                 /*
2889                  * First time we setup an MSI IRQ, we need to setup the
2890                  * corresponding IRQ chip to route correctly.
2891                  */
2892                 idata = irq_get_irq_data(virq);
2893                 ichip = irq_data_get_irq_chip(idata);
2894                 phb->ioda.irq_chip_init = 1;
2895                 phb->ioda.irq_chip = *ichip;
2896                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2897         }
2898         irq_set_chip(virq, &phb->ioda.irq_chip);
2899 }
2900
2901 /*
2902  * Returns true iff chip is something that we could call
2903  * pnv_opal_pci_msi_eoi for.
2904  */
2905 bool is_pnv_opal_msi(struct irq_chip *chip)
2906 {
2907         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2908 }
2909 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2910
2911 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2912                                   unsigned int hwirq, unsigned int virq,
2913                                   unsigned int is_64, struct msi_msg *msg)
2914 {
2915         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2916         unsigned int xive_num = hwirq - phb->msi_base;
2917         __be32 data;
2918         int rc;
2919
2920         /* No PE assigned ? bail out ... no MSI for you ! */
2921         if (pe == NULL)
2922                 return -ENXIO;
2923
2924         /* Check if we have an MVE */
2925         if (pe->mve_number < 0)
2926                 return -ENXIO;
2927
2928         /* Force 32-bit MSI on some broken devices */
2929         if (dev->no_64bit_msi)
2930                 is_64 = 0;
2931
2932         /* Assign XIVE to PE */
2933         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2934         if (rc) {
2935                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2936                         pci_name(dev), rc, xive_num);
2937                 return -EIO;
2938         }
2939
2940         if (is_64) {
2941                 __be64 addr64;
2942
2943                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2944                                      &addr64, &data);
2945                 if (rc) {
2946                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2947                                 pci_name(dev), rc);
2948                         return -EIO;
2949                 }
2950                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2951                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2952         } else {
2953                 __be32 addr32;
2954
2955                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2956                                      &addr32, &data);
2957                 if (rc) {
2958                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2959                                 pci_name(dev), rc);
2960                         return -EIO;
2961                 }
2962                 msg->address_hi = 0;
2963                 msg->address_lo = be32_to_cpu(addr32);
2964         }
2965         msg->data = be32_to_cpu(data);
2966
2967         pnv_set_msi_irq_chip(phb, virq);
2968
2969         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2970                  " address=%x_%08x data=%x PE# %x\n",
2971                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2972                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2973
2974         return 0;
2975 }
2976
2977 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2978 {
2979         unsigned int count;
2980         const __be32 *prop = of_get_property(phb->hose->dn,
2981                                              "ibm,opal-msi-ranges", NULL);
2982         if (!prop) {
2983                 /* BML Fallback */
2984                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2985         }
2986         if (!prop)
2987                 return;
2988
2989         phb->msi_base = be32_to_cpup(prop);
2990         count = be32_to_cpup(prop + 1);
2991         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2992                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2993                        phb->hose->global_number);
2994                 return;
2995         }
2996
2997         phb->msi_setup = pnv_pci_ioda_msi_setup;
2998         phb->msi32_support = 1;
2999         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
3000                 count, phb->msi_base);
3001 }
3002 #else
3003 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
3004 #endif /* CONFIG_PCI_MSI */
3005
3006 #ifdef CONFIG_PCI_IOV
3007 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
3008 {
3009         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3010         struct pnv_phb *phb = hose->private_data;
3011         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
3012         struct resource *res;
3013         int i;
3014         resource_size_t size, total_vf_bar_sz;
3015         struct pci_dn *pdn;
3016         int mul, total_vfs;
3017
3018         pdn = pci_get_pdn(pdev);
3019         pdn->vfs_expanded = 0;
3020         pdn->m64_single_mode = false;
3021
3022         total_vfs = pci_sriov_get_totalvfs(pdev);
3023         mul = phb->ioda.total_pe_num;
3024         total_vf_bar_sz = 0;
3025
3026         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3027                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3028                 if (!res->flags || res->parent)
3029                         continue;
3030                 if (!pnv_pci_is_m64_flags(res->flags)) {
3031                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
3032                                         " non M64 VF BAR%d: %pR. \n",
3033                                  i, res);
3034                         goto truncate_iov;
3035                 }
3036
3037                 total_vf_bar_sz += pci_iov_resource_size(pdev,
3038                                 i + PCI_IOV_RESOURCES);
3039
3040                 /*
3041                  * If bigger than quarter of M64 segment size, just round up
3042                  * power of two.
3043                  *
3044                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3045                  * with other devices, IOV BAR size is expanded to be
3046                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
3047                  * segment size , the expanded size would equal to half of the
3048                  * whole M64 space size, which will exhaust the M64 Space and
3049                  * limit the system flexibility.  This is a design decision to
3050                  * set the boundary to quarter of the M64 segment size.
3051                  */
3052                 if (total_vf_bar_sz > gate) {
3053                         mul = roundup_pow_of_two(total_vfs);
3054                         dev_info(&pdev->dev,
3055                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3056                                 total_vf_bar_sz, gate, mul);
3057                         pdn->m64_single_mode = true;
3058                         break;
3059                 }
3060         }
3061
3062         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3063                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3064                 if (!res->flags || res->parent)
3065                         continue;
3066
3067                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3068                 /*
3069                  * On PHB3, the minimum size alignment of M64 BAR in single
3070                  * mode is 32MB.
3071                  */
3072                 if (pdn->m64_single_mode && (size < SZ_32M))
3073                         goto truncate_iov;
3074                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3075                 res->end = res->start + size * mul - 1;
3076                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3077                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3078                          i, res, mul);
3079         }
3080         pdn->vfs_expanded = mul;
3081
3082         return;
3083
3084 truncate_iov:
3085         /* To save MMIO space, IOV BAR is truncated. */
3086         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3087                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3088                 res->flags = 0;
3089                 res->end = res->start - 1;
3090         }
3091 }
3092
3093 static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
3094 {
3095         if (WARN_ON(pci_dev_is_added(pdev)))
3096                 return;
3097
3098         if (pdev->is_virtfn) {
3099                 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
3100
3101                 /*
3102                  * VF PEs are single-device PEs so their pdev pointer needs to
3103                  * be set. The pdev doesn't exist when the PE is allocated (in
3104                  * (pcibios_sriov_enable()) so we fix it up here.
3105                  */
3106                 pe->pdev = pdev;
3107                 WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
3108         } else if (pdev->is_physfn) {
3109                 /*
3110                  * For PFs adjust their allocated IOV resources to match what
3111                  * the PHB can support using it's M64 BAR table.
3112                  */
3113                 pnv_pci_ioda_fixup_iov_resources(pdev);
3114         }
3115 }
3116 #endif /* CONFIG_PCI_IOV */
3117
3118 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3119                                   struct resource *res)
3120 {
3121         struct pnv_phb *phb = pe->phb;
3122         struct pci_bus_region region;
3123         int index;
3124         int64_t rc;
3125
3126         if (!res || !res->flags || res->start > res->end)
3127                 return;
3128
3129         if (res->flags & IORESOURCE_IO) {
3130                 region.start = res->start - phb->ioda.io_pci_base;
3131                 region.end   = res->end - phb->ioda.io_pci_base;
3132                 index = region.start / phb->ioda.io_segsize;
3133
3134                 while (index < phb->ioda.total_pe_num &&
3135                        region.start <= region.end) {
3136                         phb->ioda.io_segmap[index] = pe->pe_number;
3137                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3138                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3139                         if (rc != OPAL_SUCCESS) {
3140                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3141                                        __func__, rc, index, pe->pe_number);
3142                                 break;
3143                         }
3144
3145                         region.start += phb->ioda.io_segsize;
3146                         index++;
3147                 }
3148         } else if ((res->flags & IORESOURCE_MEM) &&
3149                    !pnv_pci_is_m64(phb, res)) {
3150                 region.start = res->start -
3151                                phb->hose->mem_offset[0] -
3152                                phb->ioda.m32_pci_base;
3153                 region.end   = res->end -
3154                                phb->hose->mem_offset[0] -
3155                                phb->ioda.m32_pci_base;
3156                 index = region.start / phb->ioda.m32_segsize;
3157
3158                 while (index < phb->ioda.total_pe_num &&
3159                        region.start <= region.end) {
3160                         phb->ioda.m32_segmap[index] = pe->pe_number;
3161                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3162                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3163                         if (rc != OPAL_SUCCESS) {
3164                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3165                                        __func__, rc, index, pe->pe_number);
3166                                 break;
3167                         }
3168
3169                         region.start += phb->ioda.m32_segsize;
3170                         index++;
3171                 }
3172         }
3173 }
3174
3175 /*
3176  * This function is supposed to be called on basis of PE from top
3177  * to bottom style. So the the I/O or MMIO segment assigned to
3178  * parent PE could be overridden by its child PEs if necessary.
3179  */
3180 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3181 {
3182         struct pci_dev *pdev;
3183         int i;
3184
3185         /*
3186          * NOTE: We only care PCI bus based PE for now. For PCI
3187          * device based PE, for example SRIOV sensitive VF should
3188          * be figured out later.
3189          */
3190         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3191
3192         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3193                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3194                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3195
3196                 /*
3197                  * If the PE contains all subordinate PCI buses, the
3198                  * windows of the child bridges should be mapped to
3199                  * the PE as well.
3200                  */
3201                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3202                         continue;
3203                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3204                         pnv_ioda_setup_pe_res(pe,
3205                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3206         }
3207 }
3208
3209 #ifdef CONFIG_DEBUG_FS
3210 static int pnv_pci_diag_data_set(void *data, u64 val)
3211 {
3212         struct pci_controller *hose;
3213         struct pnv_phb *phb;
3214         s64 ret;
3215
3216         if (val != 1ULL)
3217                 return -EINVAL;
3218
3219         hose = (struct pci_controller *)data;
3220         if (!hose || !hose->private_data)
3221                 return -ENODEV;
3222
3223         phb = hose->private_data;
3224
3225         /* Retrieve the diag data from firmware */
3226         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3227                                           phb->diag_data_size);
3228         if (ret != OPAL_SUCCESS)
3229                 return -EIO;
3230
3231         /* Print the diag data to the kernel log */
3232         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3233         return 0;
3234 }
3235
3236 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3237                         pnv_pci_diag_data_set, "%llu\n");
3238
3239 #endif /* CONFIG_DEBUG_FS */
3240
3241 static void pnv_pci_ioda_create_dbgfs(void)
3242 {
3243 #ifdef CONFIG_DEBUG_FS
3244         struct pci_controller *hose, *tmp;
3245         struct pnv_phb *phb;
3246         char name[16];
3247
3248         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3249                 phb = hose->private_data;
3250
3251                 /* Notify initialization of PHB done */
3252                 phb->initialized = 1;
3253
3254                 sprintf(name, "PCI%04x", hose->global_number);
3255                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3256                 if (!phb->dbgfs) {
3257                         pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3258                                 __func__, hose->global_number);
3259                         continue;
3260                 }
3261
3262                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3263                                     &pnv_pci_diag_data_fops);
3264         }
3265 #endif /* CONFIG_DEBUG_FS */
3266 }
3267
3268 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3269 {
3270         struct pci_dev *dev = bus->self;
3271         struct pci_bus *child;
3272
3273         /* Empty bus ? bail */
3274         if (list_empty(&bus->devices))
3275                 return;
3276
3277         /*
3278          * If there's a bridge associated with that bus enable it. This works
3279          * around races in the generic code if the enabling is done during
3280          * parallel probing. This can be removed once those races have been
3281          * fixed.
3282          */
3283         if (dev) {
3284                 int rc = pci_enable_device(dev);
3285                 if (rc)
3286                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3287                 pci_set_master(dev);
3288         }
3289
3290         /* Perform the same to child busses */
3291         list_for_each_entry(child, &bus->children, node)
3292                 pnv_pci_enable_bridge(child);
3293 }
3294
3295 static void pnv_pci_enable_bridges(void)
3296 {
3297         struct pci_controller *hose;
3298
3299         list_for_each_entry(hose, &hose_list, list_node)
3300                 pnv_pci_enable_bridge(hose->bus);
3301 }
3302
3303 static void pnv_pci_ioda_fixup(void)
3304 {
3305         pnv_pci_ioda_setup_PEs();
3306         pnv_pci_ioda_setup_iommu_api();
3307         pnv_pci_ioda_create_dbgfs();
3308
3309         pnv_pci_enable_bridges();
3310
3311 #ifdef CONFIG_EEH
3312         pnv_eeh_post_init();
3313 #endif
3314 }
3315
3316 /*
3317  * Returns the alignment for I/O or memory windows for P2P
3318  * bridges. That actually depends on how PEs are segmented.
3319  * For now, we return I/O or M32 segment size for PE sensitive
3320  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3321  * 1MiB for memory) will be returned.
3322  *
3323  * The current PCI bus might be put into one PE, which was
3324  * create against the parent PCI bridge. For that case, we
3325  * needn't enlarge the alignment so that we can save some
3326  * resources.
3327  */
3328 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3329                                                 unsigned long type)
3330 {
3331         struct pci_dev *bridge;
3332         struct pci_controller *hose = pci_bus_to_host(bus);
3333         struct pnv_phb *phb = hose->private_data;
3334         int num_pci_bridges = 0;
3335
3336         bridge = bus->self;
3337         while (bridge) {
3338                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3339                         num_pci_bridges++;
3340                         if (num_pci_bridges >= 2)
3341                                 return 1;
3342                 }
3343
3344                 bridge = bridge->bus->self;
3345         }
3346
3347         /*
3348          * We fall back to M32 if M64 isn't supported. We enforce the M64
3349          * alignment for any 64-bit resource, PCIe doesn't care and
3350          * bridges only do 64-bit prefetchable anyway.
3351          */
3352         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3353                 return phb->ioda.m64_segsize;
3354         if (type & IORESOURCE_MEM)
3355                 return phb->ioda.m32_segsize;
3356
3357         return phb->ioda.io_segsize;
3358 }
3359
3360 /*
3361  * We are updating root port or the upstream port of the
3362  * bridge behind the root port with PHB's windows in order
3363  * to accommodate the changes on required resources during
3364  * PCI (slot) hotplug, which is connected to either root
3365  * port or the downstream ports of PCIe switch behind the
3366  * root port.
3367  */
3368 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3369                                            unsigned long type)
3370 {
3371         struct pci_controller *hose = pci_bus_to_host(bus);
3372         struct pnv_phb *phb = hose->private_data;
3373         struct pci_dev *bridge = bus->self;
3374         struct resource *r, *w;
3375         bool msi_region = false;
3376         int i;
3377
3378         /* Check if we need apply fixup to the bridge's windows */
3379         if (!pci_is_root_bus(bridge->bus) &&
3380             !pci_is_root_bus(bridge->bus->self->bus))
3381                 return;
3382
3383         /* Fixup the resources */
3384         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3385                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3386                 if (!r->flags || !r->parent)
3387                         continue;
3388
3389                 w = NULL;
3390                 if (r->flags & type & IORESOURCE_IO)
3391                         w = &hose->io_resource;
3392                 else if (pnv_pci_is_m64(phb, r) &&
3393                          (type & IORESOURCE_PREFETCH) &&
3394                          phb->ioda.m64_segsize)
3395                         w = &hose->mem_resources[1];
3396                 else if (r->flags & type & IORESOURCE_MEM) {
3397                         w = &hose->mem_resources[0];
3398                         msi_region = true;
3399                 }
3400
3401                 r->start = w->start;
3402                 r->end = w->end;
3403
3404                 /* The 64KB 32-bits MSI region shouldn't be included in
3405                  * the 32-bits bridge window. Otherwise, we can see strange
3406                  * issues. One of them is EEH error observed on Garrison.
3407                  *
3408                  * Exclude top 1MB region which is the minimal alignment of
3409                  * 32-bits bridge window.
3410                  */
3411                 if (msi_region) {
3412                         r->end += 0x10000;
3413                         r->end -= 0x100000;
3414                 }
3415         }
3416 }
3417
3418 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3419 {
3420         struct pci_controller *hose = pci_bus_to_host(bus);
3421         struct pnv_phb *phb = hose->private_data;
3422         struct pci_dev *bridge = bus->self;
3423         struct pnv_ioda_pe *pe;
3424         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3425
3426         /* Extend bridge's windows if necessary */
3427         pnv_pci_fixup_bridge_resources(bus, type);
3428
3429         /* The PE for root bus should be realized before any one else */
3430         if (!phb->ioda.root_pe_populated) {
3431                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3432                 if (pe) {
3433                         phb->ioda.root_pe_idx = pe->pe_number;
3434                         phb->ioda.root_pe_populated = true;
3435                 }
3436         }
3437
3438         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3439         if (list_empty(&bus->devices))
3440                 return;
3441
3442         /* Reserve PEs according to used M64 resources */
3443         if (phb->reserve_m64_pe)
3444                 phb->reserve_m64_pe(bus, NULL, all);
3445
3446         /*
3447          * Assign PE. We might run here because of partial hotplug.
3448          * For the case, we just pick up the existing PE and should
3449          * not allocate resources again.
3450          */
3451         pe = pnv_ioda_setup_bus_PE(bus, all);
3452         if (!pe)
3453                 return;
3454
3455         pnv_ioda_setup_pe_seg(pe);
3456         switch (phb->type) {
3457         case PNV_PHB_IODA1:
3458                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3459                 break;
3460         case PNV_PHB_IODA2:
3461                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3462                 break;
3463         default:
3464                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3465                         __func__, phb->hose->global_number, phb->type);
3466         }
3467 }
3468
3469 static resource_size_t pnv_pci_default_alignment(void)
3470 {
3471         return PAGE_SIZE;
3472 }
3473
3474 #ifdef CONFIG_PCI_IOV
3475 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3476                                                       int resno)
3477 {
3478         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3479         struct pnv_phb *phb = hose->private_data;
3480         struct pci_dn *pdn = pci_get_pdn(pdev);
3481         resource_size_t align;
3482
3483         /*
3484          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3485          * SR-IOV. While from hardware perspective, the range mapped by M64
3486          * BAR should be size aligned.
3487          *
3488          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3489          * powernv-specific hardware restriction is gone. But if just use the
3490          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3491          * in one segment of M64 #15, which introduces the PE conflict between
3492          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3493          * m64_segsize.
3494          *
3495          * This function returns the total IOV BAR size if M64 BAR is in
3496          * Shared PE mode or just VF BAR size if not.
3497          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3498          * M64 segment size if IOV BAR size is less.
3499          */
3500         align = pci_iov_resource_size(pdev, resno);
3501         if (!pdn->vfs_expanded)
3502                 return align;
3503         if (pdn->m64_single_mode)
3504                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3505
3506         return pdn->vfs_expanded * align;
3507 }
3508 #endif /* CONFIG_PCI_IOV */
3509
3510 /* Prevent enabling devices for which we couldn't properly
3511  * assign a PE
3512  */
3513 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3514 {
3515         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3516         struct pnv_phb *phb = hose->private_data;
3517         struct pci_dn *pdn;
3518
3519         /* The function is probably called while the PEs have
3520          * not be created yet. For example, resource reassignment
3521          * during PCI probe period. We just skip the check if
3522          * PEs isn't ready.
3523          */
3524         if (!phb->initialized)
3525                 return true;
3526
3527         pdn = pci_get_pdn(dev);
3528         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3529                 return false;
3530
3531         return true;
3532 }
3533
3534 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3535                                        int num)
3536 {
3537         struct pnv_ioda_pe *pe = container_of(table_group,
3538                                               struct pnv_ioda_pe, table_group);
3539         struct pnv_phb *phb = pe->phb;
3540         unsigned int idx;
3541         long rc;
3542
3543         pe_info(pe, "Removing DMA window #%d\n", num);
3544         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3545                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3546                         continue;
3547
3548                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3549                                                 idx, 0, 0ul, 0ul, 0ul);
3550                 if (rc != OPAL_SUCCESS) {
3551                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3552                                 rc, idx);
3553                         return rc;
3554                 }
3555
3556                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3557         }
3558
3559         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3560         return OPAL_SUCCESS;
3561 }
3562
3563 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3564 {
3565         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3566         struct iommu_table *tbl = pe->table_group.tables[0];
3567         int64_t rc;
3568
3569         if (!weight)
3570                 return;
3571
3572         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3573         if (rc != OPAL_SUCCESS)
3574                 return;
3575
3576         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3577         if (pe->table_group.group) {
3578                 iommu_group_put(pe->table_group.group);
3579                 WARN_ON(pe->table_group.group);
3580         }
3581
3582         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3583         iommu_tce_table_put(tbl);
3584 }
3585
3586 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3587 {
3588         struct iommu_table *tbl = pe->table_group.tables[0];
3589         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3590 #ifdef CONFIG_IOMMU_API
3591         int64_t rc;
3592 #endif
3593
3594         if (!weight)
3595                 return;
3596
3597 #ifdef CONFIG_IOMMU_API
3598         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3599         if (rc)
3600                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3601 #endif
3602
3603         pnv_pci_ioda2_set_bypass(pe, false);
3604         if (pe->table_group.group) {
3605                 iommu_group_put(pe->table_group.group);
3606                 WARN_ON(pe->table_group.group);
3607         }
3608
3609         iommu_tce_table_put(tbl);
3610 }
3611
3612 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3613                                  unsigned short win,
3614                                  unsigned int *map)
3615 {
3616         struct pnv_phb *phb = pe->phb;
3617         int idx;
3618         int64_t rc;
3619
3620         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3621                 if (map[idx] != pe->pe_number)
3622                         continue;
3623
3624                 if (win == OPAL_M64_WINDOW_TYPE)
3625                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3626                                         phb->ioda.reserved_pe_idx, win,
3627                                         idx / PNV_IODA1_M64_SEGS,
3628                                         idx % PNV_IODA1_M64_SEGS);
3629                 else
3630                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3631                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3632
3633                 if (rc != OPAL_SUCCESS)
3634                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3635                                 rc, win, idx);
3636
3637                 map[idx] = IODA_INVALID_PE;
3638         }
3639 }
3640
3641 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3642 {
3643         struct pnv_phb *phb = pe->phb;
3644
3645         if (phb->type == PNV_PHB_IODA1) {
3646                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3647                                      phb->ioda.io_segmap);
3648                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3649                                      phb->ioda.m32_segmap);
3650                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3651                                      phb->ioda.m64_segmap);
3652         } else if (phb->type == PNV_PHB_IODA2) {
3653                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3654                                      phb->ioda.m32_segmap);
3655         }
3656 }
3657
3658 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3659 {
3660         struct pnv_phb *phb = pe->phb;
3661         struct pnv_ioda_pe *slave, *tmp;
3662
3663         list_del(&pe->list);
3664         switch (phb->type) {
3665         case PNV_PHB_IODA1:
3666                 pnv_pci_ioda1_release_pe_dma(pe);
3667                 break;
3668         case PNV_PHB_IODA2:
3669                 pnv_pci_ioda2_release_pe_dma(pe);
3670                 break;
3671         default:
3672                 WARN_ON(1);
3673         }
3674
3675         pnv_ioda_release_pe_seg(pe);
3676         pnv_ioda_deconfigure_pe(pe->phb, pe);
3677
3678         /* Release slave PEs in the compound PE */
3679         if (pe->flags & PNV_IODA_PE_MASTER) {
3680                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3681                         list_del(&slave->list);
3682                         pnv_ioda_free_pe(slave);
3683                 }
3684         }
3685
3686         /*
3687          * The PE for root bus can be removed because of hotplug in EEH
3688          * recovery for fenced PHB error. We need to mark the PE dead so
3689          * that it can be populated again in PCI hot add path. The PE
3690          * shouldn't be destroyed as it's the global reserved resource.
3691          */
3692         if (phb->ioda.root_pe_populated &&
3693             phb->ioda.root_pe_idx == pe->pe_number)
3694                 phb->ioda.root_pe_populated = false;
3695         else
3696                 pnv_ioda_free_pe(pe);
3697 }
3698
3699 static void pnv_pci_release_device(struct pci_dev *pdev)
3700 {
3701         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3702         struct pnv_phb *phb = hose->private_data;
3703         struct pci_dn *pdn = pci_get_pdn(pdev);
3704         struct pnv_ioda_pe *pe;
3705
3706         if (pdev->is_virtfn)
3707                 return;
3708
3709         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3710                 return;
3711
3712         /*
3713          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3714          * isn't removed and added afterwards in this scenario. We should
3715          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3716          * device count is decreased on removing devices while failing to
3717          * be increased on adding devices. It leads to unbalanced PE's device
3718          * count and eventually make normal PCI hotplug path broken.
3719          */
3720         pe = &phb->ioda.pe_array[pdn->pe_number];
3721         pdn->pe_number = IODA_INVALID_PE;
3722
3723         WARN_ON(--pe->device_count < 0);
3724         if (pe->device_count == 0)
3725                 pnv_ioda_release_pe(pe);
3726 }
3727
3728 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3729 {
3730         struct pnv_phb *phb = hose->private_data;
3731
3732         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3733                        OPAL_ASSERT_RESET);
3734 }
3735
3736 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3737         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3738         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3739 #ifdef CONFIG_PCI_MSI
3740         .setup_msi_irqs         = pnv_setup_msi_irqs,
3741         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3742 #endif
3743         .enable_device_hook     = pnv_pci_enable_device_hook,
3744         .release_device         = pnv_pci_release_device,
3745         .window_alignment       = pnv_pci_window_alignment,
3746         .setup_bridge           = pnv_pci_setup_bridge,
3747         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3748         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3749         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3750         .shutdown               = pnv_pci_ioda_shutdown,
3751 };
3752
3753 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3754 {
3755         dev_err_once(&npdev->dev,
3756                         "%s operation unsupported for NVLink devices\n",
3757                         __func__);
3758         return -EPERM;
3759 }
3760
3761 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3762         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3763 #ifdef CONFIG_PCI_MSI
3764         .setup_msi_irqs         = pnv_setup_msi_irqs,
3765         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3766 #endif
3767         .enable_device_hook     = pnv_pci_enable_device_hook,
3768         .window_alignment       = pnv_pci_window_alignment,
3769         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3770         .dma_set_mask           = pnv_npu_dma_set_mask,
3771         .shutdown               = pnv_pci_ioda_shutdown,
3772 };
3773
3774 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3775         .enable_device_hook     = pnv_pci_enable_device_hook,
3776         .window_alignment       = pnv_pci_window_alignment,
3777         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3778         .shutdown               = pnv_pci_ioda_shutdown,
3779 };
3780
3781 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3782                                          u64 hub_id, int ioda_type)
3783 {
3784         struct pci_controller *hose;
3785         struct pnv_phb *phb;
3786         unsigned long size, m64map_off, m32map_off, pemap_off;
3787         unsigned long iomap_off = 0, dma32map_off = 0;
3788         struct resource r;
3789         const __be64 *prop64;
3790         const __be32 *prop32;
3791         int len;
3792         unsigned int segno;
3793         u64 phb_id;
3794         void *aux;
3795         long rc;
3796
3797         if (!of_device_is_available(np))
3798                 return;
3799
3800         pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3801
3802         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3803         if (!prop64) {
3804                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3805                 return;
3806         }
3807         phb_id = be64_to_cpup(prop64);
3808         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3809
3810         phb = memblock_virt_alloc(sizeof(*phb), 0);
3811
3812         /* Allocate PCI controller */
3813         phb->hose = hose = pcibios_alloc_controller(np);
3814         if (!phb->hose) {
3815                 pr_err("  Can't allocate PCI controller for %pOF\n",
3816                        np);
3817                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3818                 return;
3819         }
3820
3821         spin_lock_init(&phb->lock);
3822         prop32 = of_get_property(np, "bus-range", &len);
3823         if (prop32 && len == 8) {
3824                 hose->first_busno = be32_to_cpu(prop32[0]);
3825                 hose->last_busno = be32_to_cpu(prop32[1]);
3826         } else {
3827                 pr_warn("  Broken <bus-range> on %pOF\n", np);
3828                 hose->first_busno = 0;
3829                 hose->last_busno = 0xff;
3830         }
3831         hose->private_data = phb;
3832         phb->hub_id = hub_id;
3833         phb->opal_id = phb_id;
3834         phb->type = ioda_type;
3835         mutex_init(&phb->ioda.pe_alloc_mutex);
3836
3837         /* Detect specific models for error handling */
3838         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3839                 phb->model = PNV_PHB_MODEL_P7IOC;
3840         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3841                 phb->model = PNV_PHB_MODEL_PHB3;
3842         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3843                 phb->model = PNV_PHB_MODEL_NPU;
3844         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3845                 phb->model = PNV_PHB_MODEL_NPU2;
3846         else
3847                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3848
3849         /* Initialize diagnostic data buffer */
3850         prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3851         if (prop32)
3852                 phb->diag_data_size = be32_to_cpup(prop32);
3853         else
3854                 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3855
3856         phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0);
3857
3858         /* Parse 32-bit and IO ranges (if any) */
3859         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3860
3861         /* Get registers */
3862         if (!of_address_to_resource(np, 0, &r)) {
3863                 phb->regs_phys = r.start;
3864                 phb->regs = ioremap(r.start, resource_size(&r));
3865                 if (phb->regs == NULL)
3866                         pr_err("  Failed to map registers !\n");
3867         }
3868
3869         /* Initialize more IODA stuff */
3870         phb->ioda.total_pe_num = 1;
3871         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3872         if (prop32)
3873                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3874         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3875         if (prop32)
3876                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3877
3878         /* Invalidate RID to PE# mapping */
3879         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3880                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3881
3882         /* Parse 64-bit MMIO range */
3883         pnv_ioda_parse_m64_window(phb);
3884
3885         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3886         /* FW Has already off top 64k of M32 space (MSI space) */
3887         phb->ioda.m32_size += 0x10000;
3888
3889         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3890         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3891         phb->ioda.io_size = hose->pci_io_size;
3892         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3893         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3894
3895         /* Calculate how many 32-bit TCE segments we have */
3896         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3897                                 PNV_IODA1_DMA32_SEGSIZE;
3898
3899         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3900         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3901                         sizeof(unsigned long));
3902         m64map_off = size;
3903         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3904         m32map_off = size;
3905         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3906         if (phb->type == PNV_PHB_IODA1) {
3907                 iomap_off = size;
3908                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3909                 dma32map_off = size;
3910                 size += phb->ioda.dma32_count *
3911                         sizeof(phb->ioda.dma32_segmap[0]);
3912         }
3913         pemap_off = size;
3914         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3915         aux = memblock_virt_alloc(size, 0);
3916         phb->ioda.pe_alloc = aux;
3917         phb->ioda.m64_segmap = aux + m64map_off;
3918         phb->ioda.m32_segmap = aux + m32map_off;
3919         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3920                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3921                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3922         }
3923         if (phb->type == PNV_PHB_IODA1) {
3924                 phb->ioda.io_segmap = aux + iomap_off;
3925                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3926                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3927
3928                 phb->ioda.dma32_segmap = aux + dma32map_off;
3929                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3930                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3931         }
3932         phb->ioda.pe_array = aux + pemap_off;
3933
3934         /*
3935          * Choose PE number for root bus, which shouldn't have
3936          * M64 resources consumed by its child devices. To pick
3937          * the PE number adjacent to the reserved one if possible.
3938          */
3939         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3940         if (phb->ioda.reserved_pe_idx == 0) {
3941                 phb->ioda.root_pe_idx = 1;
3942                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3943         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3944                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3945                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3946         } else {
3947                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3948         }
3949
3950         INIT_LIST_HEAD(&phb->ioda.pe_list);
3951         mutex_init(&phb->ioda.pe_list_mutex);
3952
3953         /* Calculate how many 32-bit TCE segments we have */
3954         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3955                                 PNV_IODA1_DMA32_SEGSIZE;
3956
3957 #if 0 /* We should really do that ... */
3958         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3959                                          window_type,
3960                                          window_num,
3961                                          starting_real_address,
3962                                          starting_pci_address,
3963                                          segment_size);
3964 #endif
3965
3966         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3967                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3968                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3969         if (phb->ioda.m64_size)
3970                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3971                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3972         if (phb->ioda.io_size)
3973                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3974                         phb->ioda.io_size, phb->ioda.io_segsize);
3975
3976
3977         phb->hose->ops = &pnv_pci_ops;
3978         phb->get_pe_state = pnv_ioda_get_pe_state;
3979         phb->freeze_pe = pnv_ioda_freeze_pe;
3980         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3981
3982         /* Setup MSI support */
3983         pnv_pci_init_ioda_msis(phb);
3984
3985         /*
3986          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3987          * to let the PCI core do resource assignment. It's supposed
3988          * that the PCI core will do correct I/O and MMIO alignment
3989          * for the P2P bridge bars so that each PCI bus (excluding
3990          * the child P2P bridges) can form individual PE.
3991          */
3992         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3993
3994         switch (phb->type) {
3995         case PNV_PHB_NPU_NVLINK:
3996                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3997                 break;
3998         case PNV_PHB_NPU_OCAPI:
3999                 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
4000                 break;
4001         default:
4002                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
4003                 hose->controller_ops = pnv_pci_ioda_controller_ops;
4004         }
4005
4006         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
4007
4008 #ifdef CONFIG_PCI_IOV
4009         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
4010         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
4011         ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
4012         ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
4013 #endif
4014
4015         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
4016
4017         /* Reset IODA tables to a clean state */
4018         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
4019         if (rc)
4020                 pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
4021
4022         /*
4023          * If we're running in kdump kernel, the previous kernel never
4024          * shutdown PCI devices correctly. We already got IODA table
4025          * cleaned out. So we have to issue PHB reset to stop all PCI
4026          * transactions from previous kernel. The ppc_pci_reset_phbs
4027          * kernel parameter will force this reset too.
4028          */
4029         if (is_kdump_kernel() || pci_reset_phbs) {
4030                 pr_info("  Issue PHB reset ...\n");
4031                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
4032                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
4033         }
4034
4035         /* Remove M64 resource if we can't configure it successfully */
4036         if (!phb->init_m64 || phb->init_m64(phb))
4037                 hose->mem_resources[1].flags = 0;
4038 }
4039
4040 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4041 {
4042         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4043 }
4044
4045 void __init pnv_pci_init_npu_phb(struct device_node *np)
4046 {
4047         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
4048 }
4049
4050 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
4051 {
4052         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
4053 }
4054
4055 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
4056 {
4057         struct pci_controller *hose = pci_bus_to_host(dev->bus);
4058         struct pnv_phb *phb = hose->private_data;
4059
4060         if (!machine_is(powernv))
4061                 return;
4062
4063         if (phb->type == PNV_PHB_NPU_OCAPI)
4064                 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4065 }
4066 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
4067
4068 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4069 {
4070         struct device_node *phbn;
4071         const __be64 *prop64;
4072         u64 hub_id;
4073
4074         pr_info("Probing IODA IO-Hub %pOF\n", np);
4075
4076         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4077         if (!prop64) {
4078                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4079                 return;
4080         }
4081         hub_id = be64_to_cpup(prop64);
4082         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4083
4084         /* Count child PHBs */
4085         for_each_child_of_node(np, phbn) {
4086                 /* Look for IODA1 PHBs */
4087                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4088                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4089         }
4090 }