arch/powerpc/platforms/powernv/pci-ioda.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Support PCI/PCIe on PowerNV platforms
   4  *
   5  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   6  */
   7
   8 #undef DEBUG
   9
  10 #include <linux/kernel.h>
  11 #include <linux/pci.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/delay.h>
  14 #include <linux/string.h>
  15 #include <linux/init.h>
  16 #include <linux/memblock.h>
  17 #include <linux/irq.h>
  18 #include <linux/io.h>
  19 #include <linux/msi.h>
  20 #include <linux/iommu.h>
  21 #include <linux/rculist.h>
  22 #include <linux/sizes.h>
  23
  24 #include <asm/sections.h>
  25 #include <asm/io.h>
  26 #include <asm/prom.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/machdep.h>
  29 #include <asm/msi_bitmap.h>
  30 #include <asm/ppc-pci.h>
  31 #include <asm/opal.h>
  32 #include <asm/iommu.h>
  33 #include <asm/tce.h>
  34 #include <asm/xics.h>
  35 #include <asm/debugfs.h>
  36 #include <asm/firmware.h>
  37 #include <asm/pnv-pci.h>
  38 #include <asm/mmzone.h>
  39
  40 #include <misc/cxl-base.h>
  41
  42 #include "powernv.h"
  43 #include "pci.h"
  44 #include "../../../../drivers/pci/pci.h"
  45
  46 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  47 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  48 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  49
  50 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
  51                                               "NPU_OCAPI" };
  52
  53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
  54
  55 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  56                             const char *fmt, ...)
  57 {
  58         struct va_format vaf;
  59         va_list args;
  60         char pfix[32];
  61
  62         va_start(args, fmt);
  63
  64         vaf.fmt = fmt;
  65         vaf.va = &args;
  66
  67         if (pe->flags & PNV_IODA_PE_DEV)
  68                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  69         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  70                 sprintf(pfix, "%04x:%02x     ",
  71                         pci_domain_nr(pe->pbus), pe->pbus->number);
  72 #ifdef CONFIG_PCI_IOV
  73         else if (pe->flags & PNV_IODA_PE_VF)
  74                 sprintf(pfix, "%04x:%02x:%2x.%d",
  75                         pci_domain_nr(pe->parent_dev->bus),
  76                         (pe->rid & 0xff00) >> 8,
  77                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  78 #endif /* CONFIG_PCI_IOV*/
  79
  80         printk("%spci %s: [PE# %.2x] %pV",
  81                level, pfix, pe->pe_number, &vaf);
  82
  83         va_end(args);
  84 }
  85
  86 static bool pnv_iommu_bypass_disabled __read_mostly;
  87 static bool pci_reset_phbs __read_mostly;
  88
  89 static int __init iommu_setup(char *str)
  90 {
  91         if (!str)
  92                 return -EINVAL;
  93
  94         while (*str) {
  95                 if (!strncmp(str, "nobypass", 8)) {
  96                         pnv_iommu_bypass_disabled = true;
  97                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
  98                         break;
  99                 }
 100                 str += strcspn(str, ",");
 101                 if (*str == ',')
 102                         str++;
 103         }
 104
 105         return 0;
 106 }
 107 early_param("iommu", iommu_setup);
 108
 109 static int __init pci_reset_phbs_setup(char *str)
 110 {
 111         pci_reset_phbs = true;
 112         return 0;
 113 }
 114
 115 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
 116
 117 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 118 {
 119         /*
 120          * WARNING: We cannot rely on the resource flags. The Linux PCI
 121          * allocation code sometimes decides to put a 64-bit prefetchable
 122          * BAR in the 32-bit window, so we have to compare the addresses.
 123          *
 124          * For simplicity we only test resource start.
 125          */
 126         return (r->start >= phb->ioda.m64_base &&
 127                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 128 }
 129
 130 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 131 {
 132         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 133
 134         return (resource_flags & flags) == flags;
 135 }
 136
 137 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 138 {
 139         s64 rc;
 140
 141         phb->ioda.pe_array[pe_no].phb = phb;
 142         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 143
 144         /*
 145          * Clear the PE frozen state as it might be put into frozen state
 146          * in the last PCI remove path. It's not harmful to do so when the
 147          * PE is already in unfrozen state.
 148          */
 149         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 150                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 151         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 152                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 153                         __func__, rc, phb->hose->global_number, pe_no);
 154
 155         return &phb->ioda.pe_array[pe_no];
 156 }
 157
 158 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 159 {
 160         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 161                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 162                         __func__, pe_no, phb->hose->global_number);
 163                 return;
 164         }
 165
 166         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 167                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 168                          __func__, pe_no, phb->hose->global_number);
 169
 170         pnv_ioda_init_pe(phb, pe_no);
 171 }
 172
 173 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 174 {
 175         long pe;
 176
 177         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 178                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 179                         return pnv_ioda_init_pe(phb, pe);
 180         }
 181
 182         return NULL;
 183 }
 184
 185 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 186 {
 187         struct pnv_phb *phb = pe->phb;
 188         unsigned int pe_num = pe->pe_number;
 189
 190         WARN_ON(pe->pdev);
 191         WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
 192         kfree(pe->npucomp);
 193         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 194         clear_bit(pe_num, phb->ioda.pe_alloc);
 195 }
 196
 197 /* The default M64 BAR is shared by all PEs */
 198 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 199 {
 200         const char *desc;
 201         struct resource *r;
 202         s64 rc;
 203
 204         /* Configure the default M64 BAR */
 205         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 206                                          OPAL_M64_WINDOW_TYPE,
 207                                          phb->ioda.m64_bar_idx,
 208                                          phb->ioda.m64_base,
 209                                          0, /* unused */
 210                                          phb->ioda.m64_size);
 211         if (rc != OPAL_SUCCESS) {
 212                 desc = "configuring";
 213                 goto fail;
 214         }
 215
 216         /* Enable the default M64 BAR */
 217         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 218                                       OPAL_M64_WINDOW_TYPE,
 219                                       phb->ioda.m64_bar_idx,
 220                                       OPAL_ENABLE_M64_SPLIT);
 221         if (rc != OPAL_SUCCESS) {
 222                 desc = "enabling";
 223                 goto fail;
 224         }
 225
 226         /*
 227          * Exclude the segments for reserved and root bus PE, which
 228          * are first or last two PEs.
 229          */
 230         r = &phb->hose->mem_resources[1];
 231         if (phb->ioda.reserved_pe_idx == 0)
 232                 r->start += (2 * phb->ioda.m64_segsize);
 233         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 234                 r->end -= (2 * phb->ioda.m64_segsize);
 235         else
 236                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 237                         phb->ioda.reserved_pe_idx);
 238
 239         return 0;
 240
 241 fail:
 242         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 243                 rc, desc, phb->ioda.m64_bar_idx);
 244         opal_pci_phb_mmio_enable(phb->opal_id,
 245                                  OPAL_M64_WINDOW_TYPE,
 246                                  phb->ioda.m64_bar_idx,
 247                                  OPAL_DISABLE_M64);
 248         return -EIO;
 249 }
 250
 251 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 252                                          unsigned long *pe_bitmap)
 253 {
 254         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 255         struct pnv_phb *phb = hose->private_data;
 256         struct resource *r;
 257         resource_size_t base, sgsz, start, end;
 258         int segno, i;
 259
 260         base = phb->ioda.m64_base;
 261         sgsz = phb->ioda.m64_segsize;
 262         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 263                 r = &pdev->resource[i];
 264                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 265                         continue;
 266
 267                 start = _ALIGN_DOWN(r->start - base, sgsz);
 268                 end = _ALIGN_UP(r->end - base, sgsz);
 269                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 270                         if (pe_bitmap)
 271                                 set_bit(segno, pe_bitmap);
 272                         else
 273                                 pnv_ioda_reserve_pe(phb, segno);
 274                 }
 275         }
 276 }
 277
 278 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 279 {
 280         struct resource *r;
 281         int index;
 282
 283         /*
 284          * There are 16 M64 BARs, each of which has 8 segments. So
 285          * there are as many M64 segments as the maximum number of
 286          * PEs, which is 128.
 287          */
 288         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 289                 unsigned long base, segsz = phb->ioda.m64_segsize;
 290                 int64_t rc;
 291
 292                 base = phb->ioda.m64_base +
 293                        index * PNV_IODA1_M64_SEGS * segsz;
 294                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 295                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 296                                 PNV_IODA1_M64_SEGS * segsz);
 297                 if (rc != OPAL_SUCCESS) {
 298                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 299                                 rc, phb->hose->global_number, index);
 300                         goto fail;
 301                 }
 302
 303                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 304                                 OPAL_M64_WINDOW_TYPE, index,
 305                                 OPAL_ENABLE_M64_SPLIT);
 306                 if (rc != OPAL_SUCCESS) {
 307                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 308                                 rc, phb->hose->global_number, index);
 309                         goto fail;
 310                 }
 311         }
 312
 313         /*
 314          * Exclude the segments for reserved and root bus PE, which
 315          * are first or last two PEs.
 316          */
 317         r = &phb->hose->mem_resources[1];
 318         if (phb->ioda.reserved_pe_idx == 0)
 319                 r->start += (2 * phb->ioda.m64_segsize);
 320         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 321                 r->end -= (2 * phb->ioda.m64_segsize);
 322         else
 323                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 324                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 325
 326         return 0;
 327
 328 fail:
 329         for ( ; index >= 0; index--)
 330                 opal_pci_phb_mmio_enable(phb->opal_id,
 331                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 332
 333         return -EIO;
 334 }
 335
 336 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 337                                     unsigned long *pe_bitmap,
 338                                     bool all)
 339 {
 340         struct pci_dev *pdev;
 341
 342         list_for_each_entry(pdev, &bus->devices, bus_list) {
 343                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 344
 345                 if (all && pdev->subordinate)
 346                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 347                                                 pe_bitmap, all);
 348         }
 349 }
 350
 351 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 352 {
 353         struct pci_controller *hose = pci_bus_to_host(bus);
 354         struct pnv_phb *phb = hose->private_data;
 355         struct pnv_ioda_pe *master_pe, *pe;
 356         unsigned long size, *pe_alloc;
 357         int i;
 358
 359         /* Root bus shouldn't use M64 */
 360         if (pci_is_root_bus(bus))
 361                 return NULL;
 362
 363         /* Allocate bitmap */
 364         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 365         pe_alloc = kzalloc(size, GFP_KERNEL);
 366         if (!pe_alloc) {
 367                 pr_warn("%s: Out of memory !\n",
 368                         __func__);
 369                 return NULL;
 370         }
 371
 372         /* Figure out reserved PE numbers by the PE */
 373         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 374
 375         /*
 376          * the current bus might not own M64 window and that's all
 377          * contributed by its child buses. For the case, we needn't
 378          * pick M64 dependent PE#.
 379          */
 380         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 381                 kfree(pe_alloc);
 382                 return NULL;
 383         }
 384
 385         /*
 386          * Figure out the master PE and put all slave PEs to master
 387          * PE's list to form compound PE.
 388          */
 389         master_pe = NULL;
 390         i = -1;
 391         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 392                 phb->ioda.total_pe_num) {
 393                 pe = &phb->ioda.pe_array[i];
 394
 395                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 396                 if (!master_pe) {
 397                         pe->flags |= PNV_IODA_PE_MASTER;
 398                         INIT_LIST_HEAD(&pe->slaves);
 399                         master_pe = pe;
 400                 } else {
 401                         pe->flags |= PNV_IODA_PE_SLAVE;
 402                         pe->master = master_pe;
 403                         list_add_tail(&pe->list, &master_pe->slaves);
 404                 }
 405
 406                 /*
 407                  * P7IOC supports M64DT, which helps mapping M64 segment
 408                  * to one particular PE#. However, PHB3 has fixed mapping
 409                  * between M64 segment and PE#. In order to have same logic
 410                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 411                  * segment and PE# on P7IOC.
 412                  */
 413                 if (phb->type == PNV_PHB_IODA1) {
 414                         int64_t rc;
 415
 416                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 417                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 418                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 419                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 420                         if (rc != OPAL_SUCCESS)
 421                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 422                                         __func__, rc, phb->hose->global_number,
 423                                         pe->pe_number);
 424                 }
 425         }
 426
 427         kfree(pe_alloc);
 428         return master_pe;
 429 }
 430
 431 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 432 {
 433         struct pci_controller *hose = phb->hose;
 434         struct device_node *dn = hose->dn;
 435         struct resource *res;
 436         u32 m64_range[2], i;
 437         const __be32 *r;
 438         u64 pci_addr;
 439
 440         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 441                 pr_info("  Not support M64 window\n");
 442                 return;
 443         }
 444
 445         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 446                 pr_info("  Firmware too old to support M64 window\n");
 447                 return;
 448         }
 449
 450         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 451         if (!r) {
 452                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 453                         dn);
 454                 return;
 455         }
 456
 457         /*
 458          * Find the available M64 BAR range and pickup the last one for
 459          * covering the whole 64-bits space. We support only one range.
 460          */
 461         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 462                                        m64_range, 2)) {
 463                 /* In absence of the property, assume 0..15 */
 464                 m64_range[0] = 0;
 465                 m64_range[1] = 16;
 466         }
 467         /* We only support 64 bits in our allocator */
 468         if (m64_range[1] > 63) {
 469                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 470                         __func__, m64_range[1], phb->hose->global_number);
 471                 m64_range[1] = 63;
 472         }
 473         /* Empty range, no m64 */
 474         if (m64_range[1] <= m64_range[0]) {
 475                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 476                         __func__, phb->hose->global_number);
 477                 return;
 478         }
 479
 480         /* Configure M64 informations */
 481         res = &hose->mem_resources[1];
 482         res->name = dn->full_name;
 483         res->start = of_translate_address(dn, r + 2);
 484         res->end = res->start + of_read_number(r + 4, 2) - 1;
 485         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 486         pci_addr = of_read_number(r, 2);
 487         hose->mem_offset[1] = res->start - pci_addr;
 488
 489         phb->ioda.m64_size = resource_size(res);
 490         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 491         phb->ioda.m64_base = pci_addr;
 492
 493         /* This lines up nicely with the display from processing OF ranges */
 494         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 495                 res->start, res->end, pci_addr, m64_range[0],
 496                 m64_range[0] + m64_range[1] - 1);
 497
 498         /* Mark all M64 used up by default */
 499         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 500
 501         /* Use last M64 BAR to cover M64 window */
 502         m64_range[1]--;
 503         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 504
 505         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 506
 507         /* Mark remaining ones free */
 508         for (i = m64_range[0]; i < m64_range[1]; i++)
 509                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 510
 511         /*
 512          * Setup init functions for M64 based on IODA version, IODA3 uses
 513          * the IODA2 code.
 514          */
 515         if (phb->type == PNV_PHB_IODA1)
 516                 phb->init_m64 = pnv_ioda1_init_m64;
 517         else
 518                 phb->init_m64 = pnv_ioda2_init_m64;
 519 }
 520
 521 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 522 {
 523         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 524         struct pnv_ioda_pe *slave;
 525         s64 rc;
 526
 527         /* Fetch master PE */
 528         if (pe->flags & PNV_IODA_PE_SLAVE) {
 529                 pe = pe->master;
 530                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 531                         return;
 532
 533                 pe_no = pe->pe_number;
 534         }
 535
 536         /* Freeze master PE */
 537         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 538                                      pe_no,
 539                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 540         if (rc != OPAL_SUCCESS) {
 541                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 542                         __func__, rc, phb->hose->global_number, pe_no);
 543                 return;
 544         }
 545
 546         /* Freeze slave PEs */
 547         if (!(pe->flags & PNV_IODA_PE_MASTER))
 548                 return;
 549
 550         list_for_each_entry(slave, &pe->slaves, list) {
 551                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 552                                              slave->pe_number,
 553                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 554                 if (rc != OPAL_SUCCESS)
 555                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 556                                 __func__, rc, phb->hose->global_number,
 557                                 slave->pe_number);
 558         }
 559 }
 560
 561 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 562 {
 563         struct pnv_ioda_pe *pe, *slave;
 564         s64 rc;
 565
 566         /* Find master PE */
 567         pe = &phb->ioda.pe_array[pe_no];
 568         if (pe->flags & PNV_IODA_PE_SLAVE) {
 569                 pe = pe->master;
 570                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 571                 pe_no = pe->pe_number;
 572         }
 573
 574         /* Clear frozen state for master PE */
 575         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 576         if (rc != OPAL_SUCCESS) {
 577                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 578                         __func__, rc, opt, phb->hose->global_number, pe_no);
 579                 return -EIO;
 580         }
 581
 582         if (!(pe->flags & PNV_IODA_PE_MASTER))
 583                 return 0;
 584
 585         /* Clear frozen state for slave PEs */
 586         list_for_each_entry(slave, &pe->slaves, list) {
 587                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 588                                              slave->pe_number,
 589                                              opt);
 590                 if (rc != OPAL_SUCCESS) {
 591                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 592                                 __func__, rc, opt, phb->hose->global_number,
 593                                 slave->pe_number);
 594                         return -EIO;
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 602 {
 603         struct pnv_ioda_pe *slave, *pe;
 604         u8 fstate = 0, state;
 605         __be16 pcierr = 0;
 606         s64 rc;
 607
 608         /* Sanity check on PE number */
 609         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 610                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 611
 612         /*
 613          * Fetch the master PE and the PE instance might be
 614          * not initialized yet.
 615          */
 616         pe = &phb->ioda.pe_array[pe_no];
 617         if (pe->flags & PNV_IODA_PE_SLAVE) {
 618                 pe = pe->master;
 619                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 620                 pe_no = pe->pe_number;
 621         }
 622
 623         /* Check the master PE */
 624         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 625                                         &state, &pcierr, NULL);
 626         if (rc != OPAL_SUCCESS) {
 627                 pr_warn("%s: Failure %lld getting "
 628                         "PHB#%x-PE#%x state\n",
 629                         __func__, rc,
 630                         phb->hose->global_number, pe_no);
 631                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 632         }
 633
 634         /* Check the slave PE */
 635         if (!(pe->flags & PNV_IODA_PE_MASTER))
 636                 return state;
 637
 638         list_for_each_entry(slave, &pe->slaves, list) {
 639                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 640                                                 slave->pe_number,
 641                                                 &fstate,
 642                                                 &pcierr,
 643                                                 NULL);
 644                 if (rc != OPAL_SUCCESS) {
 645                         pr_warn("%s: Failure %lld getting "
 646                                 "PHB#%x-PE#%x state\n",
 647                                 __func__, rc,
 648                                 phb->hose->global_number, slave->pe_number);
 649                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 650                 }
 651
 652                 /*
 653                  * Override the result based on the ascending
 654                  * priority.
 655                  */
 656                 if (fstate > state)
 657                         state = fstate;
 658         }
 659
 660         return state;
 661 }
 662
 663 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 664 {
 665         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 666         struct pnv_phb *phb = hose->private_data;
 667         struct pci_dn *pdn = pci_get_pdn(dev);
 668
 669         if (!pdn)
 670                 return NULL;
 671         if (pdn->pe_number == IODA_INVALID_PE)
 672                 return NULL;
 673         return &phb->ioda.pe_array[pdn->pe_number];
 674 }
 675
 676 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 677                                   struct pnv_ioda_pe *parent,
 678                                   struct pnv_ioda_pe *child,
 679                                   bool is_add)
 680 {
 681         const char *desc = is_add ? "adding" : "removing";
 682         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 683                               OPAL_REMOVE_PE_FROM_DOMAIN;
 684         struct pnv_ioda_pe *slave;
 685         long rc;
 686
 687         /* Parent PE affects child PE */
 688         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 689                                 child->pe_number, op);
 690         if (rc != OPAL_SUCCESS) {
 691                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 692                         rc, desc);
 693                 return -ENXIO;
 694         }
 695
 696         if (!(child->flags & PNV_IODA_PE_MASTER))
 697                 return 0;
 698
 699         /* Compound case: parent PE affects slave PEs */
 700         list_for_each_entry(slave, &child->slaves, list) {
 701                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 702                                         slave->pe_number, op);
 703                 if (rc != OPAL_SUCCESS) {
 704                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 705                                 rc, desc);
 706                         return -ENXIO;
 707                 }
 708         }
 709
 710         return 0;
 711 }
 712
 713 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 714                               struct pnv_ioda_pe *pe,
 715                               bool is_add)
 716 {
 717         struct pnv_ioda_pe *slave;
 718         struct pci_dev *pdev = NULL;
 719         int ret;
 720
 721         /*
 722          * Clear PE frozen state. If it's master PE, we need
 723          * clear slave PE frozen state as well.
 724          */
 725         if (is_add) {
 726                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 727                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 728                 if (pe->flags & PNV_IODA_PE_MASTER) {
 729                         list_for_each_entry(slave, &pe->slaves, list)
 730                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 731                                                           slave->pe_number,
 732                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 733                 }
 734         }
 735
 736         /*
 737          * Associate PE in PELT. We need add the PE into the
 738          * corresponding PELT-V as well. Otherwise, the error
 739          * originated from the PE might contribute to other
 740          * PEs.
 741          */
 742         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 743         if (ret)
 744                 return ret;
 745
 746         /* For compound PEs, any one affects all of them */
 747         if (pe->flags & PNV_IODA_PE_MASTER) {
 748                 list_for_each_entry(slave, &pe->slaves, list) {
 749                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 750                         if (ret)
 751                                 return ret;
 752                 }
 753         }
 754
 755         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 756                 pdev = pe->pbus->self;
 757         else if (pe->flags & PNV_IODA_PE_DEV)
 758                 pdev = pe->pdev->bus->self;
 759 #ifdef CONFIG_PCI_IOV
 760         else if (pe->flags & PNV_IODA_PE_VF)
 761                 pdev = pe->parent_dev;
 762 #endif /* CONFIG_PCI_IOV */
 763         while (pdev) {
 764                 struct pci_dn *pdn = pci_get_pdn(pdev);
 765                 struct pnv_ioda_pe *parent;
 766
 767                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 768                         parent = &phb->ioda.pe_array[pdn->pe_number];
 769                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 770                         if (ret)
 771                                 return ret;
 772                 }
 773
 774                 pdev = pdev->bus->self;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 781 {
 782         struct pci_dev *parent;
 783         uint8_t bcomp, dcomp, fcomp;
 784         int64_t rc;
 785         long rid_end, rid;
 786
 787         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 788         if (pe->pbus) {
 789                 int count;
 790
 791                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 792                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 793                 parent = pe->pbus->self;
 794                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 795                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 796                 else
 797                         count = 1;
 798
 799                 switch(count) {
 800                 case  1: bcomp = OpalPciBusAll;         break;
 801                 case  2: bcomp = OpalPciBus7Bits;       break;
 802                 case  4: bcomp = OpalPciBus6Bits;       break;
 803                 case  8: bcomp = OpalPciBus5Bits;       break;
 804                 case 16: bcomp = OpalPciBus4Bits;       break;
 805                 case 32: bcomp = OpalPciBus3Bits;       break;
 806                 default:
 807                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 808                                 count);
 809                         /* Do an exact match only */
 810                         bcomp = OpalPciBusAll;
 811                 }
 812                 rid_end = pe->rid + (count << 8);
 813         } else {
 814 #ifdef CONFIG_PCI_IOV
 815                 if (pe->flags & PNV_IODA_PE_VF)
 816                         parent = pe->parent_dev;
 817                 else
 818 #endif
 819                         parent = pe->pdev->bus->self;
 820                 bcomp = OpalPciBusAll;
 821                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 822                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 823                 rid_end = pe->rid + 1;
 824         }
 825
 826         /* Clear the reverse map */
 827         for (rid = pe->rid; rid < rid_end; rid++)
 828                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 829
 830         /* Release from all parents PELT-V */
 831         while (parent) {
 832                 struct pci_dn *pdn = pci_get_pdn(parent);
 833                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 834                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 835                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 836                         /* XXX What to do in case of error ? */
 837                 }
 838                 parent = parent->bus->self;
 839         }
 840
 841         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 842                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 843
 844         /* Disassociate PE in PELT */
 845         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 846                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 847         if (rc)
 848                 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
 849         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 850                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 851         if (rc)
 852                 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
 853
 854         pe->pbus = NULL;
 855         pe->pdev = NULL;
 856 #ifdef CONFIG_PCI_IOV
 857         pe->parent_dev = NULL;
 858 #endif
 859
 860         return 0;
 861 }
 862
 863 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 864 {
 865         struct pci_dev *parent;
 866         uint8_t bcomp, dcomp, fcomp;
 867         long rc, rid_end, rid;
 868
 869         /* Bus validation ? */
 870         if (pe->pbus) {
 871                 int count;
 872
 873                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 874                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 875                 parent = pe->pbus->self;
 876                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 877                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 878                 else
 879                         count = 1;
 880
 881                 switch(count) {
 882                 case  1: bcomp = OpalPciBusAll;         break;
 883                 case  2: bcomp = OpalPciBus7Bits;       break;
 884                 case  4: bcomp = OpalPciBus6Bits;       break;
 885                 case  8: bcomp = OpalPciBus5Bits;       break;
 886                 case 16: bcomp = OpalPciBus4Bits;       break;
 887                 case 32: bcomp = OpalPciBus3Bits;       break;
 888                 default:
 889                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 890                                 count);
 891                         /* Do an exact match only */
 892                         bcomp = OpalPciBusAll;
 893                 }
 894                 rid_end = pe->rid + (count << 8);
 895         } else {
 896 #ifdef CONFIG_PCI_IOV
 897                 if (pe->flags & PNV_IODA_PE_VF)
 898                         parent = pe->parent_dev;
 899                 else
 900 #endif /* CONFIG_PCI_IOV */
 901                         parent = pe->pdev->bus->self;
 902                 bcomp = OpalPciBusAll;
 903                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 904                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 905                 rid_end = pe->rid + 1;
 906         }
 907
 908         /*
 909          * Associate PE in PELT. We need add the PE into the
 910          * corresponding PELT-V as well. Otherwise, the error
 911          * originated from the PE might contribute to other
 912          * PEs.
 913          */
 914         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 915                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 916         if (rc) {
 917                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 918                 return -ENXIO;
 919         }
 920
 921         /*
 922          * Configure PELTV. NPUs don't have a PELTV table so skip
 923          * configuration on them.
 924          */
 925         if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
 926                 pnv_ioda_set_peltv(phb, pe, true);
 927
 928         /* Setup reverse map */
 929         for (rid = pe->rid; rid < rid_end; rid++)
 930                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 931
 932         /* Setup one MVTs on IODA1 */
 933         if (phb->type != PNV_PHB_IODA1) {
 934                 pe->mve_number = 0;
 935                 goto out;
 936         }
 937
 938         pe->mve_number = pe->pe_number;
 939         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 940         if (rc != OPAL_SUCCESS) {
 941                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 942                        rc, pe->mve_number);
 943                 pe->mve_number = -1;
 944         } else {
 945                 rc = opal_pci_set_mve_enable(phb->opal_id,
 946                                              pe->mve_number, OPAL_ENABLE_MVE);
 947                 if (rc) {
 948                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 949                                rc, pe->mve_number);
 950                         pe->mve_number = -1;
 951                 }
 952         }
 953
 954 out:
 955         return 0;
 956 }
 957
 958 #ifdef CONFIG_PCI_IOV
 959 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 960 {
 961         struct pci_dn *pdn = pci_get_pdn(dev);
 962         int i;
 963         struct resource *res, res2;
 964         resource_size_t size;
 965         u16 num_vfs;
 966
 967         if (!dev->is_physfn)
 968                 return -EINVAL;
 969
 970         /*
 971          * "offset" is in VFs.  The M64 windows are sized so that when they
 972          * are segmented, each segment is the same size as the IOV BAR.
 973          * Each segment is in a separate PE, and the high order bits of the
 974          * address are the PE number.  Therefore, each VF's BAR is in a
 975          * separate PE, and changing the IOV BAR start address changes the
 976          * range of PEs the VFs are in.
 977          */
 978         num_vfs = pdn->num_vfs;
 979         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 980                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 981                 if (!res->flags || !res->parent)
 982                         continue;
 983
 984                 /*
 985                  * The actual IOV BAR range is determined by the start address
 986                  * and the actual size for num_vfs VFs BAR.  This check is to
 987                  * make sure that after shifting, the range will not overlap
 988                  * with another device.
 989                  */
 990                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 991                 res2.flags = res->flags;
 992                 res2.start = res->start + (size * offset);
 993                 res2.end = res2.start + (size * num_vfs) - 1;
 994
 995                 if (res2.end > res->end) {
 996                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 997                                 i, &res2, res, num_vfs, offset);
 998                         return -EBUSY;
 999                 }
1000         }
1001
1002         /*
1003          * Since M64 BAR shares segments among all possible 256 PEs,
1004          * we have to shift the beginning of PF IOV BAR to make it start from
1005          * the segment which belongs to the PE number assigned to the first VF.
1006          * This creates a "hole" in the /proc/iomem which could be used for
1007          * allocating other resources so we reserve this area below and
1008          * release when IOV is released.
1009          */
1010         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1011                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1012                 if (!res->flags || !res->parent)
1013                         continue;
1014
1015                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1016                 res2 = *res;
1017                 res->start += size * offset;
1018
1019                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1020                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1021                          num_vfs, offset);
1022
1023                 if (offset < 0) {
1024                         devm_release_resource(&dev->dev, &pdn->holes[i]);
1025                         memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1026                 }
1027
1028                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1029
1030                 if (offset > 0) {
1031                         pdn->holes[i].start = res2.start;
1032                         pdn->holes[i].end = res2.start + size * offset - 1;
1033                         pdn->holes[i].flags = IORESOURCE_BUS;
1034                         pdn->holes[i].name = "pnv_iov_reserved";
1035                         devm_request_resource(&dev->dev, res->parent,
1036                                         &pdn->holes[i]);
1037                 }
1038         }
1039         return 0;
1040 }
1041 #endif /* CONFIG_PCI_IOV */
1042
1043 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1044 {
1045         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1046         struct pnv_phb *phb = hose->private_data;
1047         struct pci_dn *pdn = pci_get_pdn(dev);
1048         struct pnv_ioda_pe *pe;
1049
1050         if (!pdn) {
1051                 pr_err("%s: Device tree node not associated properly\n",
1052                            pci_name(dev));
1053                 return NULL;
1054         }
1055         if (pdn->pe_number != IODA_INVALID_PE)
1056                 return NULL;
1057
1058         pe = pnv_ioda_alloc_pe(phb);
1059         if (!pe) {
1060                 pr_warn("%s: Not enough PE# available, disabling device\n",
1061                         pci_name(dev));
1062                 return NULL;
1063         }
1064
1065         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1066          * pointer in the PE data structure, both should be destroyed at the
1067          * same time. However, this needs to be looked at more closely again
1068          * once we actually start removing things (Hotplug, SR-IOV, ...)
1069          *
1070          * At some point we want to remove the PDN completely anyways
1071          */
1072         pci_dev_get(dev);
1073         pdn->pe_number = pe->pe_number;
1074         pe->flags = PNV_IODA_PE_DEV;
1075         pe->pdev = dev;
1076         pe->pbus = NULL;
1077         pe->mve_number = -1;
1078         pe->rid = dev->bus->number << 8 | pdn->devfn;
1079
1080         pe_info(pe, "Associated device to PE\n");
1081
1082         if (pnv_ioda_configure_pe(phb, pe)) {
1083                 /* XXX What do we do here ? */
1084                 pnv_ioda_free_pe(pe);
1085                 pdn->pe_number = IODA_INVALID_PE;
1086                 pe->pdev = NULL;
1087                 pci_dev_put(dev);
1088                 return NULL;
1089         }
1090
1091         /* Put PE to the list */
1092         list_add_tail(&pe->list, &phb->ioda.pe_list);
1093
1094         return pe;
1095 }
1096
1097 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1098 {
1099         struct pci_dev *dev;
1100
1101         list_for_each_entry(dev, &bus->devices, bus_list) {
1102                 struct pci_dn *pdn = pci_get_pdn(dev);
1103
1104                 if (pdn == NULL) {
1105                         pr_warn("%s: No device node associated with device !\n",
1106                                 pci_name(dev));
1107                         continue;
1108                 }
1109
1110                 /*
1111                  * In partial hotplug case, the PCI device might be still
1112                  * associated with the PE and needn't attach it to the PE
1113                  * again.
1114                  */
1115                 if (pdn->pe_number != IODA_INVALID_PE)
1116                         continue;
1117
1118                 pe->device_count++;
1119                 pdn->pe_number = pe->pe_number;
1120                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1121                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1122         }
1123 }
1124
1125 /*
1126  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1127  * single PCI bus. Another one that contains the primary PCI bus and its
1128  * subordinate PCI devices and buses. The second type of PE is normally
1129  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1130  */
1131 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1132 {
1133         struct pci_controller *hose = pci_bus_to_host(bus);
1134         struct pnv_phb *phb = hose->private_data;
1135         struct pnv_ioda_pe *pe = NULL;
1136         unsigned int pe_num;
1137
1138         /*
1139          * In partial hotplug case, the PE instance might be still alive.
1140          * We should reuse it instead of allocating a new one.
1141          */
1142         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1143         if (pe_num != IODA_INVALID_PE) {
1144                 pe = &phb->ioda.pe_array[pe_num];
1145                 pnv_ioda_setup_same_PE(bus, pe);
1146                 return NULL;
1147         }
1148
1149         /* PE number for root bus should have been reserved */
1150         if (pci_is_root_bus(bus) &&
1151             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1152                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1153
1154         /* Check if PE is determined by M64 */
1155         if (!pe)
1156                 pe = pnv_ioda_pick_m64_pe(bus, all);
1157
1158         /* The PE number isn't pinned by M64 */
1159         if (!pe)
1160                 pe = pnv_ioda_alloc_pe(phb);
1161
1162         if (!pe) {
1163                 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1164                         __func__, pci_domain_nr(bus), bus->number);
1165                 return NULL;
1166         }
1167
1168         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1169         pe->pbus = bus;
1170         pe->pdev = NULL;
1171         pe->mve_number = -1;
1172         pe->rid = bus->busn_res.start << 8;
1173
1174         if (all)
1175                 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1176                         &bus->busn_res.start, &bus->busn_res.end,
1177                         pe->pe_number);
1178         else
1179                 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1180                         &bus->busn_res.start, pe->pe_number);
1181
1182         if (pnv_ioda_configure_pe(phb, pe)) {
1183                 /* XXX What do we do here ? */
1184                 pnv_ioda_free_pe(pe);
1185                 pe->pbus = NULL;
1186                 return NULL;
1187         }
1188
1189         /* Associate it with all child devices */
1190         pnv_ioda_setup_same_PE(bus, pe);
1191
1192         /* Put PE to the list */
1193         list_add_tail(&pe->list, &phb->ioda.pe_list);
1194
1195         return pe;
1196 }
1197
1198 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1199 {
1200         int pe_num, found_pe = false, rc;
1201         long rid;
1202         struct pnv_ioda_pe *pe;
1203         struct pci_dev *gpu_pdev;
1204         struct pci_dn *npu_pdn;
1205         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1206         struct pnv_phb *phb = hose->private_data;
1207
1208         /*
1209          * Due to a hardware errata PE#0 on the NPU is reserved for
1210          * error handling. This means we only have three PEs remaining
1211          * which need to be assigned to four links, implying some
1212          * links must share PEs.
1213          *
1214          * To achieve this we assign PEs such that NPUs linking the
1215          * same GPU get assigned the same PE.
1216          */
1217         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1218         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1219                 pe = &phb->ioda.pe_array[pe_num];
1220                 if (!pe->pdev)
1221                         continue;
1222
1223                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1224                         /*
1225                          * This device has the same peer GPU so should
1226                          * be assigned the same PE as the existing
1227                          * peer NPU.
1228                          */
1229                         dev_info(&npu_pdev->dev,
1230                                 "Associating to existing PE %x\n", pe_num);
1231                         pci_dev_get(npu_pdev);
1232                         npu_pdn = pci_get_pdn(npu_pdev);
1233                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1234                         npu_pdn->pe_number = pe_num;
1235                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1236
1237                         /* Map the PE to this link */
1238                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1239                                         OpalPciBusAll,
1240                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1241                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1242                                         OPAL_MAP_PE);
1243                         WARN_ON(rc != OPAL_SUCCESS);
1244                         found_pe = true;
1245                         break;
1246                 }
1247         }
1248
1249         if (!found_pe)
1250                 /*
1251                  * Could not find an existing PE so allocate a new
1252                  * one.
1253                  */
1254                 return pnv_ioda_setup_dev_PE(npu_pdev);
1255         else
1256                 return pe;
1257 }
1258
1259 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1260 {
1261         struct pci_dev *pdev;
1262
1263         list_for_each_entry(pdev, &bus->devices, bus_list)
1264                 pnv_ioda_setup_npu_PE(pdev);
1265 }
1266
1267 static void pnv_pci_ioda_setup_PEs(void)
1268 {
1269         struct pci_controller *hose;
1270         struct pnv_phb *phb;
1271         struct pci_bus *bus;
1272         struct pci_dev *pdev;
1273         struct pnv_ioda_pe *pe;
1274
1275         list_for_each_entry(hose, &hose_list, list_node) {
1276                 phb = hose->private_data;
1277                 if (phb->type == PNV_PHB_NPU_NVLINK) {
1278                         /* PE#0 is needed for error reporting */
1279                         pnv_ioda_reserve_pe(phb, 0);
1280                         pnv_ioda_setup_npu_PEs(hose->bus);
1281                         if (phb->model == PNV_PHB_MODEL_NPU2)
1282                                 WARN_ON_ONCE(pnv_npu2_init(hose));
1283                 }
1284                 if (phb->type == PNV_PHB_NPU_OCAPI) {
1285                         bus = hose->bus;
1286                         list_for_each_entry(pdev, &bus->devices, bus_list)
1287                                 pnv_ioda_setup_dev_PE(pdev);
1288                 }
1289         }
1290         list_for_each_entry(hose, &hose_list, list_node) {
1291                 phb = hose->private_data;
1292                 if (phb->type != PNV_PHB_IODA2)
1293                         continue;
1294
1295                 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1296                         pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1297         }
1298 }
1299
1300 #ifdef CONFIG_PCI_IOV
1301 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1302 {
1303         struct pci_bus        *bus;
1304         struct pci_controller *hose;
1305         struct pnv_phb        *phb;
1306         struct pci_dn         *pdn;
1307         int                    i, j;
1308         int                    m64_bars;
1309
1310         bus = pdev->bus;
1311         hose = pci_bus_to_host(bus);
1312         phb = hose->private_data;
1313         pdn = pci_get_pdn(pdev);
1314
1315         if (pdn->m64_single_mode)
1316                 m64_bars = num_vfs;
1317         else
1318                 m64_bars = 1;
1319
1320         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1321                 for (j = 0; j < m64_bars; j++) {
1322                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1323                                 continue;
1324                         opal_pci_phb_mmio_enable(phb->opal_id,
1325                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1326                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1327                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1328                 }
1329
1330         kfree(pdn->m64_map);
1331         return 0;
1332 }
1333
1334 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1335 {
1336         struct pci_bus        *bus;
1337         struct pci_controller *hose;
1338         struct pnv_phb        *phb;
1339         struct pci_dn         *pdn;
1340         unsigned int           win;
1341         struct resource       *res;
1342         int                    i, j;
1343         int64_t                rc;
1344         int                    total_vfs;
1345         resource_size_t        size, start;
1346         int                    pe_num;
1347         int                    m64_bars;
1348
1349         bus = pdev->bus;
1350         hose = pci_bus_to_host(bus);
1351         phb = hose->private_data;
1352         pdn = pci_get_pdn(pdev);
1353         total_vfs = pci_sriov_get_totalvfs(pdev);
1354
1355         if (pdn->m64_single_mode)
1356                 m64_bars = num_vfs;
1357         else
1358                 m64_bars = 1;
1359
1360         pdn->m64_map = kmalloc_array(m64_bars,
1361                                      sizeof(*pdn->m64_map),
1362                                      GFP_KERNEL);
1363         if (!pdn->m64_map)
1364                 return -ENOMEM;
1365         /* Initialize the m64_map to IODA_INVALID_M64 */
1366         for (i = 0; i < m64_bars ; i++)
1367                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1368                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1369
1370
1371         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1372                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1373                 if (!res->flags || !res->parent)
1374                         continue;
1375
1376                 for (j = 0; j < m64_bars; j++) {
1377                         do {
1378                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1379                                                 phb->ioda.m64_bar_idx + 1, 0);
1380
1381                                 if (win >= phb->ioda.m64_bar_idx + 1)
1382                                         goto m64_failed;
1383                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1384
1385                         pdn->m64_map[j][i] = win;
1386
1387                         if (pdn->m64_single_mode) {
1388                                 size = pci_iov_resource_size(pdev,
1389                                                         PCI_IOV_RESOURCES + i);
1390                                 start = res->start + size * j;
1391                         } else {
1392                                 size = resource_size(res);
1393                                 start = res->start;
1394                         }
1395
1396                         /* Map the M64 here */
1397                         if (pdn->m64_single_mode) {
1398                                 pe_num = pdn->pe_num_map[j];
1399                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1400                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1401                                                 pdn->m64_map[j][i], 0);
1402                         }
1403
1404                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1405                                                  OPAL_M64_WINDOW_TYPE,
1406                                                  pdn->m64_map[j][i],
1407                                                  start,
1408                                                  0, /* unused */
1409                                                  size);
1410
1411
1412                         if (rc != OPAL_SUCCESS) {
1413                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1414                                         win, rc);
1415                                 goto m64_failed;
1416                         }
1417
1418                         if (pdn->m64_single_mode)
1419                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1420                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1421                         else
1422                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1423                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1424
1425                         if (rc != OPAL_SUCCESS) {
1426                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1427                                         win, rc);
1428                                 goto m64_failed;
1429                         }
1430                 }
1431         }
1432         return 0;
1433
1434 m64_failed:
1435         pnv_pci_vf_release_m64(pdev, num_vfs);
1436         return -EBUSY;
1437 }
1438
1439 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1440                 int num);
1441
1442 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1443 {
1444         struct iommu_table    *tbl;
1445         int64_t               rc;
1446
1447         tbl = pe->table_group.tables[0];
1448         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1449         if (rc)
1450                 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
1451
1452         pnv_pci_ioda2_set_bypass(pe, false);
1453         if (pe->table_group.group) {
1454                 iommu_group_put(pe->table_group.group);
1455                 BUG_ON(pe->table_group.group);
1456         }
1457         iommu_tce_table_put(tbl);
1458 }
1459
1460 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1461 {
1462         struct pci_bus        *bus;
1463         struct pci_controller *hose;
1464         struct pnv_phb        *phb;
1465         struct pnv_ioda_pe    *pe, *pe_n;
1466         struct pci_dn         *pdn;
1467
1468         bus = pdev->bus;
1469         hose = pci_bus_to_host(bus);
1470         phb = hose->private_data;
1471         pdn = pci_get_pdn(pdev);
1472
1473         if (!pdev->is_physfn)
1474                 return;
1475
1476         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1477                 if (pe->parent_dev != pdev)
1478                         continue;
1479
1480                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1481
1482                 /* Remove from list */
1483                 mutex_lock(&phb->ioda.pe_list_mutex);
1484                 list_del(&pe->list);
1485                 mutex_unlock(&phb->ioda.pe_list_mutex);
1486
1487                 pnv_ioda_deconfigure_pe(phb, pe);
1488
1489                 pnv_ioda_free_pe(pe);
1490         }
1491 }
1492
1493 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1494 {
1495         struct pci_bus        *bus;
1496         struct pci_controller *hose;
1497         struct pnv_phb        *phb;
1498         struct pnv_ioda_pe    *pe;
1499         struct pci_dn         *pdn;
1500         u16                    num_vfs, i;
1501
1502         bus = pdev->bus;
1503         hose = pci_bus_to_host(bus);
1504         phb = hose->private_data;
1505         pdn = pci_get_pdn(pdev);
1506         num_vfs = pdn->num_vfs;
1507
1508         /* Release VF PEs */
1509         pnv_ioda_release_vf_PE(pdev);
1510
1511         if (phb->type == PNV_PHB_IODA2) {
1512                 if (!pdn->m64_single_mode)
1513                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1514
1515                 /* Release M64 windows */
1516                 pnv_pci_vf_release_m64(pdev, num_vfs);
1517
1518                 /* Release PE numbers */
1519                 if (pdn->m64_single_mode) {
1520                         for (i = 0; i < num_vfs; i++) {
1521                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1522                                         continue;
1523
1524                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1525                                 pnv_ioda_free_pe(pe);
1526                         }
1527                 } else
1528                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1529                 /* Releasing pe_num_map */
1530                 kfree(pdn->pe_num_map);
1531         }
1532 }
1533
1534 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1535                                        struct pnv_ioda_pe *pe);
1536 #ifdef CONFIG_IOMMU_API
1537 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1538                 struct iommu_table_group *table_group, struct pci_bus *bus);
1539
1540 #endif
1541 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1542 {
1543         struct pci_bus        *bus;
1544         struct pci_controller *hose;
1545         struct pnv_phb        *phb;
1546         struct pnv_ioda_pe    *pe;
1547         int                    pe_num;
1548         u16                    vf_index;
1549         struct pci_dn         *pdn;
1550
1551         bus = pdev->bus;
1552         hose = pci_bus_to_host(bus);
1553         phb = hose->private_data;
1554         pdn = pci_get_pdn(pdev);
1555
1556         if (!pdev->is_physfn)
1557                 return;
1558
1559         /* Reserve PE for each VF */
1560         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1561                 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1562                 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1563                 struct pci_dn *vf_pdn;
1564
1565                 if (pdn->m64_single_mode)
1566                         pe_num = pdn->pe_num_map[vf_index];
1567                 else
1568                         pe_num = *pdn->pe_num_map + vf_index;
1569
1570                 pe = &phb->ioda.pe_array[pe_num];
1571                 pe->pe_number = pe_num;
1572                 pe->phb = phb;
1573                 pe->flags = PNV_IODA_PE_VF;
1574                 pe->pbus = NULL;
1575                 pe->parent_dev = pdev;
1576                 pe->mve_number = -1;
1577                 pe->rid = (vf_bus << 8) | vf_devfn;
1578
1579                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1580                         hose->global_number, pdev->bus->number,
1581                         PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1582
1583                 if (pnv_ioda_configure_pe(phb, pe)) {
1584                         /* XXX What do we do here ? */
1585                         pnv_ioda_free_pe(pe);
1586                         pe->pdev = NULL;
1587                         continue;
1588                 }
1589
1590                 /* Put PE to the list */
1591                 mutex_lock(&phb->ioda.pe_list_mutex);
1592                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1593                 mutex_unlock(&phb->ioda.pe_list_mutex);
1594
1595                 /* associate this pe to it's pdn */
1596                 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1597                         if (vf_pdn->busno == vf_bus &&
1598                             vf_pdn->devfn == vf_devfn) {
1599                                 vf_pdn->pe_number = pe_num;
1600                                 break;
1601                         }
1602                 }
1603
1604                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1605 #ifdef CONFIG_IOMMU_API
1606                 iommu_register_group(&pe->table_group,
1607                                 pe->phb->hose->global_number, pe->pe_number);
1608                 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1609 #endif
1610         }
1611 }
1612
1613 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1614 {
1615         struct pci_bus        *bus;
1616         struct pci_controller *hose;
1617         struct pnv_phb        *phb;
1618         struct pnv_ioda_pe    *pe;
1619         struct pci_dn         *pdn;
1620         int                    ret;
1621         u16                    i;
1622
1623         bus = pdev->bus;
1624         hose = pci_bus_to_host(bus);
1625         phb = hose->private_data;
1626         pdn = pci_get_pdn(pdev);
1627
1628         if (phb->type == PNV_PHB_IODA2) {
1629                 if (!pdn->vfs_expanded) {
1630                         dev_info(&pdev->dev, "don't support this SRIOV device"
1631                                 " with non 64bit-prefetchable IOV BAR\n");
1632                         return -ENOSPC;
1633                 }
1634
1635                 /*
1636                  * When M64 BARs functions in Single PE mode, the number of VFs
1637                  * could be enabled must be less than the number of M64 BARs.
1638                  */
1639                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1640                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1641                         return -EBUSY;
1642                 }
1643
1644                 /* Allocating pe_num_map */
1645                 if (pdn->m64_single_mode)
1646                         pdn->pe_num_map = kmalloc_array(num_vfs,
1647                                                         sizeof(*pdn->pe_num_map),
1648                                                         GFP_KERNEL);
1649                 else
1650                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1651
1652                 if (!pdn->pe_num_map)
1653                         return -ENOMEM;
1654
1655                 if (pdn->m64_single_mode)
1656                         for (i = 0; i < num_vfs; i++)
1657                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1658
1659                 /* Calculate available PE for required VFs */
1660                 if (pdn->m64_single_mode) {
1661                         for (i = 0; i < num_vfs; i++) {
1662                                 pe = pnv_ioda_alloc_pe(phb);
1663                                 if (!pe) {
1664                                         ret = -EBUSY;
1665                                         goto m64_failed;
1666                                 }
1667
1668                                 pdn->pe_num_map[i] = pe->pe_number;
1669                         }
1670                 } else {
1671                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1672                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1673                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1674                                 0, num_vfs, 0);
1675                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1676                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1677                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1678                                 kfree(pdn->pe_num_map);
1679                                 return -EBUSY;
1680                         }
1681                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1682                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1683                 }
1684                 pdn->num_vfs = num_vfs;
1685
1686                 /* Assign M64 window accordingly */
1687                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1688                 if (ret) {
1689                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1690                         goto m64_failed;
1691                 }
1692
1693                 /*
1694                  * When using one M64 BAR to map one IOV BAR, we need to shift
1695                  * the IOV BAR according to the PE# allocated to the VFs.
1696                  * Otherwise, the PE# for the VF will conflict with others.
1697                  */
1698                 if (!pdn->m64_single_mode) {
1699                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1700                         if (ret)
1701                                 goto m64_failed;
1702                 }
1703         }
1704
1705         /* Setup VF PEs */
1706         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1707
1708         return 0;
1709
1710 m64_failed:
1711         if (pdn->m64_single_mode) {
1712                 for (i = 0; i < num_vfs; i++) {
1713                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1714                                 continue;
1715
1716                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1717                         pnv_ioda_free_pe(pe);
1718                 }
1719         } else
1720                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1721
1722         /* Releasing pe_num_map */
1723         kfree(pdn->pe_num_map);
1724
1725         return ret;
1726 }
1727
1728 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1729 {
1730         pnv_pci_sriov_disable(pdev);
1731
1732         /* Release PCI data */
1733         remove_dev_pci_data(pdev);
1734         return 0;
1735 }
1736
1737 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1738 {
1739         /* Allocate PCI data */
1740         add_dev_pci_data(pdev);
1741
1742         return pnv_pci_sriov_enable(pdev, num_vfs);
1743 }
1744 #endif /* CONFIG_PCI_IOV */
1745
1746 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1747 {
1748         struct pci_dn *pdn = pci_get_pdn(pdev);
1749         struct pnv_ioda_pe *pe;
1750
1751         /*
1752          * The function can be called while the PE#
1753          * hasn't been assigned. Do nothing for the
1754          * case.
1755          */
1756         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1757                 return;
1758
1759         pe = &phb->ioda.pe_array[pdn->pe_number];
1760         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1761         pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1762         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1763         /*
1764          * Note: iommu_add_device() will fail here as
1765          * for physical PE: the device is already added by now;
1766          * for virtual PE: sysfs entries are not ready yet and
1767          * tce_iommu_bus_notifier will add the device to a group later.
1768          */
1769 }
1770
1771 /*
1772  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1773  *
1774  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1775  * Devices can only access more than that if bit 59 of the PCI address is set
1776  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1777  * Many PCI devices are not capable of addressing that many bits, and as a
1778  * result are limited to the 4GB of virtual memory made available to 32-bit
1779  * devices in TVE#0.
1780  *
1781  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1782  * devices by configuring the virtual memory past the first 4GB inaccessible
1783  * by 64-bit DMAs.  This should only be used by devices that want more than
1784  * 4GB, and only on PEs that have no 32-bit devices.
1785  *
1786  * Currently this will only work on PHB3 (POWER8).
1787  */
1788 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1789 {
1790         u64 window_size, table_size, tce_count, addr;
1791         struct page *table_pages;
1792         u64 tce_order = 28; /* 256MB TCEs */
1793         __be64 *tces;
1794         s64 rc;
1795
1796         /*
1797          * Window size needs to be a power of two, but needs to account for
1798          * shifting memory by the 4GB offset required to skip 32bit space.
1799          */
1800         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1801         tce_count = window_size >> tce_order;
1802         table_size = tce_count << 3;
1803
1804         if (table_size < PAGE_SIZE)
1805                 table_size = PAGE_SIZE;
1806
1807         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1808                                        get_order(table_size));
1809         if (!table_pages)
1810                 goto err;
1811
1812         tces = page_address(table_pages);
1813         if (!tces)
1814                 goto err;
1815
1816         memset(tces, 0, table_size);
1817
1818         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1819                 tces[(addr + (1ULL << 32)) >> tce_order] =
1820                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1821         }
1822
1823         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1824                                         pe->pe_number,
1825                                         /* reconfigure window 0 */
1826                                         (pe->pe_number << 1) + 0,
1827                                         1,
1828                                         __pa(tces),
1829                                         table_size,
1830                                         1 << tce_order);
1831         if (rc == OPAL_SUCCESS) {
1832                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1833                 return 0;
1834         }
1835 err:
1836         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1837         return -EIO;
1838 }
1839
1840 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1841                 u64 dma_mask)
1842 {
1843         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1844         struct pnv_phb *phb = hose->private_data;
1845         struct pci_dn *pdn = pci_get_pdn(pdev);
1846         struct pnv_ioda_pe *pe;
1847
1848         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1849                 return false;
1850
1851         pe = &phb->ioda.pe_array[pdn->pe_number];
1852         if (pe->tce_bypass_enabled) {
1853                 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1854                 if (dma_mask >= top)
1855                         return true;
1856         }
1857
1858         /*
1859          * If the device can't set the TCE bypass bit but still wants
1860          * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1861          * bypass the 32-bit region and be usable for 64-bit DMAs.
1862          * The device needs to be able to address all of this space.
1863          */
1864         if (dma_mask >> 32 &&
1865             dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1866             /* pe->pdev should be set if it's a single device, pe->pbus if not */
1867             (pe->device_count == 1 || !pe->pbus) &&
1868             phb->model == PNV_PHB_MODEL_PHB3) {
1869                 /* Configure the bypass mode */
1870                 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1871                 if (rc)
1872                         return false;
1873                 /* 4GB offset bypasses 32-bit space */
1874                 pdev->dev.archdata.dma_offset = (1ULL << 32);
1875                 return true;
1876         }
1877
1878         return false;
1879 }
1880
1881 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1882 {
1883         struct pci_dev *dev;
1884
1885         list_for_each_entry(dev, &bus->devices, bus_list) {
1886                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1887                 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1888
1889                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1890                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1891         }
1892 }
1893
1894 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1895                                                      bool real_mode)
1896 {
1897         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1898                 (phb->regs + 0x210);
1899 }
1900
1901 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1902                 unsigned long index, unsigned long npages, bool rm)
1903 {
1904         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1905                         &tbl->it_group_list, struct iommu_table_group_link,
1906                         next);
1907         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1908                         struct pnv_ioda_pe, table_group);
1909         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1910         unsigned long start, end, inc;
1911
1912         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1913         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1914                         npages - 1);
1915
1916         /* p7ioc-style invalidation, 2 TCEs per write */
1917         start |= (1ull << 63);
1918         end |= (1ull << 63);
1919         inc = 16;
1920         end |= inc - 1; /* round up end to be different than start */
1921
1922         mb(); /* Ensure above stores are visible */
1923         while (start <= end) {
1924                 if (rm)
1925                         __raw_rm_writeq_be(start, invalidate);
1926                 else
1927                         __raw_writeq_be(start, invalidate);
1928
1929                 start += inc;
1930         }
1931
1932         /*
1933          * The iommu layer will do another mb() for us on build()
1934          * and we don't care on free()
1935          */
1936 }
1937
1938 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1939                 long npages, unsigned long uaddr,
1940                 enum dma_data_direction direction,
1941                 unsigned long attrs)
1942 {
1943         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1944                         attrs);
1945
1946         if (!ret)
1947                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1948
1949         return ret;
1950 }
1951
1952 #ifdef CONFIG_IOMMU_API
1953 /* Common for IODA1 and IODA2 */
1954 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1955                 unsigned long *hpa, enum dma_data_direction *direction,
1956                 bool realmode)
1957 {
1958         return pnv_tce_xchg(tbl, index, hpa, direction, !realmode);
1959 }
1960 #endif
1961
1962 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1963                 long npages)
1964 {
1965         pnv_tce_free(tbl, index, npages);
1966
1967         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1968 }
1969
1970 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1971         .set = pnv_ioda1_tce_build,
1972 #ifdef CONFIG_IOMMU_API
1973         .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1974         .tce_kill = pnv_pci_p7ioc_tce_invalidate,
1975         .useraddrptr = pnv_tce_useraddrptr,
1976 #endif
1977         .clear = pnv_ioda1_tce_free,
1978         .get = pnv_tce_get,
1979 };
1980
1981 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
1982 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
1983 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
1984
1985 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1986 {
1987         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1988         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1989
1990         mb(); /* Ensure previous TCE table stores are visible */
1991         if (rm)
1992                 __raw_rm_writeq_be(val, invalidate);
1993         else
1994                 __raw_writeq_be(val, invalidate);
1995 }
1996
1997 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1998 {
1999         /* 01xb - invalidate TCEs that match the specified PE# */
2000         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2001         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2002
2003         mb(); /* Ensure above stores are visible */
2004         __raw_writeq_be(val, invalidate);
2005 }
2006
2007 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2008                                         unsigned shift, unsigned long index,
2009                                         unsigned long npages)
2010 {
2011         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2012         unsigned long start, end, inc;
2013
2014         /* We'll invalidate DMA address in PE scope */
2015         start = PHB3_TCE_KILL_INVAL_ONE;
2016         start |= (pe->pe_number & 0xFF);
2017         end = start;
2018
2019         /* Figure out the start, end and step */
2020         start |= (index << shift);
2021         end |= ((index + npages - 1) << shift);
2022         inc = (0x1ull << shift);
2023         mb();
2024
2025         while (start <= end) {
2026                 if (rm)
2027                         __raw_rm_writeq_be(start, invalidate);
2028                 else
2029                         __raw_writeq_be(start, invalidate);
2030                 start += inc;
2031         }
2032 }
2033
2034 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2035 {
2036         struct pnv_phb *phb = pe->phb;
2037
2038         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2039                 pnv_pci_phb3_tce_invalidate_pe(pe);
2040         else
2041                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2042                                   pe->pe_number, 0, 0, 0);
2043 }
2044
2045 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2046                 unsigned long index, unsigned long npages, bool rm)
2047 {
2048         struct iommu_table_group_link *tgl;
2049
2050         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2051                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2052                                 struct pnv_ioda_pe, table_group);
2053                 struct pnv_phb *phb = pe->phb;
2054                 unsigned int shift = tbl->it_page_shift;
2055
2056                 /*
2057                  * NVLink1 can use the TCE kill register directly as
2058                  * it's the same as PHB3. NVLink2 is different and
2059                  * should go via the OPAL call.
2060                  */
2061                 if (phb->model == PNV_PHB_MODEL_NPU) {
2062                         /*
2063                          * The NVLink hardware does not support TCE kill
2064                          * per TCE entry so we have to invalidate
2065                          * the entire cache for it.
2066                          */
2067                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2068                         continue;
2069                 }
2070                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2071                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2072                                                     index, npages);
2073                 else
2074                         opal_pci_tce_kill(phb->opal_id,
2075                                           OPAL_PCI_TCE_KILL_PAGES,
2076                                           pe->pe_number, 1u << shift,
2077                                           index << shift, npages);
2078         }
2079 }
2080
2081 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2082 {
2083         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2084                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2085         else
2086                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2087 }
2088
2089 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2090                 long npages, unsigned long uaddr,
2091                 enum dma_data_direction direction,
2092                 unsigned long attrs)
2093 {
2094         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2095                         attrs);
2096
2097         if (!ret)
2098                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2099
2100         return ret;
2101 }
2102
2103 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2104                 long npages)
2105 {
2106         pnv_tce_free(tbl, index, npages);
2107
2108         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2109 }
2110
2111 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2112         .set = pnv_ioda2_tce_build,
2113 #ifdef CONFIG_IOMMU_API
2114         .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
2115         .tce_kill = pnv_pci_ioda2_tce_invalidate,
2116         .useraddrptr = pnv_tce_useraddrptr,
2117 #endif
2118         .clear = pnv_ioda2_tce_free,
2119         .get = pnv_tce_get,
2120         .free = pnv_pci_ioda2_table_free_pages,
2121 };
2122
2123 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2124 {
2125         unsigned int *weight = (unsigned int *)data;
2126
2127         /* This is quite simplistic. The "base" weight of a device
2128          * is 10. 0 means no DMA is to be accounted for it.
2129          */
2130         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2131                 return 0;
2132
2133         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2134             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2135             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2136                 *weight += 3;
2137         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2138                 *weight += 15;
2139         else
2140                 *weight += 10;
2141
2142         return 0;
2143 }
2144
2145 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2146 {
2147         unsigned int weight = 0;
2148
2149         /* SRIOV VF has same DMA32 weight as its PF */
2150 #ifdef CONFIG_PCI_IOV
2151         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2152                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2153                 return weight;
2154         }
2155 #endif
2156
2157         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2158                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2159         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2160                 struct pci_dev *pdev;
2161
2162                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2163                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2164         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2165                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2166         }
2167
2168         return weight;
2169 }
2170
2171 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2172                                        struct pnv_ioda_pe *pe)
2173 {
2174
2175         struct page *tce_mem = NULL;
2176         struct iommu_table *tbl;
2177         unsigned int weight, total_weight = 0;
2178         unsigned int tce32_segsz, base, segs, avail, i;
2179         int64_t rc;
2180         void *addr;
2181
2182         /* XXX FIXME: Handle 64-bit only DMA devices */
2183         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2184         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2185         weight = pnv_pci_ioda_pe_dma_weight(pe);
2186         if (!weight)
2187                 return;
2188
2189         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2190                      &total_weight);
2191         segs = (weight * phb->ioda.dma32_count) / total_weight;
2192         if (!segs)
2193                 segs = 1;
2194
2195         /*
2196          * Allocate contiguous DMA32 segments. We begin with the expected
2197          * number of segments. With one more attempt, the number of DMA32
2198          * segments to be allocated is decreased by one until one segment
2199          * is allocated successfully.
2200          */
2201         do {
2202                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2203                         for (avail = 0, i = base; i < base + segs; i++) {
2204                                 if (phb->ioda.dma32_segmap[i] ==
2205                                     IODA_INVALID_PE)
2206                                         avail++;
2207                         }
2208
2209                         if (avail == segs)
2210                                 goto found;
2211                 }
2212         } while (--segs);
2213
2214         if (!segs) {
2215                 pe_warn(pe, "No available DMA32 segments\n");
2216                 return;
2217         }
2218
2219 found:
2220         tbl = pnv_pci_table_alloc(phb->hose->node);
2221         if (WARN_ON(!tbl))
2222                 return;
2223
2224         iommu_register_group(&pe->table_group, phb->hose->global_number,
2225                         pe->pe_number);
2226         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2227
2228         /* Grab a 32-bit TCE table */
2229         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2230                 weight, total_weight, base, segs);
2231         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2232                 base * PNV_IODA1_DMA32_SEGSIZE,
2233                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2234
2235         /* XXX Currently, we allocate one big contiguous table for the
2236          * TCEs. We only really need one chunk per 256M of TCE space
2237          * (ie per segment) but that's an optimization for later, it
2238          * requires some added smarts with our get/put_tce implementation
2239          *
2240          * Each TCE page is 4KB in size and each TCE entry occupies 8
2241          * bytes
2242          */
2243         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2244         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2245                                    get_order(tce32_segsz * segs));
2246         if (!tce_mem) {
2247                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2248                 goto fail;
2249         }
2250         addr = page_address(tce_mem);
2251         memset(addr, 0, tce32_segsz * segs);
2252
2253         /* Configure HW */
2254         for (i = 0; i < segs; i++) {
2255                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2256                                               pe->pe_number,
2257                                               base + i, 1,
2258                                               __pa(addr) + tce32_segsz * i,
2259                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2260                 if (rc) {
2261                         pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
2262                                rc);
2263                         goto fail;
2264                 }
2265         }
2266
2267         /* Setup DMA32 segment mapping */
2268         for (i = base; i < base + segs; i++)
2269                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2270
2271         /* Setup linux iommu table */
2272         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2273                                   base * PNV_IODA1_DMA32_SEGSIZE,
2274                                   IOMMU_PAGE_SHIFT_4K);
2275
2276         tbl->it_ops = &pnv_ioda1_iommu_ops;
2277         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2278         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2279         iommu_init_table(tbl, phb->hose->node, 0, 0);
2280
2281         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2282                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2283
2284         return;
2285  fail:
2286         /* XXX Failure: Try to fallback to 64-bit only ? */
2287         if (tce_mem)
2288                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2289         if (tbl) {
2290                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2291                 iommu_tce_table_put(tbl);
2292         }
2293 }
2294
2295 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2296                 int num, struct iommu_table *tbl)
2297 {
2298         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2299                         table_group);
2300         struct pnv_phb *phb = pe->phb;
2301         int64_t rc;
2302         const unsigned long size = tbl->it_indirect_levels ?
2303                         tbl->it_level_size : tbl->it_size;
2304         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2305         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2306
2307         pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
2308                 num, start_addr, start_addr + win_size - 1,
2309                 IOMMU_PAGE_SIZE(tbl));
2310
2311         /*
2312          * Map TCE table through TVT. The TVE index is the PE number
2313          * shifted by 1 bit for 32-bits DMA space.
2314          */
2315         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2316                         pe->pe_number,
2317                         (pe->pe_number << 1) + num,
2318                         tbl->it_indirect_levels + 1,
2319                         __pa(tbl->it_base),
2320                         size << 3,
2321                         IOMMU_PAGE_SIZE(tbl));
2322         if (rc) {
2323                 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
2324                 return rc;
2325         }
2326
2327         pnv_pci_link_table_and_group(phb->hose->node, num,
2328                         tbl, &pe->table_group);
2329         pnv_pci_ioda2_tce_invalidate_pe(pe);
2330
2331         return 0;
2332 }
2333
2334 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2335 {
2336         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2337         int64_t rc;
2338
2339         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2340         if (enable) {
2341                 phys_addr_t top = memblock_end_of_DRAM();
2342
2343                 top = roundup_pow_of_two(top);
2344                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2345                                                      pe->pe_number,
2346                                                      window_id,
2347                                                      pe->tce_bypass_base,
2348                                                      top);
2349         } else {
2350                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2351                                                      pe->pe_number,
2352                                                      window_id,
2353                                                      pe->tce_bypass_base,
2354                                                      0);
2355         }
2356         if (rc)
2357                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2358         else
2359                 pe->tce_bypass_enabled = enable;
2360 }
2361
2362 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2363                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2364                 bool alloc_userspace_copy, struct iommu_table **ptbl)
2365 {
2366         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2367                         table_group);
2368         int nid = pe->phb->hose->node;
2369         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2370         long ret;
2371         struct iommu_table *tbl;
2372
2373         tbl = pnv_pci_table_alloc(nid);
2374         if (!tbl)
2375                 return -ENOMEM;
2376
2377         tbl->it_ops = &pnv_ioda2_iommu_ops;
2378
2379         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2380                         bus_offset, page_shift, window_size,
2381                         levels, alloc_userspace_copy, tbl);
2382         if (ret) {
2383                 iommu_tce_table_put(tbl);
2384                 return ret;
2385         }
2386
2387         *ptbl = tbl;
2388
2389         return 0;
2390 }
2391
2392 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2393 {
2394         struct iommu_table *tbl = NULL;
2395         long rc;
2396         unsigned long res_start, res_end;
2397
2398         /*
2399          * crashkernel= specifies the kdump kernel's maximum memory at
2400          * some offset and there is no guaranteed the result is a power
2401          * of 2, which will cause errors later.
2402          */
2403         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2404
2405         /*
2406          * In memory constrained environments, e.g. kdump kernel, the
2407          * DMA window can be larger than available memory, which will
2408          * cause errors later.
2409          */
2410         const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
2411
2412         /*
2413          * We create the default window as big as we can. The constraint is
2414          * the max order of allocation possible. The TCE table is likely to
2415          * end up being multilevel and with on-demand allocation in place,
2416          * the initial use is not going to be huge as the default window aims
2417          * to support crippled devices (i.e. not fully 64bit DMAble) only.
2418          */
2419         /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
2420         const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
2421         /* Each TCE level cannot exceed maxblock so go multilevel if needed */
2422         unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
2423         unsigned long tcelevel_order = ilog2(maxblock >> 3);
2424         unsigned int levels = tces_order / tcelevel_order;
2425
2426         if (tces_order % tcelevel_order)
2427                 levels += 1;
2428         /*
2429          * We try to stick to default levels (which is >1 at the moment) in
2430          * order to save memory by relying on on-demain TCE level allocation.
2431          */
2432         levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
2433
2434         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
2435                         window_size, levels, false, &tbl);
2436         if (rc) {
2437                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2438                                 rc);
2439                 return rc;
2440         }
2441
2442         /* We use top part of 32bit space for MMIO so exclude it from DMA */
2443         res_start = 0;
2444         res_end = 0;
2445         if (window_size > pe->phb->ioda.m32_pci_base) {
2446                 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
2447                 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
2448         }
2449         iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
2450
2451         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2452         if (rc) {
2453                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2454                                 rc);
2455                 iommu_tce_table_put(tbl);
2456                 return rc;
2457         }
2458
2459         if (!pnv_iommu_bypass_disabled)
2460                 pnv_pci_ioda2_set_bypass(pe, true);
2461
2462         /*
2463          * Set table base for the case of IOMMU DMA use. Usually this is done
2464          * from dma_dev_setup() which is not called when a device is returned
2465          * from VFIO so do it here.
2466          */
2467         if (pe->pdev)
2468                 set_iommu_table_base(&pe->pdev->dev, tbl);
2469
2470         return 0;
2471 }
2472
2473 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2474 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2475                 int num)
2476 {
2477         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2478                         table_group);
2479         struct pnv_phb *phb = pe->phb;
2480         long ret;
2481
2482         pe_info(pe, "Removing DMA window #%d\n", num);
2483
2484         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2485                         (pe->pe_number << 1) + num,
2486                         0/* levels */, 0/* table address */,
2487                         0/* table size */, 0/* page size */);
2488         if (ret)
2489                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2490         else
2491                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2492
2493         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2494
2495         return ret;
2496 }
2497 #endif
2498
2499 #ifdef CONFIG_IOMMU_API
2500 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2501                 __u64 window_size, __u32 levels)
2502 {
2503         unsigned long bytes = 0;
2504         const unsigned window_shift = ilog2(window_size);
2505         unsigned entries_shift = window_shift - page_shift;
2506         unsigned table_shift = entries_shift + 3;
2507         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2508         unsigned long direct_table_size;
2509
2510         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2511                         !is_power_of_2(window_size))
2512                 return 0;
2513
2514         /* Calculate a direct table size from window_size and levels */
2515         entries_shift = (entries_shift + levels - 1) / levels;
2516         table_shift = entries_shift + 3;
2517         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2518         direct_table_size =  1UL << table_shift;
2519
2520         for ( ; levels; --levels) {
2521                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2522
2523                 tce_table_size /= direct_table_size;
2524                 tce_table_size <<= 3;
2525                 tce_table_size = max_t(unsigned long,
2526                                 tce_table_size, direct_table_size);
2527         }
2528
2529         return bytes + bytes; /* one for HW table, one for userspace copy */
2530 }
2531
2532 static long pnv_pci_ioda2_create_table_userspace(
2533                 struct iommu_table_group *table_group,
2534                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2535                 struct iommu_table **ptbl)
2536 {
2537         long ret = pnv_pci_ioda2_create_table(table_group,
2538                         num, page_shift, window_size, levels, true, ptbl);
2539
2540         if (!ret)
2541                 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2542                                 page_shift, window_size, levels);
2543         return ret;
2544 }
2545
2546 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2547 {
2548         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2549                                                 table_group);
2550         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2551         struct iommu_table *tbl = pe->table_group.tables[0];
2552
2553         pnv_pci_ioda2_set_bypass(pe, false);
2554         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2555         if (pe->pbus)
2556                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2557         else if (pe->pdev)
2558                 set_iommu_table_base(&pe->pdev->dev, NULL);
2559         iommu_tce_table_put(tbl);
2560 }
2561
2562 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2563 {
2564         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2565                                                 table_group);
2566
2567         pnv_pci_ioda2_setup_default_config(pe);
2568         if (pe->pbus)
2569                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2570 }
2571
2572 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2573         .get_table_size = pnv_pci_ioda2_get_table_size,
2574         .create_table = pnv_pci_ioda2_create_table_userspace,
2575         .set_window = pnv_pci_ioda2_set_window,
2576         .unset_window = pnv_pci_ioda2_unset_window,
2577         .take_ownership = pnv_ioda2_take_ownership,
2578         .release_ownership = pnv_ioda2_release_ownership,
2579 };
2580
2581 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2582                 struct iommu_table_group *table_group,
2583                 struct pci_bus *bus)
2584 {
2585         struct pci_dev *dev;
2586
2587         list_for_each_entry(dev, &bus->devices, bus_list) {
2588                 iommu_add_device(table_group, &dev->dev);
2589
2590                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2591                         pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2592                                         table_group, dev->subordinate);
2593         }
2594 }
2595
2596 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2597                 struct iommu_table_group *table_group, struct pci_bus *bus)
2598 {
2599
2600         if (pe->flags & PNV_IODA_PE_DEV)
2601                 iommu_add_device(table_group, &pe->pdev->dev);
2602
2603         if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2604                 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2605                                 bus);
2606 }
2607
2608 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2609
2610 static void pnv_pci_ioda_setup_iommu_api(void)
2611 {
2612         struct pci_controller *hose;
2613         struct pnv_phb *phb;
2614         struct pnv_ioda_pe *pe;
2615
2616         /*
2617          * There are 4 types of PEs:
2618          * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2619          *   created from pnv_pci_setup_bridge();
2620          * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2621          *   created from pnv_pci_setup_bridge();
2622          * - PNV_IODA_PE_VF: a SRIOV virtual function,
2623          *   created from pnv_pcibios_sriov_enable();
2624          * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2625          *   created from pnv_pci_ioda_fixup().
2626          *
2627          * Normally a PE is represented by an IOMMU group, however for
2628          * devices with side channels the groups need to be more strict.
2629          */
2630         list_for_each_entry(hose, &hose_list, list_node) {
2631                 phb = hose->private_data;
2632
2633                 if (phb->type == PNV_PHB_NPU_NVLINK ||
2634                     phb->type == PNV_PHB_NPU_OCAPI)
2635                         continue;
2636
2637                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2638                         struct iommu_table_group *table_group;
2639
2640                         table_group = pnv_try_setup_npu_table_group(pe);
2641                         if (!table_group) {
2642                                 if (!pnv_pci_ioda_pe_dma_weight(pe))
2643                                         continue;
2644
2645                                 table_group = &pe->table_group;
2646                                 iommu_register_group(&pe->table_group,
2647                                                 pe->phb->hose->global_number,
2648                                                 pe->pe_number);
2649                         }
2650                         pnv_ioda_setup_bus_iommu_group(pe, table_group,
2651                                         pe->pbus);
2652                 }
2653         }
2654
2655         /*
2656          * Now we have all PHBs discovered, time to add NPU devices to
2657          * the corresponding IOMMU groups.
2658          */
2659         list_for_each_entry(hose, &hose_list, list_node) {
2660                 unsigned long  pgsizes;
2661
2662                 phb = hose->private_data;
2663
2664                 if (phb->type != PNV_PHB_NPU_NVLINK)
2665                         continue;
2666
2667                 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2668                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2669                         /*
2670                          * IODA2 bridges get this set up from
2671                          * pci_controller_ops::setup_bridge but NPU bridges
2672                          * do not have this hook defined so we do it here.
2673                          */
2674                         pe->table_group.pgsizes = pgsizes;
2675                         pnv_npu_compound_attach(pe);
2676                 }
2677         }
2678 }
2679 #else /* !CONFIG_IOMMU_API */
2680 static void pnv_pci_ioda_setup_iommu_api(void) { };
2681 #endif
2682
2683 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2684 {
2685         struct pci_controller *hose = phb->hose;
2686         struct device_node *dn = hose->dn;
2687         unsigned long mask = 0;
2688         int i, rc, count;
2689         u32 val;
2690
2691         count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2692         if (count <= 0) {
2693                 mask = SZ_4K | SZ_64K;
2694                 /* Add 16M for POWER8 by default */
2695                 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2696                                 !cpu_has_feature(CPU_FTR_ARCH_300))
2697                         mask |= SZ_16M | SZ_256M;
2698                 return mask;
2699         }
2700
2701         for (i = 0; i < count; i++) {
2702                 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2703                                                 i, &val);
2704                 if (rc == 0)
2705                         mask |= 1ULL << val;
2706         }
2707
2708         return mask;
2709 }
2710
2711 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2712                                        struct pnv_ioda_pe *pe)
2713 {
2714         int64_t rc;
2715
2716         if (!pnv_pci_ioda_pe_dma_weight(pe))
2717                 return;
2718
2719         /* TVE #1 is selected by PCI address bit 59 */
2720         pe->tce_bypass_base = 1ull << 59;
2721
2722         /* The PE will reserve all possible 32-bits space */
2723         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2724                 phb->ioda.m32_pci_base);
2725
2726         /* Setup linux iommu table */
2727         pe->table_group.tce32_start = 0;
2728         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2729         pe->table_group.max_dynamic_windows_supported =
2730                         IOMMU_TABLE_GROUP_MAX_TABLES;
2731         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2732         pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2733 #ifdef CONFIG_IOMMU_API
2734         pe->table_group.ops = &pnv_pci_ioda2_ops;
2735 #endif
2736
2737         rc = pnv_pci_ioda2_setup_default_config(pe);
2738         if (rc)
2739                 return;
2740
2741         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2742                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2743 }
2744
2745 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2746 {
2747         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2748                                            ioda.irq_chip);
2749
2750         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2751 }
2752
2753 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2754 {
2755         int64_t rc;
2756         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2757         struct irq_chip *chip = irq_data_get_irq_chip(d);
2758
2759         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2760         WARN_ON_ONCE(rc);
2761
2762         icp_native_eoi(d);
2763 }
2764
2765
2766 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2767 {
2768         struct irq_data *idata;
2769         struct irq_chip *ichip;
2770
2771         /* The MSI EOI OPAL call is only needed on PHB3 */
2772         if (phb->model != PNV_PHB_MODEL_PHB3)
2773                 return;
2774
2775         if (!phb->ioda.irq_chip_init) {
2776                 /*
2777                  * First time we setup an MSI IRQ, we need to setup the
2778                  * corresponding IRQ chip to route correctly.
2779                  */
2780                 idata = irq_get_irq_data(virq);
2781                 ichip = irq_data_get_irq_chip(idata);
2782                 phb->ioda.irq_chip_init = 1;
2783                 phb->ioda.irq_chip = *ichip;
2784                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2785         }
2786         irq_set_chip(virq, &phb->ioda.irq_chip);
2787 }
2788
2789 /*
2790  * Returns true iff chip is something that we could call
2791  * pnv_opal_pci_msi_eoi for.
2792  */
2793 bool is_pnv_opal_msi(struct irq_chip *chip)
2794 {
2795         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2796 }
2797 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2798
2799 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2800                                   unsigned int hwirq, unsigned int virq,
2801                                   unsigned int is_64, struct msi_msg *msg)
2802 {
2803         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2804         unsigned int xive_num = hwirq - phb->msi_base;
2805         __be32 data;
2806         int rc;
2807
2808         /* No PE assigned ? bail out ... no MSI for you ! */
2809         if (pe == NULL)
2810                 return -ENXIO;
2811
2812         /* Check if we have an MVE */
2813         if (pe->mve_number < 0)
2814                 return -ENXIO;
2815
2816         /* Force 32-bit MSI on some broken devices */
2817         if (dev->no_64bit_msi)
2818                 is_64 = 0;
2819
2820         /* Assign XIVE to PE */
2821         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2822         if (rc) {
2823                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2824                         pci_name(dev), rc, xive_num);
2825                 return -EIO;
2826         }
2827
2828         if (is_64) {
2829                 __be64 addr64;
2830
2831                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2832                                      &addr64, &data);
2833                 if (rc) {
2834                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2835                                 pci_name(dev), rc);
2836                         return -EIO;
2837                 }
2838                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2839                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2840         } else {
2841                 __be32 addr32;
2842
2843                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2844                                      &addr32, &data);
2845                 if (rc) {
2846                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2847                                 pci_name(dev), rc);
2848                         return -EIO;
2849                 }
2850                 msg->address_hi = 0;
2851                 msg->address_lo = be32_to_cpu(addr32);
2852         }
2853         msg->data = be32_to_cpu(data);
2854
2855         pnv_set_msi_irq_chip(phb, virq);
2856
2857         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2858                  " address=%x_%08x data=%x PE# %x\n",
2859                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2860                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2861
2862         return 0;
2863 }
2864
2865 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2866 {
2867         unsigned int count;
2868         const __be32 *prop = of_get_property(phb->hose->dn,
2869                                              "ibm,opal-msi-ranges", NULL);
2870         if (!prop) {
2871                 /* BML Fallback */
2872                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2873         }
2874         if (!prop)
2875                 return;
2876
2877         phb->msi_base = be32_to_cpup(prop);
2878         count = be32_to_cpup(prop + 1);
2879         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2880                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2881                        phb->hose->global_number);
2882                 return;
2883         }
2884
2885         phb->msi_setup = pnv_pci_ioda_msi_setup;
2886         phb->msi32_support = 1;
2887         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2888                 count, phb->msi_base);
2889 }
2890
2891 #ifdef CONFIG_PCI_IOV
2892 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2893 {
2894         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2895         struct pnv_phb *phb = hose->private_data;
2896         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2897         struct resource *res;
2898         int i;
2899         resource_size_t size, total_vf_bar_sz;
2900         struct pci_dn *pdn;
2901         int mul, total_vfs;
2902
2903         pdn = pci_get_pdn(pdev);
2904         pdn->vfs_expanded = 0;
2905         pdn->m64_single_mode = false;
2906
2907         total_vfs = pci_sriov_get_totalvfs(pdev);
2908         mul = phb->ioda.total_pe_num;
2909         total_vf_bar_sz = 0;
2910
2911         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2912                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2913                 if (!res->flags || res->parent)
2914                         continue;
2915                 if (!pnv_pci_is_m64_flags(res->flags)) {
2916                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
2917                                         " non M64 VF BAR%d: %pR. \n",
2918                                  i, res);
2919                         goto truncate_iov;
2920                 }
2921
2922                 total_vf_bar_sz += pci_iov_resource_size(pdev,
2923                                 i + PCI_IOV_RESOURCES);
2924
2925                 /*
2926                  * If bigger than quarter of M64 segment size, just round up
2927                  * power of two.
2928                  *
2929                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2930                  * with other devices, IOV BAR size is expanded to be
2931                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
2932                  * segment size , the expanded size would equal to half of the
2933                  * whole M64 space size, which will exhaust the M64 Space and
2934                  * limit the system flexibility.  This is a design decision to
2935                  * set the boundary to quarter of the M64 segment size.
2936                  */
2937                 if (total_vf_bar_sz > gate) {
2938                         mul = roundup_pow_of_two(total_vfs);
2939                         dev_info(&pdev->dev,
2940                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2941                                 total_vf_bar_sz, gate, mul);
2942                         pdn->m64_single_mode = true;
2943                         break;
2944                 }
2945         }
2946
2947         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2948                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2949                 if (!res->flags || res->parent)
2950                         continue;
2951
2952                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2953                 /*
2954                  * On PHB3, the minimum size alignment of M64 BAR in single
2955                  * mode is 32MB.
2956                  */
2957                 if (pdn->m64_single_mode && (size < SZ_32M))
2958                         goto truncate_iov;
2959                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2960                 res->end = res->start + size * mul - 1;
2961                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2962                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2963                          i, res, mul);
2964         }
2965         pdn->vfs_expanded = mul;
2966
2967         return;
2968
2969 truncate_iov:
2970         /* To save MMIO space, IOV BAR is truncated. */
2971         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2972                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2973                 res->flags = 0;
2974                 res->end = res->start - 1;
2975         }
2976 }
2977
2978 static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
2979 {
2980         if (WARN_ON(pci_dev_is_added(pdev)))
2981                 return;
2982
2983         if (pdev->is_virtfn) {
2984                 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
2985
2986                 /*
2987                  * VF PEs are single-device PEs so their pdev pointer needs to
2988                  * be set. The pdev doesn't exist when the PE is allocated (in
2989                  * (pcibios_sriov_enable()) so we fix it up here.
2990                  */
2991                 pe->pdev = pdev;
2992                 WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
2993         } else if (pdev->is_physfn) {
2994                 /*
2995                  * For PFs adjust their allocated IOV resources to match what
2996                  * the PHB can support using it's M64 BAR table.
2997                  */
2998                 pnv_pci_ioda_fixup_iov_resources(pdev);
2999         }
3000 }
3001 #endif /* CONFIG_PCI_IOV */
3002
3003 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3004                                   struct resource *res)
3005 {
3006         struct pnv_phb *phb = pe->phb;
3007         struct pci_bus_region region;
3008         int index;
3009         int64_t rc;
3010
3011         if (!res || !res->flags || res->start > res->end ||
3012             res->flags & IORESOURCE_UNSET)
3013                 return;
3014
3015         if (res->flags & IORESOURCE_IO) {
3016                 region.start = res->start - phb->ioda.io_pci_base;
3017                 region.end   = res->end - phb->ioda.io_pci_base;
3018                 index = region.start / phb->ioda.io_segsize;
3019
3020                 while (index < phb->ioda.total_pe_num &&
3021                        region.start <= region.end) {
3022                         phb->ioda.io_segmap[index] = pe->pe_number;
3023                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3024                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3025                         if (rc != OPAL_SUCCESS) {
3026                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3027                                        __func__, rc, index, pe->pe_number);
3028                                 break;
3029                         }
3030
3031                         region.start += phb->ioda.io_segsize;
3032                         index++;
3033                 }
3034         } else if ((res->flags & IORESOURCE_MEM) &&
3035                    !pnv_pci_is_m64(phb, res)) {
3036                 region.start = res->start -
3037                                phb->hose->mem_offset[0] -
3038                                phb->ioda.m32_pci_base;
3039                 region.end   = res->end -
3040                                phb->hose->mem_offset[0] -
3041                                phb->ioda.m32_pci_base;
3042                 index = region.start / phb->ioda.m32_segsize;
3043
3044                 while (index < phb->ioda.total_pe_num &&
3045                        region.start <= region.end) {
3046                         phb->ioda.m32_segmap[index] = pe->pe_number;
3047                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3048                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3049                         if (rc != OPAL_SUCCESS) {
3050                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3051                                        __func__, rc, index, pe->pe_number);
3052                                 break;
3053                         }
3054
3055                         region.start += phb->ioda.m32_segsize;
3056                         index++;
3057                 }
3058         }
3059 }
3060
3061 /*
3062  * This function is supposed to be called on basis of PE from top
3063  * to bottom style. So the the I/O or MMIO segment assigned to
3064  * parent PE could be overridden by its child PEs if necessary.
3065  */
3066 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3067 {
3068         struct pci_dev *pdev;
3069         int i;
3070
3071         /*
3072          * NOTE: We only care PCI bus based PE for now. For PCI
3073          * device based PE, for example SRIOV sensitive VF should
3074          * be figured out later.
3075          */
3076         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3077
3078         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3079                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3080                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3081
3082                 /*
3083                  * If the PE contains all subordinate PCI buses, the
3084                  * windows of the child bridges should be mapped to
3085                  * the PE as well.
3086                  */
3087                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3088                         continue;
3089                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3090                         pnv_ioda_setup_pe_res(pe,
3091                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3092         }
3093 }
3094
3095 #ifdef CONFIG_DEBUG_FS
3096 static int pnv_pci_diag_data_set(void *data, u64 val)
3097 {
3098         struct pci_controller *hose;
3099         struct pnv_phb *phb;
3100         s64 ret;
3101
3102         if (val != 1ULL)
3103                 return -EINVAL;
3104
3105         hose = (struct pci_controller *)data;
3106         if (!hose || !hose->private_data)
3107                 return -ENODEV;
3108
3109         phb = hose->private_data;
3110
3111         /* Retrieve the diag data from firmware */
3112         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3113                                           phb->diag_data_size);
3114         if (ret != OPAL_SUCCESS)
3115                 return -EIO;
3116
3117         /* Print the diag data to the kernel log */
3118         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3119         return 0;
3120 }
3121
3122 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3123                         pnv_pci_diag_data_set, "%llu\n");
3124
3125 #endif /* CONFIG_DEBUG_FS */
3126
3127 static void pnv_pci_ioda_create_dbgfs(void)
3128 {
3129 #ifdef CONFIG_DEBUG_FS
3130         struct pci_controller *hose, *tmp;
3131         struct pnv_phb *phb;
3132         char name[16];
3133
3134         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3135                 phb = hose->private_data;
3136
3137                 /* Notify initialization of PHB done */
3138                 phb->initialized = 1;
3139
3140                 sprintf(name, "PCI%04x", hose->global_number);
3141                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3142                 if (!phb->dbgfs) {
3143                         pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3144                                 __func__, hose->global_number);
3145                         continue;
3146                 }
3147
3148                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3149                                     &pnv_pci_diag_data_fops);
3150         }
3151 #endif /* CONFIG_DEBUG_FS */
3152 }
3153
3154 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3155 {
3156         struct pci_dev *dev = bus->self;
3157         struct pci_bus *child;
3158
3159         /* Empty bus ? bail */
3160         if (list_empty(&bus->devices))
3161                 return;
3162
3163         /*
3164          * If there's a bridge associated with that bus enable it. This works
3165          * around races in the generic code if the enabling is done during
3166          * parallel probing. This can be removed once those races have been
3167          * fixed.
3168          */
3169         if (dev) {
3170                 int rc = pci_enable_device(dev);
3171                 if (rc)
3172                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3173                 pci_set_master(dev);
3174         }
3175
3176         /* Perform the same to child busses */
3177         list_for_each_entry(child, &bus->children, node)
3178                 pnv_pci_enable_bridge(child);
3179 }
3180
3181 static void pnv_pci_enable_bridges(void)
3182 {
3183         struct pci_controller *hose;
3184
3185         list_for_each_entry(hose, &hose_list, list_node)
3186                 pnv_pci_enable_bridge(hose->bus);
3187 }
3188
3189 static void pnv_pci_ioda_fixup(void)
3190 {
3191         pnv_pci_ioda_setup_PEs();
3192         pnv_pci_ioda_setup_iommu_api();
3193         pnv_pci_ioda_create_dbgfs();
3194
3195         pnv_pci_enable_bridges();
3196
3197 #ifdef CONFIG_EEH
3198         pnv_eeh_post_init();
3199 #endif
3200 }
3201
3202 /*
3203  * Returns the alignment for I/O or memory windows for P2P
3204  * bridges. That actually depends on how PEs are segmented.
3205  * For now, we return I/O or M32 segment size for PE sensitive
3206  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3207  * 1MiB for memory) will be returned.
3208  *
3209  * The current PCI bus might be put into one PE, which was
3210  * create against the parent PCI bridge. For that case, we
3211  * needn't enlarge the alignment so that we can save some
3212  * resources.
3213  */
3214 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3215                                                 unsigned long type)
3216 {
3217         struct pci_dev *bridge;
3218         struct pci_controller *hose = pci_bus_to_host(bus);
3219         struct pnv_phb *phb = hose->private_data;
3220         int num_pci_bridges = 0;
3221
3222         bridge = bus->self;
3223         while (bridge) {
3224                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3225                         num_pci_bridges++;
3226                         if (num_pci_bridges >= 2)
3227                                 return 1;
3228                 }
3229
3230                 bridge = bridge->bus->self;
3231         }
3232
3233         /*
3234          * We fall back to M32 if M64 isn't supported. We enforce the M64
3235          * alignment for any 64-bit resource, PCIe doesn't care and
3236          * bridges only do 64-bit prefetchable anyway.
3237          */
3238         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3239                 return phb->ioda.m64_segsize;
3240         if (type & IORESOURCE_MEM)
3241                 return phb->ioda.m32_segsize;
3242
3243         return phb->ioda.io_segsize;
3244 }
3245
3246 /*
3247  * We are updating root port or the upstream port of the
3248  * bridge behind the root port with PHB's windows in order
3249  * to accommodate the changes on required resources during
3250  * PCI (slot) hotplug, which is connected to either root
3251  * port or the downstream ports of PCIe switch behind the
3252  * root port.
3253  */
3254 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3255                                            unsigned long type)
3256 {
3257         struct pci_controller *hose = pci_bus_to_host(bus);
3258         struct pnv_phb *phb = hose->private_data;
3259         struct pci_dev *bridge = bus->self;
3260         struct resource *r, *w;
3261         bool msi_region = false;
3262         int i;
3263
3264         /* Check if we need apply fixup to the bridge's windows */
3265         if (!pci_is_root_bus(bridge->bus) &&
3266             !pci_is_root_bus(bridge->bus->self->bus))
3267                 return;
3268
3269         /* Fixup the resources */
3270         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3271                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3272                 if (!r->flags || !r->parent)
3273                         continue;
3274
3275                 w = NULL;
3276                 if (r->flags & type & IORESOURCE_IO)
3277                         w = &hose->io_resource;
3278                 else if (pnv_pci_is_m64(phb, r) &&
3279                          (type & IORESOURCE_PREFETCH) &&
3280                          phb->ioda.m64_segsize)
3281                         w = &hose->mem_resources[1];
3282                 else if (r->flags & type & IORESOURCE_MEM) {
3283                         w = &hose->mem_resources[0];
3284                         msi_region = true;
3285                 }
3286
3287                 r->start = w->start;
3288                 r->end = w->end;
3289
3290                 /* The 64KB 32-bits MSI region shouldn't be included in
3291                  * the 32-bits bridge window. Otherwise, we can see strange
3292                  * issues. One of them is EEH error observed on Garrison.
3293                  *
3294                  * Exclude top 1MB region which is the minimal alignment of
3295                  * 32-bits bridge window.
3296                  */
3297                 if (msi_region) {
3298                         r->end += 0x10000;
3299                         r->end -= 0x100000;
3300                 }
3301         }
3302 }
3303
3304 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3305 {
3306         struct pci_controller *hose = pci_bus_to_host(bus);
3307         struct pnv_phb *phb = hose->private_data;
3308         struct pci_dev *bridge = bus->self;
3309         struct pnv_ioda_pe *pe;
3310         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3311
3312         /* Extend bridge's windows if necessary */
3313         pnv_pci_fixup_bridge_resources(bus, type);
3314
3315         /* The PE for root bus should be realized before any one else */
3316         if (!phb->ioda.root_pe_populated) {
3317                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3318                 if (pe) {
3319                         phb->ioda.root_pe_idx = pe->pe_number;
3320                         phb->ioda.root_pe_populated = true;
3321                 }
3322         }
3323
3324         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3325         if (list_empty(&bus->devices))
3326                 return;
3327
3328         /* Reserve PEs according to used M64 resources */
3329         pnv_ioda_reserve_m64_pe(bus, NULL, all);
3330
3331         /*
3332          * Assign PE. We might run here because of partial hotplug.
3333          * For the case, we just pick up the existing PE and should
3334          * not allocate resources again.
3335          */
3336         pe = pnv_ioda_setup_bus_PE(bus, all);
3337         if (!pe)
3338                 return;
3339
3340         pnv_ioda_setup_pe_seg(pe);
3341         switch (phb->type) {
3342         case PNV_PHB_IODA1:
3343                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3344                 break;
3345         case PNV_PHB_IODA2:
3346                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3347                 break;
3348         default:
3349                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3350                         __func__, phb->hose->global_number, phb->type);
3351         }
3352 }
3353
3354 static resource_size_t pnv_pci_default_alignment(void)
3355 {
3356         return PAGE_SIZE;
3357 }
3358
3359 #ifdef CONFIG_PCI_IOV
3360 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3361                                                       int resno)
3362 {
3363         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3364         struct pnv_phb *phb = hose->private_data;
3365         struct pci_dn *pdn = pci_get_pdn(pdev);
3366         resource_size_t align;
3367
3368         /*
3369          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3370          * SR-IOV. While from hardware perspective, the range mapped by M64
3371          * BAR should be size aligned.
3372          *
3373          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3374          * powernv-specific hardware restriction is gone. But if just use the
3375          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3376          * in one segment of M64 #15, which introduces the PE conflict between
3377          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3378          * m64_segsize.
3379          *
3380          * This function returns the total IOV BAR size if M64 BAR is in
3381          * Shared PE mode or just VF BAR size if not.
3382          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3383          * M64 segment size if IOV BAR size is less.
3384          */
3385         align = pci_iov_resource_size(pdev, resno);
3386         if (!pdn->vfs_expanded)
3387                 return align;
3388         if (pdn->m64_single_mode)
3389                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3390
3391         return pdn->vfs_expanded * align;
3392 }
3393 #endif /* CONFIG_PCI_IOV */
3394
3395 /* Prevent enabling devices for which we couldn't properly
3396  * assign a PE
3397  */
3398 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3399 {
3400         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3401         struct pnv_phb *phb = hose->private_data;
3402         struct pci_dn *pdn;
3403
3404         /* The function is probably called while the PEs have
3405          * not be created yet. For example, resource reassignment
3406          * during PCI probe period. We just skip the check if
3407          * PEs isn't ready.
3408          */
3409         if (!phb->initialized)
3410                 return true;
3411
3412         pdn = pci_get_pdn(dev);
3413         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3414                 return false;
3415
3416         return true;
3417 }
3418
3419 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3420                                        int num)
3421 {
3422         struct pnv_ioda_pe *pe = container_of(table_group,
3423                                               struct pnv_ioda_pe, table_group);
3424         struct pnv_phb *phb = pe->phb;
3425         unsigned int idx;
3426         long rc;
3427
3428         pe_info(pe, "Removing DMA window #%d\n", num);
3429         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3430                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3431                         continue;
3432
3433                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3434                                                 idx, 0, 0ul, 0ul, 0ul);
3435                 if (rc != OPAL_SUCCESS) {
3436                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3437                                 rc, idx);
3438                         return rc;
3439                 }
3440
3441                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3442         }
3443
3444         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3445         return OPAL_SUCCESS;
3446 }
3447
3448 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3449 {
3450         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3451         struct iommu_table *tbl = pe->table_group.tables[0];
3452         int64_t rc;
3453
3454         if (!weight)
3455                 return;
3456
3457         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3458         if (rc != OPAL_SUCCESS)
3459                 return;
3460
3461         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3462         if (pe->table_group.group) {
3463                 iommu_group_put(pe->table_group.group);
3464                 WARN_ON(pe->table_group.group);
3465         }
3466
3467         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3468         iommu_tce_table_put(tbl);
3469 }
3470
3471 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3472 {
3473         struct iommu_table *tbl = pe->table_group.tables[0];
3474         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3475 #ifdef CONFIG_IOMMU_API
3476         int64_t rc;
3477 #endif
3478
3479         if (!weight)
3480                 return;
3481
3482 #ifdef CONFIG_IOMMU_API
3483         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3484         if (rc)
3485                 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
3486 #endif
3487
3488         pnv_pci_ioda2_set_bypass(pe, false);
3489         if (pe->table_group.group) {
3490                 iommu_group_put(pe->table_group.group);
3491                 WARN_ON(pe->table_group.group);
3492         }
3493
3494         iommu_tce_table_put(tbl);
3495 }
3496
3497 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3498                                  unsigned short win,
3499                                  unsigned int *map)
3500 {
3501         struct pnv_phb *phb = pe->phb;
3502         int idx;
3503         int64_t rc;
3504
3505         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3506                 if (map[idx] != pe->pe_number)
3507                         continue;
3508
3509                 if (win == OPAL_M64_WINDOW_TYPE)
3510                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3511                                         phb->ioda.reserved_pe_idx, win,
3512                                         idx / PNV_IODA1_M64_SEGS,
3513                                         idx % PNV_IODA1_M64_SEGS);
3514                 else
3515                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3516                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3517
3518                 if (rc != OPAL_SUCCESS)
3519                         pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
3520                                 rc, win, idx);
3521
3522                 map[idx] = IODA_INVALID_PE;
3523         }
3524 }
3525
3526 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3527 {
3528         struct pnv_phb *phb = pe->phb;
3529
3530         if (phb->type == PNV_PHB_IODA1) {
3531                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3532                                      phb->ioda.io_segmap);
3533                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3534                                      phb->ioda.m32_segmap);
3535                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3536                                      phb->ioda.m64_segmap);
3537         } else if (phb->type == PNV_PHB_IODA2) {
3538                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3539                                      phb->ioda.m32_segmap);
3540         }
3541 }
3542
3543 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3544 {
3545         struct pnv_phb *phb = pe->phb;
3546         struct pnv_ioda_pe *slave, *tmp;
3547
3548         list_del(&pe->list);
3549         switch (phb->type) {
3550         case PNV_PHB_IODA1:
3551                 pnv_pci_ioda1_release_pe_dma(pe);
3552                 break;
3553         case PNV_PHB_IODA2:
3554                 pnv_pci_ioda2_release_pe_dma(pe);
3555                 break;
3556         default:
3557                 WARN_ON(1);
3558         }
3559
3560         pnv_ioda_release_pe_seg(pe);
3561         pnv_ioda_deconfigure_pe(pe->phb, pe);
3562
3563         /* Release slave PEs in the compound PE */
3564         if (pe->flags & PNV_IODA_PE_MASTER) {
3565                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3566                         list_del(&slave->list);
3567                         pnv_ioda_free_pe(slave);
3568                 }
3569         }
3570
3571         /*
3572          * The PE for root bus can be removed because of hotplug in EEH
3573          * recovery for fenced PHB error. We need to mark the PE dead so
3574          * that it can be populated again in PCI hot add path. The PE
3575          * shouldn't be destroyed as it's the global reserved resource.
3576          */
3577         if (phb->ioda.root_pe_populated &&
3578             phb->ioda.root_pe_idx == pe->pe_number)
3579                 phb->ioda.root_pe_populated = false;
3580         else
3581                 pnv_ioda_free_pe(pe);
3582 }
3583
3584 static void pnv_pci_release_device(struct pci_dev *pdev)
3585 {
3586         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3587         struct pnv_phb *phb = hose->private_data;
3588         struct pci_dn *pdn = pci_get_pdn(pdev);
3589         struct pnv_ioda_pe *pe;
3590
3591         if (pdev->is_virtfn)
3592                 return;
3593
3594         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3595                 return;
3596
3597         /*
3598          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3599          * isn't removed and added afterwards in this scenario. We should
3600          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3601          * device count is decreased on removing devices while failing to
3602          * be increased on adding devices. It leads to unbalanced PE's device
3603          * count and eventually make normal PCI hotplug path broken.
3604          */
3605         pe = &phb->ioda.pe_array[pdn->pe_number];
3606         pdn->pe_number = IODA_INVALID_PE;
3607
3608         WARN_ON(--pe->device_count < 0);
3609         if (pe->device_count == 0)
3610                 pnv_ioda_release_pe(pe);
3611 }
3612
3613 static void pnv_npu_disable_device(struct pci_dev *pdev)
3614 {
3615         struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3616         struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3617
3618         if (eehpe && eeh_ops && eeh_ops->reset)
3619                 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3620 }
3621
3622 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3623 {
3624         struct pnv_phb *phb = hose->private_data;
3625
3626         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3627                        OPAL_ASSERT_RESET);
3628 }
3629
3630 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3631         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3632         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3633         .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
3634         .setup_msi_irqs         = pnv_setup_msi_irqs,
3635         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3636         .enable_device_hook     = pnv_pci_enable_device_hook,
3637         .release_device         = pnv_pci_release_device,
3638         .window_alignment       = pnv_pci_window_alignment,
3639         .setup_bridge           = pnv_pci_setup_bridge,
3640         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3641         .shutdown               = pnv_pci_ioda_shutdown,
3642 };
3643
3644 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3645         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3646         .setup_msi_irqs         = pnv_setup_msi_irqs,
3647         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3648         .enable_device_hook     = pnv_pci_enable_device_hook,
3649         .window_alignment       = pnv_pci_window_alignment,
3650         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3651         .shutdown               = pnv_pci_ioda_shutdown,
3652         .disable_device         = pnv_npu_disable_device,
3653 };
3654
3655 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3656         .enable_device_hook     = pnv_pci_enable_device_hook,
3657         .window_alignment       = pnv_pci_window_alignment,
3658         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3659         .shutdown               = pnv_pci_ioda_shutdown,
3660 };
3661
3662 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3663                                          u64 hub_id, int ioda_type)
3664 {
3665         struct pci_controller *hose;
3666         struct pnv_phb *phb;
3667         unsigned long size, m64map_off, m32map_off, pemap_off;
3668         unsigned long iomap_off = 0, dma32map_off = 0;
3669         struct resource r;
3670         const __be64 *prop64;
3671         const __be32 *prop32;
3672         int len;
3673         unsigned int segno;
3674         u64 phb_id;
3675         void *aux;
3676         long rc;
3677
3678         if (!of_device_is_available(np))
3679                 return;
3680
3681         pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3682
3683         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3684         if (!prop64) {
3685                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3686                 return;
3687         }
3688         phb_id = be64_to_cpup(prop64);
3689         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3690
3691         phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3692         if (!phb)
3693                 panic("%s: Failed to allocate %zu bytes\n", __func__,
3694                       sizeof(*phb));
3695
3696         /* Allocate PCI controller */
3697         phb->hose = hose = pcibios_alloc_controller(np);
3698         if (!phb->hose) {
3699                 pr_err("  Can't allocate PCI controller for %pOF\n",
3700                        np);
3701                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3702                 return;
3703         }
3704
3705         spin_lock_init(&phb->lock);
3706         prop32 = of_get_property(np, "bus-range", &len);
3707         if (prop32 && len == 8) {
3708                 hose->first_busno = be32_to_cpu(prop32[0]);
3709                 hose->last_busno = be32_to_cpu(prop32[1]);
3710         } else {
3711                 pr_warn("  Broken <bus-range> on %pOF\n", np);
3712                 hose->first_busno = 0;
3713                 hose->last_busno = 0xff;
3714         }
3715         hose->private_data = phb;
3716         phb->hub_id = hub_id;
3717         phb->opal_id = phb_id;
3718         phb->type = ioda_type;
3719         mutex_init(&phb->ioda.pe_alloc_mutex);
3720
3721         /* Detect specific models for error handling */
3722         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3723                 phb->model = PNV_PHB_MODEL_P7IOC;
3724         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3725                 phb->model = PNV_PHB_MODEL_PHB3;
3726         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3727                 phb->model = PNV_PHB_MODEL_NPU;
3728         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3729                 phb->model = PNV_PHB_MODEL_NPU2;
3730         else
3731                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3732
3733         /* Initialize diagnostic data buffer */
3734         prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3735         if (prop32)
3736                 phb->diag_data_size = be32_to_cpup(prop32);
3737         else
3738                 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3739
3740         phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3741         if (!phb->diag_data)
3742                 panic("%s: Failed to allocate %u bytes\n", __func__,
3743                       phb->diag_data_size);
3744
3745         /* Parse 32-bit and IO ranges (if any) */
3746         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3747
3748         /* Get registers */
3749         if (!of_address_to_resource(np, 0, &r)) {
3750                 phb->regs_phys = r.start;
3751                 phb->regs = ioremap(r.start, resource_size(&r));
3752                 if (phb->regs == NULL)
3753                         pr_err("  Failed to map registers !\n");
3754         }
3755
3756         /* Initialize more IODA stuff */
3757         phb->ioda.total_pe_num = 1;
3758         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3759         if (prop32)
3760                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3761         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3762         if (prop32)
3763                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3764
3765         /* Invalidate RID to PE# mapping */
3766         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3767                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3768
3769         /* Parse 64-bit MMIO range */
3770         pnv_ioda_parse_m64_window(phb);
3771
3772         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3773         /* FW Has already off top 64k of M32 space (MSI space) */
3774         phb->ioda.m32_size += 0x10000;
3775
3776         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3777         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3778         phb->ioda.io_size = hose->pci_io_size;
3779         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3780         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3781
3782         /* Calculate how many 32-bit TCE segments we have */
3783         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3784                                 PNV_IODA1_DMA32_SEGSIZE;
3785
3786         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3787         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3788                         sizeof(unsigned long));
3789         m64map_off = size;
3790         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3791         m32map_off = size;
3792         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3793         if (phb->type == PNV_PHB_IODA1) {
3794                 iomap_off = size;
3795                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3796                 dma32map_off = size;
3797                 size += phb->ioda.dma32_count *
3798                         sizeof(phb->ioda.dma32_segmap[0]);
3799         }
3800         pemap_off = size;
3801         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3802         aux = memblock_alloc(size, SMP_CACHE_BYTES);
3803         if (!aux)
3804                 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3805         phb->ioda.pe_alloc = aux;
3806         phb->ioda.m64_segmap = aux + m64map_off;
3807         phb->ioda.m32_segmap = aux + m32map_off;
3808         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3809                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3810                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3811         }
3812         if (phb->type == PNV_PHB_IODA1) {
3813                 phb->ioda.io_segmap = aux + iomap_off;
3814                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3815                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3816
3817                 phb->ioda.dma32_segmap = aux + dma32map_off;
3818                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3819                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3820         }
3821         phb->ioda.pe_array = aux + pemap_off;
3822
3823         /*
3824          * Choose PE number for root bus, which shouldn't have
3825          * M64 resources consumed by its child devices. To pick
3826          * the PE number adjacent to the reserved one if possible.
3827          */
3828         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3829         if (phb->ioda.reserved_pe_idx == 0) {
3830                 phb->ioda.root_pe_idx = 1;
3831                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3832         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3833                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3834                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3835         } else {
3836                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3837         }
3838
3839         INIT_LIST_HEAD(&phb->ioda.pe_list);
3840         mutex_init(&phb->ioda.pe_list_mutex);
3841
3842         /* Calculate how many 32-bit TCE segments we have */
3843         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3844                                 PNV_IODA1_DMA32_SEGSIZE;
3845
3846 #if 0 /* We should really do that ... */
3847         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3848                                          window_type,
3849                                          window_num,
3850                                          starting_real_address,
3851                                          starting_pci_address,
3852                                          segment_size);
3853 #endif
3854
3855         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3856                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3857                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3858         if (phb->ioda.m64_size)
3859                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3860                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3861         if (phb->ioda.io_size)
3862                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3863                         phb->ioda.io_size, phb->ioda.io_segsize);
3864
3865
3866         phb->hose->ops = &pnv_pci_ops;
3867         phb->get_pe_state = pnv_ioda_get_pe_state;
3868         phb->freeze_pe = pnv_ioda_freeze_pe;
3869         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3870
3871         /* Setup MSI support */
3872         pnv_pci_init_ioda_msis(phb);
3873
3874         /*
3875          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3876          * to let the PCI core do resource assignment. It's supposed
3877          * that the PCI core will do correct I/O and MMIO alignment
3878          * for the P2P bridge bars so that each PCI bus (excluding
3879          * the child P2P bridges) can form individual PE.
3880          */
3881         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3882
3883         switch (phb->type) {
3884         case PNV_PHB_NPU_NVLINK:
3885                 hose->controller_ops = pnv_npu_ioda_controller_ops;
3886                 break;
3887         case PNV_PHB_NPU_OCAPI:
3888                 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3889                 break;
3890         default:
3891                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3892                 hose->controller_ops = pnv_pci_ioda_controller_ops;
3893         }
3894
3895         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3896
3897 #ifdef CONFIG_PCI_IOV
3898         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
3899         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3900         ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3901         ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3902 #endif
3903
3904         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3905
3906         /* Reset IODA tables to a clean state */
3907         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3908         if (rc)
3909                 pr_warn("  OPAL Error %ld performing IODA table reset !\n", rc);
3910
3911         /*
3912          * If we're running in kdump kernel, the previous kernel never
3913          * shutdown PCI devices correctly. We already got IODA table
3914          * cleaned out. So we have to issue PHB reset to stop all PCI
3915          * transactions from previous kernel. The ppc_pci_reset_phbs
3916          * kernel parameter will force this reset too. Additionally,
3917          * if the IODA reset above failed then use a bigger hammer.
3918          * This can happen if we get a PHB fatal error in very early
3919          * boot.
3920          */
3921         if (is_kdump_kernel() || pci_reset_phbs || rc) {
3922                 pr_info("  Issue PHB reset ...\n");
3923                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3924                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3925         }
3926
3927         /* Remove M64 resource if we can't configure it successfully */
3928         if (!phb->init_m64 || phb->init_m64(phb))
3929                 hose->mem_resources[1].flags = 0;
3930 }
3931
3932 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3933 {
3934         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3935 }
3936
3937 void __init pnv_pci_init_npu_phb(struct device_node *np)
3938 {
3939         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3940 }
3941
3942 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3943 {
3944         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3945 }
3946
3947 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3948 {
3949         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3950         struct pnv_phb *phb = hose->private_data;
3951
3952         if (!machine_is(powernv))
3953                 return;
3954
3955         if (phb->type == PNV_PHB_NPU_OCAPI)
3956                 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3957 }
3958 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3959
3960 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3961 {
3962         struct device_node *phbn;
3963         const __be64 *prop64;
3964         u64 hub_id;
3965
3966         pr_info("Probing IODA IO-Hub %pOF\n", np);
3967
3968         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3969         if (!prop64) {
3970                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3971                 return;
3972         }
3973         hub_id = be64_to_cpup(prop64);
3974         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3975
3976         /* Count child PHBs */
3977         for_each_child_of_node(np, phbn) {
3978                 /* Look for IODA1 PHBs */
3979                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3980                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3981         }
3982 }