1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support PCI/PCIe on PowerNV platforms
5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/init.h>
16 #include <linux/memblock.h>
17 #include <linux/irq.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
21 #include <linux/rculist.h>
22 #include <linux/sizes.h>
24 #include <asm/sections.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
32 #include <asm/iommu.h>
35 #include <asm/debugfs.h>
36 #include <asm/firmware.h>
37 #include <asm/pnv-pci.h>
38 #include <asm/mmzone.h>
40 #include <misc/cxl-base.h>
44 #include "../../../../drivers/pci/pci.h"
46 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
47 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
48 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
50 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54 static void pnv_pci_configure_bus(struct pci_bus *bus);
56 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
68 if (pe->flags & PNV_IODA_PE_DEV)
69 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
70 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
71 sprintf(pfix, "%04x:%02x ",
72 pci_domain_nr(pe->pbus), pe->pbus->number);
74 else if (pe->flags & PNV_IODA_PE_VF)
75 sprintf(pfix, "%04x:%02x:%2x.%d",
76 pci_domain_nr(pe->parent_dev->bus),
77 (pe->rid & 0xff00) >> 8,
78 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
79 #endif /* CONFIG_PCI_IOV*/
81 printk("%spci %s: [PE# %.2x] %pV",
82 level, pfix, pe->pe_number, &vaf);
87 static bool pnv_iommu_bypass_disabled __read_mostly;
88 static bool pci_reset_phbs __read_mostly;
90 static int __init iommu_setup(char *str)
96 if (!strncmp(str, "nobypass", 8)) {
97 pnv_iommu_bypass_disabled = true;
98 pr_info("PowerNV: IOMMU bypass window disabled.\n");
101 str += strcspn(str, ",");
108 early_param("iommu", iommu_setup);
110 static int __init pci_reset_phbs_setup(char *str)
112 pci_reset_phbs = true;
116 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
118 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
122 phb->ioda.pe_array[pe_no].phb = phb;
123 phb->ioda.pe_array[pe_no].pe_number = pe_no;
124 phb->ioda.pe_array[pe_no].dma_setup_done = false;
127 * Clear the PE frozen state as it might be put into frozen state
128 * in the last PCI remove path. It's not harmful to do so when the
129 * PE is already in unfrozen state.
131 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
132 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
133 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
134 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
135 __func__, rc, phb->hose->global_number, pe_no);
137 return &phb->ioda.pe_array[pe_no];
140 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
142 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
143 pr_warn("%s: Invalid PE %x on PHB#%x\n",
144 __func__, pe_no, phb->hose->global_number);
148 mutex_lock(&phb->ioda.pe_alloc_mutex);
149 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
150 pr_debug("%s: PE %x was reserved on PHB#%x\n",
151 __func__, pe_no, phb->hose->global_number);
152 mutex_unlock(&phb->ioda.pe_alloc_mutex);
154 pnv_ioda_init_pe(phb, pe_no);
157 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count)
159 struct pnv_ioda_pe *ret = NULL;
162 mutex_lock(&phb->ioda.pe_alloc_mutex);
164 /* scan backwards for a run of @count cleared bits */
165 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
166 if (test_bit(pe, phb->ioda.pe_alloc)) {
178 for (i = pe; i < pe + count; i++) {
179 set_bit(i, phb->ioda.pe_alloc);
180 pnv_ioda_init_pe(phb, i);
182 ret = &phb->ioda.pe_array[pe];
185 mutex_unlock(&phb->ioda.pe_alloc_mutex);
189 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
191 struct pnv_phb *phb = pe->phb;
192 unsigned int pe_num = pe->pe_number;
195 WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */
197 memset(pe, 0, sizeof(struct pnv_ioda_pe));
199 mutex_lock(&phb->ioda.pe_alloc_mutex);
200 clear_bit(pe_num, phb->ioda.pe_alloc);
201 mutex_unlock(&phb->ioda.pe_alloc_mutex);
204 /* The default M64 BAR is shared by all PEs */
205 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
211 /* Configure the default M64 BAR */
212 rc = opal_pci_set_phb_mem_window(phb->opal_id,
213 OPAL_M64_WINDOW_TYPE,
214 phb->ioda.m64_bar_idx,
218 if (rc != OPAL_SUCCESS) {
219 desc = "configuring";
223 /* Enable the default M64 BAR */
224 rc = opal_pci_phb_mmio_enable(phb->opal_id,
225 OPAL_M64_WINDOW_TYPE,
226 phb->ioda.m64_bar_idx,
227 OPAL_ENABLE_M64_SPLIT);
228 if (rc != OPAL_SUCCESS) {
234 * Exclude the segments for reserved and root bus PE, which
235 * are first or last two PEs.
237 r = &phb->hose->mem_resources[1];
238 if (phb->ioda.reserved_pe_idx == 0)
239 r->start += (2 * phb->ioda.m64_segsize);
240 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
241 r->end -= (2 * phb->ioda.m64_segsize);
243 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
244 phb->ioda.reserved_pe_idx);
249 pr_warn(" Failure %lld %s M64 BAR#%d\n",
250 rc, desc, phb->ioda.m64_bar_idx);
251 opal_pci_phb_mmio_enable(phb->opal_id,
252 OPAL_M64_WINDOW_TYPE,
253 phb->ioda.m64_bar_idx,
258 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
259 unsigned long *pe_bitmap)
261 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
263 resource_size_t base, sgsz, start, end;
266 base = phb->ioda.m64_base;
267 sgsz = phb->ioda.m64_segsize;
268 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
269 r = &pdev->resource[i];
270 if (!r->parent || !pnv_pci_is_m64(phb, r))
273 start = ALIGN_DOWN(r->start - base, sgsz);
274 end = ALIGN(r->end - base, sgsz);
275 for (segno = start / sgsz; segno < end / sgsz; segno++) {
277 set_bit(segno, pe_bitmap);
279 pnv_ioda_reserve_pe(phb, segno);
284 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
290 * There are 16 M64 BARs, each of which has 8 segments. So
291 * there are as many M64 segments as the maximum number of
294 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
295 unsigned long base, segsz = phb->ioda.m64_segsize;
298 base = phb->ioda.m64_base +
299 index * PNV_IODA1_M64_SEGS * segsz;
300 rc = opal_pci_set_phb_mem_window(phb->opal_id,
301 OPAL_M64_WINDOW_TYPE, index, base, 0,
302 PNV_IODA1_M64_SEGS * segsz);
303 if (rc != OPAL_SUCCESS) {
304 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
305 rc, phb->hose->global_number, index);
309 rc = opal_pci_phb_mmio_enable(phb->opal_id,
310 OPAL_M64_WINDOW_TYPE, index,
311 OPAL_ENABLE_M64_SPLIT);
312 if (rc != OPAL_SUCCESS) {
313 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
314 rc, phb->hose->global_number, index);
319 for (index = 0; index < phb->ioda.total_pe_num; index++) {
323 * P7IOC supports M64DT, which helps mapping M64 segment
324 * to one particular PE#. However, PHB3 has fixed mapping
325 * between M64 segment and PE#. In order to have same logic
326 * for P7IOC and PHB3, we enforce fixed mapping between M64
327 * segment and PE# on P7IOC.
329 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
330 index, OPAL_M64_WINDOW_TYPE,
331 index / PNV_IODA1_M64_SEGS,
332 index % PNV_IODA1_M64_SEGS);
333 if (rc != OPAL_SUCCESS) {
334 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
335 __func__, rc, phb->hose->global_number,
342 * Exclude the segments for reserved and root bus PE, which
343 * are first or last two PEs.
345 r = &phb->hose->mem_resources[1];
346 if (phb->ioda.reserved_pe_idx == 0)
347 r->start += (2 * phb->ioda.m64_segsize);
348 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
349 r->end -= (2 * phb->ioda.m64_segsize);
351 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
352 phb->ioda.reserved_pe_idx, phb->hose->global_number);
357 for ( ; index >= 0; index--)
358 opal_pci_phb_mmio_enable(phb->opal_id,
359 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
364 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
365 unsigned long *pe_bitmap,
368 struct pci_dev *pdev;
370 list_for_each_entry(pdev, &bus->devices, bus_list) {
371 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
373 if (all && pdev->subordinate)
374 pnv_ioda_reserve_m64_pe(pdev->subordinate,
379 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
381 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
382 struct pnv_ioda_pe *master_pe, *pe;
383 unsigned long size, *pe_alloc;
386 /* Root bus shouldn't use M64 */
387 if (pci_is_root_bus(bus))
390 /* Allocate bitmap */
391 size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
392 pe_alloc = kzalloc(size, GFP_KERNEL);
394 pr_warn("%s: Out of memory !\n",
399 /* Figure out reserved PE numbers by the PE */
400 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
403 * the current bus might not own M64 window and that's all
404 * contributed by its child buses. For the case, we needn't
405 * pick M64 dependent PE#.
407 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
413 * Figure out the master PE and put all slave PEs to master
414 * PE's list to form compound PE.
418 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
419 phb->ioda.total_pe_num) {
420 pe = &phb->ioda.pe_array[i];
422 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
424 pe->flags |= PNV_IODA_PE_MASTER;
425 INIT_LIST_HEAD(&pe->slaves);
428 pe->flags |= PNV_IODA_PE_SLAVE;
429 pe->master = master_pe;
430 list_add_tail(&pe->list, &master_pe->slaves);
438 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
440 struct pci_controller *hose = phb->hose;
441 struct device_node *dn = hose->dn;
442 struct resource *res;
447 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
448 pr_info(" Not support M64 window\n");
452 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
453 pr_info(" Firmware too old to support M64 window\n");
457 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
459 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
465 * Find the available M64 BAR range and pickup the last one for
466 * covering the whole 64-bits space. We support only one range.
468 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
470 /* In absence of the property, assume 0..15 */
474 /* We only support 64 bits in our allocator */
475 if (m64_range[1] > 63) {
476 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
477 __func__, m64_range[1], phb->hose->global_number);
480 /* Empty range, no m64 */
481 if (m64_range[1] <= m64_range[0]) {
482 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
483 __func__, phb->hose->global_number);
487 /* Configure M64 informations */
488 res = &hose->mem_resources[1];
489 res->name = dn->full_name;
490 res->start = of_translate_address(dn, r + 2);
491 res->end = res->start + of_read_number(r + 4, 2) - 1;
492 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
493 pci_addr = of_read_number(r, 2);
494 hose->mem_offset[1] = res->start - pci_addr;
496 phb->ioda.m64_size = resource_size(res);
497 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
498 phb->ioda.m64_base = pci_addr;
500 /* This lines up nicely with the display from processing OF ranges */
501 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
502 res->start, res->end, pci_addr, m64_range[0],
503 m64_range[0] + m64_range[1] - 1);
505 /* Mark all M64 used up by default */
506 phb->ioda.m64_bar_alloc = (unsigned long)-1;
508 /* Use last M64 BAR to cover M64 window */
510 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
512 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
514 /* Mark remaining ones free */
515 for (i = m64_range[0]; i < m64_range[1]; i++)
516 clear_bit(i, &phb->ioda.m64_bar_alloc);
519 * Setup init functions for M64 based on IODA version, IODA3 uses
522 if (phb->type == PNV_PHB_IODA1)
523 phb->init_m64 = pnv_ioda1_init_m64;
525 phb->init_m64 = pnv_ioda2_init_m64;
528 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
530 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
531 struct pnv_ioda_pe *slave;
534 /* Fetch master PE */
535 if (pe->flags & PNV_IODA_PE_SLAVE) {
537 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
540 pe_no = pe->pe_number;
543 /* Freeze master PE */
544 rc = opal_pci_eeh_freeze_set(phb->opal_id,
546 OPAL_EEH_ACTION_SET_FREEZE_ALL);
547 if (rc != OPAL_SUCCESS) {
548 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
549 __func__, rc, phb->hose->global_number, pe_no);
553 /* Freeze slave PEs */
554 if (!(pe->flags & PNV_IODA_PE_MASTER))
557 list_for_each_entry(slave, &pe->slaves, list) {
558 rc = opal_pci_eeh_freeze_set(phb->opal_id,
560 OPAL_EEH_ACTION_SET_FREEZE_ALL);
561 if (rc != OPAL_SUCCESS)
562 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
563 __func__, rc, phb->hose->global_number,
568 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
570 struct pnv_ioda_pe *pe, *slave;
574 pe = &phb->ioda.pe_array[pe_no];
575 if (pe->flags & PNV_IODA_PE_SLAVE) {
577 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
578 pe_no = pe->pe_number;
581 /* Clear frozen state for master PE */
582 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
583 if (rc != OPAL_SUCCESS) {
584 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
585 __func__, rc, opt, phb->hose->global_number, pe_no);
589 if (!(pe->flags & PNV_IODA_PE_MASTER))
592 /* Clear frozen state for slave PEs */
593 list_for_each_entry(slave, &pe->slaves, list) {
594 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
597 if (rc != OPAL_SUCCESS) {
598 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
599 __func__, rc, opt, phb->hose->global_number,
608 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
610 struct pnv_ioda_pe *slave, *pe;
611 u8 fstate = 0, state;
615 /* Sanity check on PE number */
616 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
617 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
620 * Fetch the master PE and the PE instance might be
621 * not initialized yet.
623 pe = &phb->ioda.pe_array[pe_no];
624 if (pe->flags & PNV_IODA_PE_SLAVE) {
626 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
627 pe_no = pe->pe_number;
630 /* Check the master PE */
631 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
632 &state, &pcierr, NULL);
633 if (rc != OPAL_SUCCESS) {
634 pr_warn("%s: Failure %lld getting "
635 "PHB#%x-PE#%x state\n",
637 phb->hose->global_number, pe_no);
638 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
641 /* Check the slave PE */
642 if (!(pe->flags & PNV_IODA_PE_MASTER))
645 list_for_each_entry(slave, &pe->slaves, list) {
646 rc = opal_pci_eeh_freeze_status(phb->opal_id,
651 if (rc != OPAL_SUCCESS) {
652 pr_warn("%s: Failure %lld getting "
653 "PHB#%x-PE#%x state\n",
655 phb->hose->global_number, slave->pe_number);
656 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
660 * Override the result based on the ascending
670 struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn)
672 int pe_number = phb->ioda.pe_rmap[bdfn];
674 if (pe_number == IODA_INVALID_PE)
677 return &phb->ioda.pe_array[pe_number];
680 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
682 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
683 struct pci_dn *pdn = pci_get_pdn(dev);
687 if (pdn->pe_number == IODA_INVALID_PE)
689 return &phb->ioda.pe_array[pdn->pe_number];
692 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
693 struct pnv_ioda_pe *parent,
694 struct pnv_ioda_pe *child,
697 const char *desc = is_add ? "adding" : "removing";
698 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
699 OPAL_REMOVE_PE_FROM_DOMAIN;
700 struct pnv_ioda_pe *slave;
703 /* Parent PE affects child PE */
704 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
705 child->pe_number, op);
706 if (rc != OPAL_SUCCESS) {
707 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
712 if (!(child->flags & PNV_IODA_PE_MASTER))
715 /* Compound case: parent PE affects slave PEs */
716 list_for_each_entry(slave, &child->slaves, list) {
717 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
718 slave->pe_number, op);
719 if (rc != OPAL_SUCCESS) {
720 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
729 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
730 struct pnv_ioda_pe *pe,
733 struct pnv_ioda_pe *slave;
734 struct pci_dev *pdev = NULL;
738 * Clear PE frozen state. If it's master PE, we need
739 * clear slave PE frozen state as well.
742 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
743 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
744 if (pe->flags & PNV_IODA_PE_MASTER) {
745 list_for_each_entry(slave, &pe->slaves, list)
746 opal_pci_eeh_freeze_clear(phb->opal_id,
748 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
753 * Associate PE in PELT. We need add the PE into the
754 * corresponding PELT-V as well. Otherwise, the error
755 * originated from the PE might contribute to other
758 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
762 /* For compound PEs, any one affects all of them */
763 if (pe->flags & PNV_IODA_PE_MASTER) {
764 list_for_each_entry(slave, &pe->slaves, list) {
765 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
771 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
772 pdev = pe->pbus->self;
773 else if (pe->flags & PNV_IODA_PE_DEV)
774 pdev = pe->pdev->bus->self;
775 #ifdef CONFIG_PCI_IOV
776 else if (pe->flags & PNV_IODA_PE_VF)
777 pdev = pe->parent_dev;
778 #endif /* CONFIG_PCI_IOV */
780 struct pci_dn *pdn = pci_get_pdn(pdev);
781 struct pnv_ioda_pe *parent;
783 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
784 parent = &phb->ioda.pe_array[pdn->pe_number];
785 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
790 pdev = pdev->bus->self;
796 static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
797 struct pnv_ioda_pe *pe,
798 struct pci_dev *parent)
803 struct pci_dn *pdn = pci_get_pdn(parent);
805 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
806 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
808 OPAL_REMOVE_PE_FROM_DOMAIN);
809 /* XXX What to do in case of error ? */
811 parent = parent->bus->self;
814 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
815 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
817 /* Disassociate PE in PELT */
818 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
819 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
821 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
824 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
826 struct pci_dev *parent;
827 uint8_t bcomp, dcomp, fcomp;
831 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
835 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
836 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
837 parent = pe->pbus->self;
838 if (pe->flags & PNV_IODA_PE_BUS_ALL)
839 count = resource_size(&pe->pbus->busn_res);
844 case 1: bcomp = OpalPciBusAll; break;
845 case 2: bcomp = OpalPciBus7Bits; break;
846 case 4: bcomp = OpalPciBus6Bits; break;
847 case 8: bcomp = OpalPciBus5Bits; break;
848 case 16: bcomp = OpalPciBus4Bits; break;
849 case 32: bcomp = OpalPciBus3Bits; break;
851 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
853 /* Do an exact match only */
854 bcomp = OpalPciBusAll;
856 rid_end = pe->rid + (count << 8);
858 #ifdef CONFIG_PCI_IOV
859 if (pe->flags & PNV_IODA_PE_VF)
860 parent = pe->parent_dev;
863 parent = pe->pdev->bus->self;
864 bcomp = OpalPciBusAll;
865 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
866 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
867 rid_end = pe->rid + 1;
870 /* Clear the reverse map */
871 for (rid = pe->rid; rid < rid_end; rid++)
872 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
875 * Release from all parents PELT-V. NPUs don't have a PELTV
878 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
879 pnv_ioda_unset_peltv(phb, pe, parent);
881 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
882 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
884 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
888 #ifdef CONFIG_PCI_IOV
889 pe->parent_dev = NULL;
895 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
897 uint8_t bcomp, dcomp, fcomp;
898 long rc, rid_end, rid;
900 /* Bus validation ? */
904 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
905 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
906 if (pe->flags & PNV_IODA_PE_BUS_ALL)
907 count = resource_size(&pe->pbus->busn_res);
912 case 1: bcomp = OpalPciBusAll; break;
913 case 2: bcomp = OpalPciBus7Bits; break;
914 case 4: bcomp = OpalPciBus6Bits; break;
915 case 8: bcomp = OpalPciBus5Bits; break;
916 case 16: bcomp = OpalPciBus4Bits; break;
917 case 32: bcomp = OpalPciBus3Bits; break;
919 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
921 /* Do an exact match only */
922 bcomp = OpalPciBusAll;
924 rid_end = pe->rid + (count << 8);
926 bcomp = OpalPciBusAll;
927 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
928 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
929 rid_end = pe->rid + 1;
933 * Associate PE in PELT. We need add the PE into the
934 * corresponding PELT-V as well. Otherwise, the error
935 * originated from the PE might contribute to other
938 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
939 bcomp, dcomp, fcomp, OPAL_MAP_PE);
941 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
946 * Configure PELTV. NPUs don't have a PELTV table so skip
947 * configuration on them.
949 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
950 pnv_ioda_set_peltv(phb, pe, true);
952 /* Setup reverse map */
953 for (rid = pe->rid; rid < rid_end; rid++)
954 phb->ioda.pe_rmap[rid] = pe->pe_number;
956 /* Setup one MVTs on IODA1 */
957 if (phb->type != PNV_PHB_IODA1) {
962 pe->mve_number = pe->pe_number;
963 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
964 if (rc != OPAL_SUCCESS) {
965 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
969 rc = opal_pci_set_mve_enable(phb->opal_id,
970 pe->mve_number, OPAL_ENABLE_MVE);
972 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
982 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
984 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
985 struct pci_dn *pdn = pci_get_pdn(dev);
986 struct pnv_ioda_pe *pe;
989 pr_err("%s: Device tree node not associated properly\n",
993 if (pdn->pe_number != IODA_INVALID_PE)
996 pe = pnv_ioda_alloc_pe(phb, 1);
998 pr_warn("%s: Not enough PE# available, disabling device\n",
1003 /* NOTE: We don't get a reference for the pointer in the PE
1004 * data structure, both the device and PE structures should be
1005 * destroyed at the same time. However, removing nvlink
1006 * devices will need some work.
1008 * At some point we want to remove the PDN completely anyways
1010 pdn->pe_number = pe->pe_number;
1011 pe->flags = PNV_IODA_PE_DEV;
1014 pe->mve_number = -1;
1015 pe->rid = dev->bus->number << 8 | pdn->devfn;
1018 pe_info(pe, "Associated device to PE\n");
1020 if (pnv_ioda_configure_pe(phb, pe)) {
1021 /* XXX What do we do here ? */
1022 pnv_ioda_free_pe(pe);
1023 pdn->pe_number = IODA_INVALID_PE;
1028 /* Put PE to the list */
1029 mutex_lock(&phb->ioda.pe_list_mutex);
1030 list_add_tail(&pe->list, &phb->ioda.pe_list);
1031 mutex_unlock(&phb->ioda.pe_list_mutex);
1036 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1037 * single PCI bus. Another one that contains the primary PCI bus and its
1038 * subordinate PCI devices and buses. The second type of PE is normally
1039 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1041 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1043 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
1044 struct pnv_ioda_pe *pe = NULL;
1045 unsigned int pe_num;
1048 * In partial hotplug case, the PE instance might be still alive.
1049 * We should reuse it instead of allocating a new one.
1051 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1052 if (WARN_ON(pe_num != IODA_INVALID_PE)) {
1053 pe = &phb->ioda.pe_array[pe_num];
1057 /* PE number for root bus should have been reserved */
1058 if (pci_is_root_bus(bus))
1059 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1061 /* Check if PE is determined by M64 */
1063 pe = pnv_ioda_pick_m64_pe(bus, all);
1065 /* The PE number isn't pinned by M64 */
1067 pe = pnv_ioda_alloc_pe(phb, 1);
1070 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1071 __func__, pci_domain_nr(bus), bus->number);
1075 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1078 pe->mve_number = -1;
1079 pe->rid = bus->busn_res.start << 8;
1082 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1083 &bus->busn_res.start, &bus->busn_res.end,
1086 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1087 &bus->busn_res.start, pe->pe_number);
1089 if (pnv_ioda_configure_pe(phb, pe)) {
1090 /* XXX What do we do here ? */
1091 pnv_ioda_free_pe(pe);
1096 /* Put PE to the list */
1097 list_add_tail(&pe->list, &phb->ioda.pe_list);
1102 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1104 int pe_num, found_pe = false, rc;
1106 struct pnv_ioda_pe *pe;
1107 struct pci_dev *gpu_pdev;
1108 struct pci_dn *npu_pdn;
1109 struct pnv_phb *phb = pci_bus_to_pnvhb(npu_pdev->bus);
1112 * Intentionally leak a reference on the npu device (for
1113 * nvlink only; this is not an opencapi path) to make sure it
1114 * never goes away, as it's been the case all along and some
1115 * work is needed otherwise.
1117 pci_dev_get(npu_pdev);
1120 * Due to a hardware errata PE#0 on the NPU is reserved for
1121 * error handling. This means we only have three PEs remaining
1122 * which need to be assigned to four links, implying some
1123 * links must share PEs.
1125 * To achieve this we assign PEs such that NPUs linking the
1126 * same GPU get assigned the same PE.
1128 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1129 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1130 pe = &phb->ioda.pe_array[pe_num];
1134 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1136 * This device has the same peer GPU so should
1137 * be assigned the same PE as the existing
1140 dev_info(&npu_pdev->dev,
1141 "Associating to existing PE %x\n", pe_num);
1142 npu_pdn = pci_get_pdn(npu_pdev);
1143 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1144 npu_pdn->pe_number = pe_num;
1145 phb->ioda.pe_rmap[rid] = pe->pe_number;
1148 /* Map the PE to this link */
1149 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1151 OPAL_COMPARE_RID_DEVICE_NUMBER,
1152 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1154 WARN_ON(rc != OPAL_SUCCESS);
1162 * Could not find an existing PE so allocate a new
1165 return pnv_ioda_setup_dev_PE(npu_pdev);
1170 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1172 struct pci_dev *pdev;
1174 list_for_each_entry(pdev, &bus->devices, bus_list)
1175 pnv_ioda_setup_npu_PE(pdev);
1178 static void pnv_pci_ioda_setup_nvlink(void)
1180 struct pci_controller *hose;
1181 struct pnv_phb *phb;
1182 struct pnv_ioda_pe *pe;
1184 list_for_each_entry(hose, &hose_list, list_node) {
1185 phb = hose->private_data;
1186 if (phb->type == PNV_PHB_NPU_NVLINK) {
1187 /* PE#0 is needed for error reporting */
1188 pnv_ioda_reserve_pe(phb, 0);
1189 pnv_ioda_setup_npu_PEs(hose->bus);
1190 if (phb->model == PNV_PHB_MODEL_NPU2)
1191 WARN_ON_ONCE(pnv_npu2_init(hose));
1194 list_for_each_entry(hose, &hose_list, list_node) {
1195 phb = hose->private_data;
1196 if (phb->type != PNV_PHB_IODA2)
1199 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1200 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1203 #ifdef CONFIG_IOMMU_API
1204 /* setup iommu groups so we can do nvlink pass-thru */
1205 pnv_pci_npu_setup_iommu_groups();
1209 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
1210 struct pnv_ioda_pe *pe);
1212 static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
1214 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1215 struct pci_dn *pdn = pci_get_pdn(pdev);
1216 struct pnv_ioda_pe *pe;
1218 /* Check if the BDFN for this device is associated with a PE yet */
1219 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
1221 /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */
1222 if (WARN_ON(pdev->is_virtfn))
1225 pnv_pci_configure_bus(pdev->bus);
1226 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
1227 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);
1231 * If we can't setup the IODA PE something has gone horribly
1232 * wrong and we can't enable DMA for the device.
1237 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);
1241 * We assume that bridges *probably* don't need to do any DMA so we can
1242 * skip allocating a TCE table, etc unless we get a non-bridge device.
1244 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {
1245 switch (phb->type) {
1247 pnv_pci_ioda1_setup_dma_pe(phb, pe);
1250 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1253 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
1254 __func__, phb->hose->global_number, phb->type);
1259 pdn->pe_number = pe->pe_number;
1262 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1263 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1264 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1266 /* PEs with a DMA weight of zero won't have a group */
1267 if (pe->table_group.group)
1268 iommu_add_device(&pe->table_group, &pdev->dev);
1272 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1274 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1275 * Devices can only access more than that if bit 59 of the PCI address is set
1276 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1277 * Many PCI devices are not capable of addressing that many bits, and as a
1278 * result are limited to the 4GB of virtual memory made available to 32-bit
1281 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1282 * devices by configuring the virtual memory past the first 4GB inaccessible
1283 * by 64-bit DMAs. This should only be used by devices that want more than
1284 * 4GB, and only on PEs that have no 32-bit devices.
1286 * Currently this will only work on PHB3 (POWER8).
1288 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1290 u64 window_size, table_size, tce_count, addr;
1291 struct page *table_pages;
1292 u64 tce_order = 28; /* 256MB TCEs */
1297 * Window size needs to be a power of two, but needs to account for
1298 * shifting memory by the 4GB offset required to skip 32bit space.
1300 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1301 tce_count = window_size >> tce_order;
1302 table_size = tce_count << 3;
1304 if (table_size < PAGE_SIZE)
1305 table_size = PAGE_SIZE;
1307 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1308 get_order(table_size));
1312 tces = page_address(table_pages);
1316 memset(tces, 0, table_size);
1318 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1319 tces[(addr + (1ULL << 32)) >> tce_order] =
1320 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1323 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1325 /* reconfigure window 0 */
1326 (pe->pe_number << 1) + 0,
1331 if (rc == OPAL_SUCCESS) {
1332 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1336 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1340 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1343 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1344 struct pci_dn *pdn = pci_get_pdn(pdev);
1345 struct pnv_ioda_pe *pe;
1347 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1350 pe = &phb->ioda.pe_array[pdn->pe_number];
1351 if (pe->tce_bypass_enabled) {
1352 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1353 if (dma_mask >= top)
1358 * If the device can't set the TCE bypass bit but still wants
1359 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1360 * bypass the 32-bit region and be usable for 64-bit DMAs.
1361 * The device needs to be able to address all of this space.
1363 if (dma_mask >> 32 &&
1364 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1365 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1366 (pe->device_count == 1 || !pe->pbus) &&
1367 phb->model == PNV_PHB_MODEL_PHB3) {
1368 /* Configure the bypass mode */
1369 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1372 /* 4GB offset bypasses 32-bit space */
1373 pdev->dev.archdata.dma_offset = (1ULL << 32);
1380 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1383 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1384 (phb->regs + 0x210);
1387 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1388 unsigned long index, unsigned long npages, bool rm)
1390 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1391 &tbl->it_group_list, struct iommu_table_group_link,
1393 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1394 struct pnv_ioda_pe, table_group);
1395 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1396 unsigned long start, end, inc;
1398 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1399 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1402 /* p7ioc-style invalidation, 2 TCEs per write */
1403 start |= (1ull << 63);
1404 end |= (1ull << 63);
1406 end |= inc - 1; /* round up end to be different than start */
1408 mb(); /* Ensure above stores are visible */
1409 while (start <= end) {
1411 __raw_rm_writeq_be(start, invalidate);
1413 __raw_writeq_be(start, invalidate);
1419 * The iommu layer will do another mb() for us on build()
1420 * and we don't care on free()
1424 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1425 long npages, unsigned long uaddr,
1426 enum dma_data_direction direction,
1427 unsigned long attrs)
1429 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1433 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1438 #ifdef CONFIG_IOMMU_API
1439 /* Common for IODA1 and IODA2 */
1440 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1441 unsigned long *hpa, enum dma_data_direction *direction,
1444 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode);
1448 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1451 pnv_tce_free(tbl, index, npages);
1453 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1456 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1457 .set = pnv_ioda1_tce_build,
1458 #ifdef CONFIG_IOMMU_API
1459 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1460 .tce_kill = pnv_pci_p7ioc_tce_invalidate,
1461 .useraddrptr = pnv_tce_useraddrptr,
1463 .clear = pnv_ioda1_tce_free,
1467 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1468 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1469 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1471 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1473 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1474 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1476 mb(); /* Ensure previous TCE table stores are visible */
1478 __raw_rm_writeq_be(val, invalidate);
1480 __raw_writeq_be(val, invalidate);
1483 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1485 /* 01xb - invalidate TCEs that match the specified PE# */
1486 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1487 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1489 mb(); /* Ensure above stores are visible */
1490 __raw_writeq_be(val, invalidate);
1493 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1494 unsigned shift, unsigned long index,
1495 unsigned long npages)
1497 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1498 unsigned long start, end, inc;
1500 /* We'll invalidate DMA address in PE scope */
1501 start = PHB3_TCE_KILL_INVAL_ONE;
1502 start |= (pe->pe_number & 0xFF);
1505 /* Figure out the start, end and step */
1506 start |= (index << shift);
1507 end |= ((index + npages - 1) << shift);
1508 inc = (0x1ull << shift);
1511 while (start <= end) {
1513 __raw_rm_writeq_be(start, invalidate);
1515 __raw_writeq_be(start, invalidate);
1520 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1522 struct pnv_phb *phb = pe->phb;
1524 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1525 pnv_pci_phb3_tce_invalidate_pe(pe);
1527 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1528 pe->pe_number, 0, 0, 0);
1531 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1532 unsigned long index, unsigned long npages, bool rm)
1534 struct iommu_table_group_link *tgl;
1536 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1537 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1538 struct pnv_ioda_pe, table_group);
1539 struct pnv_phb *phb = pe->phb;
1540 unsigned int shift = tbl->it_page_shift;
1543 * NVLink1 can use the TCE kill register directly as
1544 * it's the same as PHB3. NVLink2 is different and
1545 * should go via the OPAL call.
1547 if (phb->model == PNV_PHB_MODEL_NPU) {
1549 * The NVLink hardware does not support TCE kill
1550 * per TCE entry so we have to invalidate
1551 * the entire cache for it.
1553 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1556 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1557 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1560 opal_pci_tce_kill(phb->opal_id,
1561 OPAL_PCI_TCE_KILL_PAGES,
1562 pe->pe_number, 1u << shift,
1563 index << shift, npages);
1567 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1569 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
1570 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1572 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
1575 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1576 long npages, unsigned long uaddr,
1577 enum dma_data_direction direction,
1578 unsigned long attrs)
1580 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1584 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1589 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1592 pnv_tce_free(tbl, index, npages);
1594 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1597 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1598 .set = pnv_ioda2_tce_build,
1599 #ifdef CONFIG_IOMMU_API
1600 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1601 .tce_kill = pnv_pci_ioda2_tce_invalidate,
1602 .useraddrptr = pnv_tce_useraddrptr,
1604 .clear = pnv_ioda2_tce_free,
1606 .free = pnv_pci_ioda2_table_free_pages,
1609 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1611 unsigned int *weight = (unsigned int *)data;
1613 /* This is quite simplistic. The "base" weight of a device
1614 * is 10. 0 means no DMA is to be accounted for it.
1616 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1619 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1620 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1621 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1623 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1631 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1633 unsigned int weight = 0;
1635 /* SRIOV VF has same DMA32 weight as its PF */
1636 #ifdef CONFIG_PCI_IOV
1637 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1638 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1643 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
1644 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
1645 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
1646 struct pci_dev *pdev;
1648 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
1649 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
1650 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
1651 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
1657 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
1658 struct pnv_ioda_pe *pe)
1661 struct page *tce_mem = NULL;
1662 struct iommu_table *tbl;
1663 unsigned int weight, total_weight = 0;
1664 unsigned int tce32_segsz, base, segs, avail, i;
1668 /* XXX FIXME: Handle 64-bit only DMA devices */
1669 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1670 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1671 weight = pnv_pci_ioda_pe_dma_weight(pe);
1675 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
1677 segs = (weight * phb->ioda.dma32_count) / total_weight;
1682 * Allocate contiguous DMA32 segments. We begin with the expected
1683 * number of segments. With one more attempt, the number of DMA32
1684 * segments to be allocated is decreased by one until one segment
1685 * is allocated successfully.
1688 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
1689 for (avail = 0, i = base; i < base + segs; i++) {
1690 if (phb->ioda.dma32_segmap[i] ==
1701 pe_warn(pe, "No available DMA32 segments\n");
1706 tbl = pnv_pci_table_alloc(phb->hose->node);
1710 iommu_register_group(&pe->table_group, phb->hose->global_number,
1712 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1714 /* Grab a 32-bit TCE table */
1715 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
1716 weight, total_weight, base, segs);
1717 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1718 base * PNV_IODA1_DMA32_SEGSIZE,
1719 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
1721 /* XXX Currently, we allocate one big contiguous table for the
1722 * TCEs. We only really need one chunk per 256M of TCE space
1723 * (ie per segment) but that's an optimization for later, it
1724 * requires some added smarts with our get/put_tce implementation
1726 * Each TCE page is 4KB in size and each TCE entry occupies 8
1729 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
1730 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1731 get_order(tce32_segsz * segs));
1733 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1736 addr = page_address(tce_mem);
1737 memset(addr, 0, tce32_segsz * segs);
1740 for (i = 0; i < segs; i++) {
1741 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1744 __pa(addr) + tce32_segsz * i,
1745 tce32_segsz, IOMMU_PAGE_SIZE_4K);
1747 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
1753 /* Setup DMA32 segment mapping */
1754 for (i = base; i < base + segs; i++)
1755 phb->ioda.dma32_segmap[i] = pe->pe_number;
1757 /* Setup linux iommu table */
1758 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
1759 base * PNV_IODA1_DMA32_SEGSIZE,
1760 IOMMU_PAGE_SHIFT_4K);
1762 tbl->it_ops = &pnv_ioda1_iommu_ops;
1763 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1764 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
1765 iommu_init_table(tbl, phb->hose->node, 0, 0);
1767 pe->dma_setup_done = true;
1770 /* XXX Failure: Try to fallback to 64-bit only ? */
1772 __free_pages(tce_mem, get_order(tce32_segsz * segs));
1774 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1775 iommu_tce_table_put(tbl);
1779 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1780 int num, struct iommu_table *tbl)
1782 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1784 struct pnv_phb *phb = pe->phb;
1786 const unsigned long size = tbl->it_indirect_levels ?
1787 tbl->it_level_size : tbl->it_size;
1788 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1789 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1791 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
1792 num, start_addr, start_addr + win_size - 1,
1793 IOMMU_PAGE_SIZE(tbl));
1796 * Map TCE table through TVT. The TVE index is the PE number
1797 * shifted by 1 bit for 32-bits DMA space.
1799 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1801 (pe->pe_number << 1) + num,
1802 tbl->it_indirect_levels + 1,
1805 IOMMU_PAGE_SIZE(tbl));
1807 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
1811 pnv_pci_link_table_and_group(phb->hose->node, num,
1812 tbl, &pe->table_group);
1813 pnv_pci_ioda2_tce_invalidate_pe(pe);
1818 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1820 uint16_t window_id = (pe->pe_number << 1 ) + 1;
1823 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1825 phys_addr_t top = memblock_end_of_DRAM();
1827 top = roundup_pow_of_two(top);
1828 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1831 pe->tce_bypass_base,
1834 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1837 pe->tce_bypass_base,
1841 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1843 pe->tce_bypass_enabled = enable;
1846 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
1847 int num, __u32 page_shift, __u64 window_size, __u32 levels,
1848 bool alloc_userspace_copy, struct iommu_table **ptbl)
1850 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1852 int nid = pe->phb->hose->node;
1853 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
1855 struct iommu_table *tbl;
1857 tbl = pnv_pci_table_alloc(nid);
1861 tbl->it_ops = &pnv_ioda2_iommu_ops;
1863 ret = pnv_pci_ioda2_table_alloc_pages(nid,
1864 bus_offset, page_shift, window_size,
1865 levels, alloc_userspace_copy, tbl);
1867 iommu_tce_table_put(tbl);
1876 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
1878 struct iommu_table *tbl = NULL;
1880 unsigned long res_start, res_end;
1883 * crashkernel= specifies the kdump kernel's maximum memory at
1884 * some offset and there is no guaranteed the result is a power
1885 * of 2, which will cause errors later.
1887 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
1890 * In memory constrained environments, e.g. kdump kernel, the
1891 * DMA window can be larger than available memory, which will
1892 * cause errors later.
1894 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
1897 * We create the default window as big as we can. The constraint is
1898 * the max order of allocation possible. The TCE table is likely to
1899 * end up being multilevel and with on-demand allocation in place,
1900 * the initial use is not going to be huge as the default window aims
1901 * to support crippled devices (i.e. not fully 64bit DMAble) only.
1903 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
1904 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
1905 /* Each TCE level cannot exceed maxblock so go multilevel if needed */
1906 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
1907 unsigned long tcelevel_order = ilog2(maxblock >> 3);
1908 unsigned int levels = tces_order / tcelevel_order;
1910 if (tces_order % tcelevel_order)
1913 * We try to stick to default levels (which is >1 at the moment) in
1914 * order to save memory by relying on on-demain TCE level allocation.
1916 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
1918 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
1919 window_size, levels, false, &tbl);
1921 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
1926 /* We use top part of 32bit space for MMIO so exclude it from DMA */
1929 if (window_size > pe->phb->ioda.m32_pci_base) {
1930 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
1931 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
1933 iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
1935 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
1937 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
1939 iommu_tce_table_put(tbl);
1943 if (!pnv_iommu_bypass_disabled)
1944 pnv_pci_ioda2_set_bypass(pe, true);
1947 * Set table base for the case of IOMMU DMA use. Usually this is done
1948 * from dma_dev_setup() which is not called when a device is returned
1949 * from VFIO so do it here.
1952 set_iommu_table_base(&pe->pdev->dev, tbl);
1957 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1960 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1962 struct pnv_phb *phb = pe->phb;
1965 pe_info(pe, "Removing DMA window #%d\n", num);
1967 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1968 (pe->pe_number << 1) + num,
1969 0/* levels */, 0/* table address */,
1970 0/* table size */, 0/* page size */);
1972 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
1974 pnv_pci_ioda2_tce_invalidate_pe(pe);
1976 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
1981 #ifdef CONFIG_IOMMU_API
1982 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
1983 __u64 window_size, __u32 levels)
1985 unsigned long bytes = 0;
1986 const unsigned window_shift = ilog2(window_size);
1987 unsigned entries_shift = window_shift - page_shift;
1988 unsigned table_shift = entries_shift + 3;
1989 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
1990 unsigned long direct_table_size;
1992 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
1993 !is_power_of_2(window_size))
1996 /* Calculate a direct table size from window_size and levels */
1997 entries_shift = (entries_shift + levels - 1) / levels;
1998 table_shift = entries_shift + 3;
1999 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2000 direct_table_size = 1UL << table_shift;
2002 for ( ; levels; --levels) {
2003 bytes += ALIGN(tce_table_size, direct_table_size);
2005 tce_table_size /= direct_table_size;
2006 tce_table_size <<= 3;
2007 tce_table_size = max_t(unsigned long,
2008 tce_table_size, direct_table_size);
2011 return bytes + bytes; /* one for HW table, one for userspace copy */
2014 static long pnv_pci_ioda2_create_table_userspace(
2015 struct iommu_table_group *table_group,
2016 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2017 struct iommu_table **ptbl)
2019 long ret = pnv_pci_ioda2_create_table(table_group,
2020 num, page_shift, window_size, levels, true, ptbl);
2023 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2024 page_shift, window_size, levels);
2028 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
2030 struct pci_dev *dev;
2032 list_for_each_entry(dev, &bus->devices, bus_list) {
2033 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
2034 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
2036 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2037 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
2041 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2043 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2045 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2046 struct iommu_table *tbl = pe->table_group.tables[0];
2048 pnv_pci_ioda2_set_bypass(pe, false);
2049 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2051 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2053 set_iommu_table_base(&pe->pdev->dev, NULL);
2054 iommu_tce_table_put(tbl);
2057 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2059 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2062 pnv_pci_ioda2_setup_default_config(pe);
2064 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2067 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2068 .get_table_size = pnv_pci_ioda2_get_table_size,
2069 .create_table = pnv_pci_ioda2_create_table_userspace,
2070 .set_window = pnv_pci_ioda2_set_window,
2071 .unset_window = pnv_pci_ioda2_unset_window,
2072 .take_ownership = pnv_ioda2_take_ownership,
2073 .release_ownership = pnv_ioda2_release_ownership,
2077 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2078 struct pnv_ioda_pe *pe)
2082 /* TVE #1 is selected by PCI address bit 59 */
2083 pe->tce_bypass_base = 1ull << 59;
2085 /* The PE will reserve all possible 32-bits space */
2086 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2087 phb->ioda.m32_pci_base);
2089 /* Setup linux iommu table */
2090 pe->table_group.tce32_start = 0;
2091 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2092 pe->table_group.max_dynamic_windows_supported =
2093 IOMMU_TABLE_GROUP_MAX_TABLES;
2094 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2095 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2097 rc = pnv_pci_ioda2_setup_default_config(pe);
2101 #ifdef CONFIG_IOMMU_API
2102 pe->table_group.ops = &pnv_pci_ioda2_ops;
2103 iommu_register_group(&pe->table_group, phb->hose->global_number,
2106 pe->dma_setup_done = true;
2109 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2111 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2114 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2117 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2120 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2121 struct irq_chip *chip = irq_data_get_irq_chip(d);
2123 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2130 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2132 struct irq_data *idata;
2133 struct irq_chip *ichip;
2135 /* The MSI EOI OPAL call is only needed on PHB3 */
2136 if (phb->model != PNV_PHB_MODEL_PHB3)
2139 if (!phb->ioda.irq_chip_init) {
2141 * First time we setup an MSI IRQ, we need to setup the
2142 * corresponding IRQ chip to route correctly.
2144 idata = irq_get_irq_data(virq);
2145 ichip = irq_data_get_irq_chip(idata);
2146 phb->ioda.irq_chip_init = 1;
2147 phb->ioda.irq_chip = *ichip;
2148 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2150 irq_set_chip(virq, &phb->ioda.irq_chip);
2154 * Returns true iff chip is something that we could call
2155 * pnv_opal_pci_msi_eoi for.
2157 bool is_pnv_opal_msi(struct irq_chip *chip)
2159 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2161 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2163 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2164 unsigned int hwirq, unsigned int virq,
2165 unsigned int is_64, struct msi_msg *msg)
2167 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2168 unsigned int xive_num = hwirq - phb->msi_base;
2172 /* No PE assigned ? bail out ... no MSI for you ! */
2176 /* Check if we have an MVE */
2177 if (pe->mve_number < 0)
2180 /* Force 32-bit MSI on some broken devices */
2181 if (dev->no_64bit_msi)
2184 /* Assign XIVE to PE */
2185 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2187 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2188 pci_name(dev), rc, xive_num);
2195 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2198 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2202 msg->address_hi = be64_to_cpu(addr64) >> 32;
2203 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2207 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2210 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2214 msg->address_hi = 0;
2215 msg->address_lo = be32_to_cpu(addr32);
2217 msg->data = be32_to_cpu(data);
2219 pnv_set_msi_irq_chip(phb, virq);
2221 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2222 " address=%x_%08x data=%x PE# %x\n",
2223 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2224 msg->address_hi, msg->address_lo, data, pe->pe_number);
2229 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2232 const __be32 *prop = of_get_property(phb->hose->dn,
2233 "ibm,opal-msi-ranges", NULL);
2236 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2241 phb->msi_base = be32_to_cpup(prop);
2242 count = be32_to_cpup(prop + 1);
2243 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2244 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2245 phb->hose->global_number);
2249 phb->msi_setup = pnv_pci_ioda_msi_setup;
2250 phb->msi32_support = 1;
2251 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2252 count, phb->msi_base);
2255 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2256 struct resource *res)
2258 struct pnv_phb *phb = pe->phb;
2259 struct pci_bus_region region;
2263 if (!res || !res->flags || res->start > res->end ||
2264 res->flags & IORESOURCE_UNSET)
2267 if (res->flags & IORESOURCE_IO) {
2268 region.start = res->start - phb->ioda.io_pci_base;
2269 region.end = res->end - phb->ioda.io_pci_base;
2270 index = region.start / phb->ioda.io_segsize;
2272 while (index < phb->ioda.total_pe_num &&
2273 region.start <= region.end) {
2274 phb->ioda.io_segmap[index] = pe->pe_number;
2275 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2276 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2277 if (rc != OPAL_SUCCESS) {
2278 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
2279 __func__, rc, index, pe->pe_number);
2283 region.start += phb->ioda.io_segsize;
2286 } else if ((res->flags & IORESOURCE_MEM) &&
2287 !pnv_pci_is_m64(phb, res)) {
2288 region.start = res->start -
2289 phb->hose->mem_offset[0] -
2290 phb->ioda.m32_pci_base;
2291 region.end = res->end -
2292 phb->hose->mem_offset[0] -
2293 phb->ioda.m32_pci_base;
2294 index = region.start / phb->ioda.m32_segsize;
2296 while (index < phb->ioda.total_pe_num &&
2297 region.start <= region.end) {
2298 phb->ioda.m32_segmap[index] = pe->pe_number;
2299 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2300 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2301 if (rc != OPAL_SUCCESS) {
2302 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
2303 __func__, rc, index, pe->pe_number);
2307 region.start += phb->ioda.m32_segsize;
2314 * This function is supposed to be called on basis of PE from top
2315 * to bottom style. So the the I/O or MMIO segment assigned to
2316 * parent PE could be overridden by its child PEs if necessary.
2318 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
2320 struct pci_dev *pdev;
2324 * NOTE: We only care PCI bus based PE for now. For PCI
2325 * device based PE, for example SRIOV sensitive VF should
2326 * be figured out later.
2328 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2330 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
2331 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2332 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
2335 * If the PE contains all subordinate PCI buses, the
2336 * windows of the child bridges should be mapped to
2339 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
2341 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
2342 pnv_ioda_setup_pe_res(pe,
2343 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
2347 #ifdef CONFIG_DEBUG_FS
2348 static int pnv_pci_diag_data_set(void *data, u64 val)
2350 struct pnv_phb *phb = data;
2353 /* Retrieve the diag data from firmware */
2354 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
2355 phb->diag_data_size);
2356 if (ret != OPAL_SUCCESS)
2359 /* Print the diag data to the kernel log */
2360 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
2364 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set,
2367 static int pnv_pci_ioda_pe_dump(void *data, u64 val)
2369 struct pnv_phb *phb = data;
2372 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
2373 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
2375 if (!test_bit(pe_num, phb->ioda.pe_alloc))
2378 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
2379 pe->rid, pe->device_count,
2380 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
2381 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
2382 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
2383 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
2384 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
2385 (pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
2391 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL,
2392 pnv_pci_ioda_pe_dump, "%llu\n");
2394 #endif /* CONFIG_DEBUG_FS */
2396 static void pnv_pci_ioda_create_dbgfs(void)
2398 #ifdef CONFIG_DEBUG_FS
2399 struct pci_controller *hose, *tmp;
2400 struct pnv_phb *phb;
2403 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2404 phb = hose->private_data;
2406 /* Notify initialization of PHB done */
2407 phb->initialized = 1;
2409 sprintf(name, "PCI%04x", hose->global_number);
2410 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2412 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs,
2413 phb, &pnv_pci_diag_data_fops);
2414 debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs,
2415 phb, &pnv_pci_ioda_pe_dump_fops);
2417 #endif /* CONFIG_DEBUG_FS */
2420 static void pnv_pci_enable_bridge(struct pci_bus *bus)
2422 struct pci_dev *dev = bus->self;
2423 struct pci_bus *child;
2425 /* Empty bus ? bail */
2426 if (list_empty(&bus->devices))
2430 * If there's a bridge associated with that bus enable it. This works
2431 * around races in the generic code if the enabling is done during
2432 * parallel probing. This can be removed once those races have been
2436 int rc = pci_enable_device(dev);
2438 pci_err(dev, "Error enabling bridge (%d)\n", rc);
2439 pci_set_master(dev);
2442 /* Perform the same to child busses */
2443 list_for_each_entry(child, &bus->children, node)
2444 pnv_pci_enable_bridge(child);
2447 static void pnv_pci_enable_bridges(void)
2449 struct pci_controller *hose;
2451 list_for_each_entry(hose, &hose_list, list_node)
2452 pnv_pci_enable_bridge(hose->bus);
2455 static void pnv_pci_ioda_fixup(void)
2457 pnv_pci_ioda_setup_nvlink();
2458 pnv_pci_ioda_create_dbgfs();
2460 pnv_pci_enable_bridges();
2463 pnv_eeh_post_init();
2468 * Returns the alignment for I/O or memory windows for P2P
2469 * bridges. That actually depends on how PEs are segmented.
2470 * For now, we return I/O or M32 segment size for PE sensitive
2471 * P2P bridges. Otherwise, the default values (4KiB for I/O,
2472 * 1MiB for memory) will be returned.
2474 * The current PCI bus might be put into one PE, which was
2475 * create against the parent PCI bridge. For that case, we
2476 * needn't enlarge the alignment so that we can save some
2479 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2482 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2483 int num_pci_bridges = 0;
2484 struct pci_dev *bridge;
2488 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2490 if (num_pci_bridges >= 2)
2494 bridge = bridge->bus->self;
2498 * We fall back to M32 if M64 isn't supported. We enforce the M64
2499 * alignment for any 64-bit resource, PCIe doesn't care and
2500 * bridges only do 64-bit prefetchable anyway.
2502 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
2503 return phb->ioda.m64_segsize;
2504 if (type & IORESOURCE_MEM)
2505 return phb->ioda.m32_segsize;
2507 return phb->ioda.io_segsize;
2511 * We are updating root port or the upstream port of the
2512 * bridge behind the root port with PHB's windows in order
2513 * to accommodate the changes on required resources during
2514 * PCI (slot) hotplug, which is connected to either root
2515 * port or the downstream ports of PCIe switch behind the
2518 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
2521 struct pci_controller *hose = pci_bus_to_host(bus);
2522 struct pnv_phb *phb = hose->private_data;
2523 struct pci_dev *bridge = bus->self;
2524 struct resource *r, *w;
2525 bool msi_region = false;
2528 /* Check if we need apply fixup to the bridge's windows */
2529 if (!pci_is_root_bus(bridge->bus) &&
2530 !pci_is_root_bus(bridge->bus->self->bus))
2533 /* Fixup the resources */
2534 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
2535 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
2536 if (!r->flags || !r->parent)
2540 if (r->flags & type & IORESOURCE_IO)
2541 w = &hose->io_resource;
2542 else if (pnv_pci_is_m64(phb, r) &&
2543 (type & IORESOURCE_PREFETCH) &&
2544 phb->ioda.m64_segsize)
2545 w = &hose->mem_resources[1];
2546 else if (r->flags & type & IORESOURCE_MEM) {
2547 w = &hose->mem_resources[0];
2551 r->start = w->start;
2554 /* The 64KB 32-bits MSI region shouldn't be included in
2555 * the 32-bits bridge window. Otherwise, we can see strange
2556 * issues. One of them is EEH error observed on Garrison.
2558 * Exclude top 1MB region which is the minimal alignment of
2559 * 32-bits bridge window.
2568 static void pnv_pci_configure_bus(struct pci_bus *bus)
2570 struct pci_dev *bridge = bus->self;
2571 struct pnv_ioda_pe *pe;
2572 bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
2574 dev_info(&bus->dev, "Configuring PE for bus\n");
2576 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
2577 if (WARN_ON(list_empty(&bus->devices)))
2580 /* Reserve PEs according to used M64 resources */
2581 pnv_ioda_reserve_m64_pe(bus, NULL, all);
2584 * Assign PE. We might run here because of partial hotplug.
2585 * For the case, we just pick up the existing PE and should
2586 * not allocate resources again.
2588 pe = pnv_ioda_setup_bus_PE(bus, all);
2592 pnv_ioda_setup_pe_seg(pe);
2595 static resource_size_t pnv_pci_default_alignment(void)
2600 /* Prevent enabling devices for which we couldn't properly
2603 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2605 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
2608 /* The function is probably called while the PEs have
2609 * not be created yet. For example, resource reassignment
2610 * during PCI probe period. We just skip the check if
2613 if (!phb->initialized)
2616 pdn = pci_get_pdn(dev);
2617 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2623 static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
2625 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2626 struct pnv_phb *phb = hose->private_data;
2628 struct pnv_ioda_pe *pe;
2630 if (!phb->initialized)
2633 pdn = pci_get_pdn(dev);
2637 if (pdn->pe_number == IODA_INVALID_PE) {
2638 pe = pnv_ioda_setup_dev_PE(dev);
2645 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
2648 struct pnv_ioda_pe *pe = container_of(table_group,
2649 struct pnv_ioda_pe, table_group);
2650 struct pnv_phb *phb = pe->phb;
2654 pe_info(pe, "Removing DMA window #%d\n", num);
2655 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
2656 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
2659 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2660 idx, 0, 0ul, 0ul, 0ul);
2661 if (rc != OPAL_SUCCESS) {
2662 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
2667 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
2670 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2671 return OPAL_SUCCESS;
2674 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
2676 struct iommu_table *tbl = pe->table_group.tables[0];
2679 if (!pe->dma_setup_done)
2682 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
2683 if (rc != OPAL_SUCCESS)
2686 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
2687 if (pe->table_group.group) {
2688 iommu_group_put(pe->table_group.group);
2689 WARN_ON(pe->table_group.group);
2692 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
2693 iommu_tce_table_put(tbl);
2696 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
2698 struct iommu_table *tbl = pe->table_group.tables[0];
2701 if (!pe->dma_setup_done)
2704 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2706 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
2708 pnv_pci_ioda2_set_bypass(pe, false);
2709 if (pe->table_group.group) {
2710 iommu_group_put(pe->table_group.group);
2711 WARN_ON(pe->table_group.group);
2714 iommu_tce_table_put(tbl);
2717 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
2721 struct pnv_phb *phb = pe->phb;
2725 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
2726 if (map[idx] != pe->pe_number)
2729 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2730 phb->ioda.reserved_pe_idx, win, 0, idx);
2732 if (rc != OPAL_SUCCESS)
2733 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
2736 map[idx] = IODA_INVALID_PE;
2740 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
2742 struct pnv_phb *phb = pe->phb;
2744 if (phb->type == PNV_PHB_IODA1) {
2745 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
2746 phb->ioda.io_segmap);
2747 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2748 phb->ioda.m32_segmap);
2749 /* M64 is pre-configured by pnv_ioda1_init_m64() */
2750 } else if (phb->type == PNV_PHB_IODA2) {
2751 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2752 phb->ioda.m32_segmap);
2756 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
2758 struct pnv_phb *phb = pe->phb;
2759 struct pnv_ioda_pe *slave, *tmp;
2761 pe_info(pe, "Releasing PE\n");
2763 mutex_lock(&phb->ioda.pe_list_mutex);
2764 list_del(&pe->list);
2765 mutex_unlock(&phb->ioda.pe_list_mutex);
2767 switch (phb->type) {
2769 pnv_pci_ioda1_release_pe_dma(pe);
2772 pnv_pci_ioda2_release_pe_dma(pe);
2774 case PNV_PHB_NPU_OCAPI:
2780 pnv_ioda_release_pe_seg(pe);
2781 pnv_ioda_deconfigure_pe(pe->phb, pe);
2783 /* Release slave PEs in the compound PE */
2784 if (pe->flags & PNV_IODA_PE_MASTER) {
2785 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
2786 list_del(&slave->list);
2787 pnv_ioda_free_pe(slave);
2792 * The PE for root bus can be removed because of hotplug in EEH
2793 * recovery for fenced PHB error. We need to mark the PE dead so
2794 * that it can be populated again in PCI hot add path. The PE
2795 * shouldn't be destroyed as it's the global reserved resource.
2797 if (phb->ioda.root_pe_idx == pe->pe_number)
2800 pnv_ioda_free_pe(pe);
2803 static void pnv_pci_release_device(struct pci_dev *pdev)
2805 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
2806 struct pci_dn *pdn = pci_get_pdn(pdev);
2807 struct pnv_ioda_pe *pe;
2809 /* The VF PE state is torn down when sriov_disable() is called */
2810 if (pdev->is_virtfn)
2813 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2816 #ifdef CONFIG_PCI_IOV
2818 * FIXME: Try move this to sriov_disable(). It's here since we allocate
2819 * the iov state at probe time since we need to fiddle with the IOV
2822 if (pdev->is_physfn)
2823 kfree(pdev->dev.archdata.iov_data);
2827 * PCI hotplug can happen as part of EEH error recovery. The @pdn
2828 * isn't removed and added afterwards in this scenario. We should
2829 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
2830 * device count is decreased on removing devices while failing to
2831 * be increased on adding devices. It leads to unbalanced PE's device
2832 * count and eventually make normal PCI hotplug path broken.
2834 pe = &phb->ioda.pe_array[pdn->pe_number];
2835 pdn->pe_number = IODA_INVALID_PE;
2837 WARN_ON(--pe->device_count < 0);
2838 if (pe->device_count == 0)
2839 pnv_ioda_release_pe(pe);
2842 static void pnv_npu_disable_device(struct pci_dev *pdev)
2844 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
2845 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
2847 if (eehpe && eeh_ops && eeh_ops->reset)
2848 eeh_ops->reset(eehpe, EEH_RESET_HOT);
2851 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
2853 struct pnv_phb *phb = hose->private_data;
2855 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
2859 static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus)
2861 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2862 struct pnv_ioda_pe *pe;
2864 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2865 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
2871 if (bus->number == ((pe->rid >> 8) & 0xFF)) {
2878 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
2879 .dma_dev_setup = pnv_pci_ioda_dma_dev_setup,
2880 .dma_bus_setup = pnv_pci_ioda_dma_bus_setup,
2881 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
2882 .setup_msi_irqs = pnv_setup_msi_irqs,
2883 .teardown_msi_irqs = pnv_teardown_msi_irqs,
2884 .enable_device_hook = pnv_pci_enable_device_hook,
2885 .release_device = pnv_pci_release_device,
2886 .window_alignment = pnv_pci_window_alignment,
2887 .setup_bridge = pnv_pci_fixup_bridge_resources,
2888 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
2889 .shutdown = pnv_pci_ioda_shutdown,
2892 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
2893 .setup_msi_irqs = pnv_setup_msi_irqs,
2894 .teardown_msi_irqs = pnv_teardown_msi_irqs,
2895 .enable_device_hook = pnv_pci_enable_device_hook,
2896 .window_alignment = pnv_pci_window_alignment,
2897 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
2898 .shutdown = pnv_pci_ioda_shutdown,
2899 .disable_device = pnv_npu_disable_device,
2902 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
2903 .enable_device_hook = pnv_ocapi_enable_device_hook,
2904 .release_device = pnv_pci_release_device,
2905 .window_alignment = pnv_pci_window_alignment,
2906 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
2907 .shutdown = pnv_pci_ioda_shutdown,
2910 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2911 u64 hub_id, int ioda_type)
2913 struct pci_controller *hose;
2914 struct pnv_phb *phb;
2915 unsigned long size, m64map_off, m32map_off, pemap_off;
2916 unsigned long iomap_off = 0, dma32map_off = 0;
2917 struct pnv_ioda_pe *root_pe;
2919 const __be64 *prop64;
2920 const __be32 *prop32;
2927 if (!of_device_is_available(np))
2930 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
2932 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
2934 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
2937 phb_id = be64_to_cpup(prop64);
2938 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
2940 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
2942 panic("%s: Failed to allocate %zu bytes\n", __func__,
2945 /* Allocate PCI controller */
2946 phb->hose = hose = pcibios_alloc_controller(np);
2948 pr_err(" Can't allocate PCI controller for %pOF\n",
2950 memblock_free(__pa(phb), sizeof(struct pnv_phb));
2954 spin_lock_init(&phb->lock);
2955 prop32 = of_get_property(np, "bus-range", &len);
2956 if (prop32 && len == 8) {
2957 hose->first_busno = be32_to_cpu(prop32[0]);
2958 hose->last_busno = be32_to_cpu(prop32[1]);
2960 pr_warn(" Broken <bus-range> on %pOF\n", np);
2961 hose->first_busno = 0;
2962 hose->last_busno = 0xff;
2964 hose->private_data = phb;
2965 phb->hub_id = hub_id;
2966 phb->opal_id = phb_id;
2967 phb->type = ioda_type;
2968 mutex_init(&phb->ioda.pe_alloc_mutex);
2970 /* Detect specific models for error handling */
2971 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
2972 phb->model = PNV_PHB_MODEL_P7IOC;
2973 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
2974 phb->model = PNV_PHB_MODEL_PHB3;
2975 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
2976 phb->model = PNV_PHB_MODEL_NPU;
2977 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
2978 phb->model = PNV_PHB_MODEL_NPU2;
2980 phb->model = PNV_PHB_MODEL_UNKNOWN;
2982 /* Initialize diagnostic data buffer */
2983 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
2985 phb->diag_data_size = be32_to_cpup(prop32);
2987 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
2989 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
2990 if (!phb->diag_data)
2991 panic("%s: Failed to allocate %u bytes\n", __func__,
2992 phb->diag_data_size);
2994 /* Parse 32-bit and IO ranges (if any) */
2995 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
2998 if (!of_address_to_resource(np, 0, &r)) {
2999 phb->regs_phys = r.start;
3000 phb->regs = ioremap(r.start, resource_size(&r));
3001 if (phb->regs == NULL)
3002 pr_err(" Failed to map registers !\n");
3005 /* Initialize more IODA stuff */
3006 phb->ioda.total_pe_num = 1;
3007 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3009 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3010 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3012 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3014 /* Invalidate RID to PE# mapping */
3015 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3016 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3018 /* Parse 64-bit MMIO range */
3019 pnv_ioda_parse_m64_window(phb);
3021 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3022 /* FW Has already off top 64k of M32 space (MSI space) */
3023 phb->ioda.m32_size += 0x10000;
3025 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3026 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3027 phb->ioda.io_size = hose->pci_io_size;
3028 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3029 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3031 /* Calculate how many 32-bit TCE segments we have */
3032 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3033 PNV_IODA1_DMA32_SEGSIZE;
3035 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3036 size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3037 sizeof(unsigned long));
3039 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3041 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3042 if (phb->type == PNV_PHB_IODA1) {
3044 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3045 dma32map_off = size;
3046 size += phb->ioda.dma32_count *
3047 sizeof(phb->ioda.dma32_segmap[0]);
3050 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3051 aux = memblock_alloc(size, SMP_CACHE_BYTES);
3053 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3054 phb->ioda.pe_alloc = aux;
3055 phb->ioda.m64_segmap = aux + m64map_off;
3056 phb->ioda.m32_segmap = aux + m32map_off;
3057 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3058 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3059 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3061 if (phb->type == PNV_PHB_IODA1) {
3062 phb->ioda.io_segmap = aux + iomap_off;
3063 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3064 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3066 phb->ioda.dma32_segmap = aux + dma32map_off;
3067 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3068 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3070 phb->ioda.pe_array = aux + pemap_off;
3073 * Choose PE number for root bus, which shouldn't have
3074 * M64 resources consumed by its child devices. To pick
3075 * the PE number adjacent to the reserved one if possible.
3077 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3078 if (phb->ioda.reserved_pe_idx == 0) {
3079 phb->ioda.root_pe_idx = 1;
3080 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3081 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3082 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3083 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3085 /* otherwise just allocate one */
3086 root_pe = pnv_ioda_alloc_pe(phb, 1);
3087 phb->ioda.root_pe_idx = root_pe->pe_number;
3090 INIT_LIST_HEAD(&phb->ioda.pe_list);
3091 mutex_init(&phb->ioda.pe_list_mutex);
3093 /* Calculate how many 32-bit TCE segments we have */
3094 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3095 PNV_IODA1_DMA32_SEGSIZE;
3097 #if 0 /* We should really do that ... */
3098 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3101 starting_real_address,
3102 starting_pci_address,
3106 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3107 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3108 phb->ioda.m32_size, phb->ioda.m32_segsize);
3109 if (phb->ioda.m64_size)
3110 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3111 phb->ioda.m64_size, phb->ioda.m64_segsize);
3112 if (phb->ioda.io_size)
3113 pr_info(" IO: 0x%x [segment=0x%x]\n",
3114 phb->ioda.io_size, phb->ioda.io_segsize);
3117 phb->hose->ops = &pnv_pci_ops;
3118 phb->get_pe_state = pnv_ioda_get_pe_state;
3119 phb->freeze_pe = pnv_ioda_freeze_pe;
3120 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3122 /* Setup MSI support */
3123 pnv_pci_init_ioda_msis(phb);
3126 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3127 * to let the PCI core do resource assignment. It's supposed
3128 * that the PCI core will do correct I/O and MMIO alignment
3129 * for the P2P bridge bars so that each PCI bus (excluding
3130 * the child P2P bridges) can form individual PE.
3132 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3134 switch (phb->type) {
3135 case PNV_PHB_NPU_NVLINK:
3136 hose->controller_ops = pnv_npu_ioda_controller_ops;
3138 case PNV_PHB_NPU_OCAPI:
3139 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3142 hose->controller_ops = pnv_pci_ioda_controller_ops;
3145 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3147 #ifdef CONFIG_PCI_IOV
3148 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
3149 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3150 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3151 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3154 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3156 /* Reset IODA tables to a clean state */
3157 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3159 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3162 * If we're running in kdump kernel, the previous kernel never
3163 * shutdown PCI devices correctly. We already got IODA table
3164 * cleaned out. So we have to issue PHB reset to stop all PCI
3165 * transactions from previous kernel. The ppc_pci_reset_phbs
3166 * kernel parameter will force this reset too. Additionally,
3167 * if the IODA reset above failed then use a bigger hammer.
3168 * This can happen if we get a PHB fatal error in very early
3171 if (is_kdump_kernel() || pci_reset_phbs || rc) {
3172 pr_info(" Issue PHB reset ...\n");
3173 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3174 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3177 /* Remove M64 resource if we can't configure it successfully */
3178 if (!phb->init_m64 || phb->init_m64(phb))
3179 hose->mem_resources[1].flags = 0;
3182 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3184 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3187 void __init pnv_pci_init_npu_phb(struct device_node *np)
3189 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3192 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3194 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3197 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3199 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
3201 if (!machine_is(powernv))
3204 if (phb->type == PNV_PHB_NPU_OCAPI)
3205 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3207 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3209 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3211 struct device_node *phbn;
3212 const __be64 *prop64;
3215 pr_info("Probing IODA IO-Hub %pOF\n", np);
3217 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3219 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3222 hub_id = be64_to_cpup(prop64);
3223 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3225 /* Count child PHBs */
3226 for_each_child_of_node(np, phbn) {
3227 /* Look for IODA1 PHBs */
3228 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3229 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);