arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24 #include <linux/memblock.h>
  25 #include <linux/iommu.h>
  26 #include <linux/rculist.h>
  27 #include <linux/sizes.h>
  28
  29 #include <asm/sections.h>
  30 #include <asm/io.h>
  31 #include <asm/prom.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/machdep.h>
  34 #include <asm/msi_bitmap.h>
  35 #include <asm/ppc-pci.h>
  36 #include <asm/opal.h>
  37 #include <asm/iommu.h>
  38 #include <asm/tce.h>
  39 #include <asm/xics.h>
  40 #include <asm/debugfs.h>
  41 #include <asm/firmware.h>
  42 #include <asm/pnv-pci.h>
  43 #include <asm/mmzone.h>
  44
  45 #include <misc/cxl-base.h>
  46
  47 #include "powernv.h"
  48 #include "pci.h"
  49
  50 #define PNV_IODA1_M64_NUM       16      /* Number of M64 BARs   */
  51 #define PNV_IODA1_M64_SEGS      8       /* Segments per M64 BAR */
  52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
  53
  54 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  55 #define POWERNV_IOMMU_MAX_LEVELS        5
  56
  57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
  58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  59
  60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  61                             const char *fmt, ...)
  62 {
  63         struct va_format vaf;
  64         va_list args;
  65         char pfix[32];
  66
  67         va_start(args, fmt);
  68
  69         vaf.fmt = fmt;
  70         vaf.va = &args;
  71
  72         if (pe->flags & PNV_IODA_PE_DEV)
  73                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  74         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  75                 sprintf(pfix, "%04x:%02x     ",
  76                         pci_domain_nr(pe->pbus), pe->pbus->number);
  77 #ifdef CONFIG_PCI_IOV
  78         else if (pe->flags & PNV_IODA_PE_VF)
  79                 sprintf(pfix, "%04x:%02x:%2x.%d",
  80                         pci_domain_nr(pe->parent_dev->bus),
  81                         (pe->rid & 0xff00) >> 8,
  82                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  83 #endif /* CONFIG_PCI_IOV*/
  84
  85         printk("%spci %s: [PE# %.2x] %pV",
  86                level, pfix, pe->pe_number, &vaf);
  87
  88         va_end(args);
  89 }
  90
  91 static bool pnv_iommu_bypass_disabled __read_mostly;
  92
  93 static int __init iommu_setup(char *str)
  94 {
  95         if (!str)
  96                 return -EINVAL;
  97
  98         while (*str) {
  99                 if (!strncmp(str, "nobypass", 8)) {
 100                         pnv_iommu_bypass_disabled = true;
 101                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 102                         break;
 103                 }
 104                 str += strcspn(str, ",");
 105                 if (*str == ',')
 106                         str++;
 107         }
 108
 109         return 0;
 110 }
 111 early_param("iommu", iommu_setup);
 112
 113 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
 114 {
 115         /*
 116          * WARNING: We cannot rely on the resource flags. The Linux PCI
 117          * allocation code sometimes decides to put a 64-bit prefetchable
 118          * BAR in the 32-bit window, so we have to compare the addresses.
 119          *
 120          * For simplicity we only test resource start.
 121          */
 122         return (r->start >= phb->ioda.m64_base &&
 123                 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
 124 }
 125
 126 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
 127 {
 128         unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 129
 130         return (resource_flags & flags) == flags;
 131 }
 132
 133 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
 134 {
 135         s64 rc;
 136
 137         phb->ioda.pe_array[pe_no].phb = phb;
 138         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 139
 140         /*
 141          * Clear the PE frozen state as it might be put into frozen state
 142          * in the last PCI remove path. It's not harmful to do so when the
 143          * PE is already in unfrozen state.
 144          */
 145         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 146                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 147         if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
 148                 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
 149                         __func__, rc, phb->hose->global_number, pe_no);
 150
 151         return &phb->ioda.pe_array[pe_no];
 152 }
 153
 154 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 155 {
 156         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
 157                 pr_warn("%s: Invalid PE %x on PHB#%x\n",
 158                         __func__, pe_no, phb->hose->global_number);
 159                 return;
 160         }
 161
 162         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
 163                 pr_debug("%s: PE %x was reserved on PHB#%x\n",
 164                          __func__, pe_no, phb->hose->global_number);
 165
 166         pnv_ioda_init_pe(phb, pe_no);
 167 }
 168
 169 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
 170 {
 171         long pe;
 172
 173         for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
 174                 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
 175                         return pnv_ioda_init_pe(phb, pe);
 176         }
 177
 178         return NULL;
 179 }
 180
 181 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
 182 {
 183         struct pnv_phb *phb = pe->phb;
 184         unsigned int pe_num = pe->pe_number;
 185
 186         WARN_ON(pe->pdev);
 187
 188         memset(pe, 0, sizeof(struct pnv_ioda_pe));
 189         clear_bit(pe_num, phb->ioda.pe_alloc);
 190 }
 191
 192 /* The default M64 BAR is shared by all PEs */
 193 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 194 {
 195         const char *desc;
 196         struct resource *r;
 197         s64 rc;
 198
 199         /* Configure the default M64 BAR */
 200         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 201                                          OPAL_M64_WINDOW_TYPE,
 202                                          phb->ioda.m64_bar_idx,
 203                                          phb->ioda.m64_base,
 204                                          0, /* unused */
 205                                          phb->ioda.m64_size);
 206         if (rc != OPAL_SUCCESS) {
 207                 desc = "configuring";
 208                 goto fail;
 209         }
 210
 211         /* Enable the default M64 BAR */
 212         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 213                                       OPAL_M64_WINDOW_TYPE,
 214                                       phb->ioda.m64_bar_idx,
 215                                       OPAL_ENABLE_M64_SPLIT);
 216         if (rc != OPAL_SUCCESS) {
 217                 desc = "enabling";
 218                 goto fail;
 219         }
 220
 221         /*
 222          * Exclude the segments for reserved and root bus PE, which
 223          * are first or last two PEs.
 224          */
 225         r = &phb->hose->mem_resources[1];
 226         if (phb->ioda.reserved_pe_idx == 0)
 227                 r->start += (2 * phb->ioda.m64_segsize);
 228         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 229                 r->end -= (2 * phb->ioda.m64_segsize);
 230         else
 231                 pr_warn("  Cannot strip M64 segment for reserved PE#%x\n",
 232                         phb->ioda.reserved_pe_idx);
 233
 234         return 0;
 235
 236 fail:
 237         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 238                 rc, desc, phb->ioda.m64_bar_idx);
 239         opal_pci_phb_mmio_enable(phb->opal_id,
 240                                  OPAL_M64_WINDOW_TYPE,
 241                                  phb->ioda.m64_bar_idx,
 242                                  OPAL_DISABLE_M64);
 243         return -EIO;
 244 }
 245
 246 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
 247                                          unsigned long *pe_bitmap)
 248 {
 249         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 250         struct pnv_phb *phb = hose->private_data;
 251         struct resource *r;
 252         resource_size_t base, sgsz, start, end;
 253         int segno, i;
 254
 255         base = phb->ioda.m64_base;
 256         sgsz = phb->ioda.m64_segsize;
 257         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 258                 r = &pdev->resource[i];
 259                 if (!r->parent || !pnv_pci_is_m64(phb, r))
 260                         continue;
 261
 262                 start = _ALIGN_DOWN(r->start - base, sgsz);
 263                 end = _ALIGN_UP(r->end - base, sgsz);
 264                 for (segno = start / sgsz; segno < end / sgsz; segno++) {
 265                         if (pe_bitmap)
 266                                 set_bit(segno, pe_bitmap);
 267                         else
 268                                 pnv_ioda_reserve_pe(phb, segno);
 269                 }
 270         }
 271 }
 272
 273 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
 274 {
 275         struct resource *r;
 276         int index;
 277
 278         /*
 279          * There are 16 M64 BARs, each of which has 8 segments. So
 280          * there are as many M64 segments as the maximum number of
 281          * PEs, which is 128.
 282          */
 283         for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
 284                 unsigned long base, segsz = phb->ioda.m64_segsize;
 285                 int64_t rc;
 286
 287                 base = phb->ioda.m64_base +
 288                        index * PNV_IODA1_M64_SEGS * segsz;
 289                 rc = opal_pci_set_phb_mem_window(phb->opal_id,
 290                                 OPAL_M64_WINDOW_TYPE, index, base, 0,
 291                                 PNV_IODA1_M64_SEGS * segsz);
 292                 if (rc != OPAL_SUCCESS) {
 293                         pr_warn("  Error %lld setting M64 PHB#%x-BAR#%d\n",
 294                                 rc, phb->hose->global_number, index);
 295                         goto fail;
 296                 }
 297
 298                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
 299                                 OPAL_M64_WINDOW_TYPE, index,
 300                                 OPAL_ENABLE_M64_SPLIT);
 301                 if (rc != OPAL_SUCCESS) {
 302                         pr_warn("  Error %lld enabling M64 PHB#%x-BAR#%d\n",
 303                                 rc, phb->hose->global_number, index);
 304                         goto fail;
 305                 }
 306         }
 307
 308         /*
 309          * Exclude the segments for reserved and root bus PE, which
 310          * are first or last two PEs.
 311          */
 312         r = &phb->hose->mem_resources[1];
 313         if (phb->ioda.reserved_pe_idx == 0)
 314                 r->start += (2 * phb->ioda.m64_segsize);
 315         else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
 316                 r->end -= (2 * phb->ioda.m64_segsize);
 317         else
 318                 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
 319                      phb->ioda.reserved_pe_idx, phb->hose->global_number);
 320
 321         return 0;
 322
 323 fail:
 324         for ( ; index >= 0; index--)
 325                 opal_pci_phb_mmio_enable(phb->opal_id,
 326                         OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
 327
 328         return -EIO;
 329 }
 330
 331 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
 332                                     unsigned long *pe_bitmap,
 333                                     bool all)
 334 {
 335         struct pci_dev *pdev;
 336
 337         list_for_each_entry(pdev, &bus->devices, bus_list) {
 338                 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
 339
 340                 if (all && pdev->subordinate)
 341                         pnv_ioda_reserve_m64_pe(pdev->subordinate,
 342                                                 pe_bitmap, all);
 343         }
 344 }
 345
 346 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
 347 {
 348         struct pci_controller *hose = pci_bus_to_host(bus);
 349         struct pnv_phb *phb = hose->private_data;
 350         struct pnv_ioda_pe *master_pe, *pe;
 351         unsigned long size, *pe_alloc;
 352         int i;
 353
 354         /* Root bus shouldn't use M64 */
 355         if (pci_is_root_bus(bus))
 356                 return NULL;
 357
 358         /* Allocate bitmap */
 359         size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
 360         pe_alloc = kzalloc(size, GFP_KERNEL);
 361         if (!pe_alloc) {
 362                 pr_warn("%s: Out of memory !\n",
 363                         __func__);
 364                 return NULL;
 365         }
 366
 367         /* Figure out reserved PE numbers by the PE */
 368         pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
 369
 370         /*
 371          * the current bus might not own M64 window and that's all
 372          * contributed by its child buses. For the case, we needn't
 373          * pick M64 dependent PE#.
 374          */
 375         if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
 376                 kfree(pe_alloc);
 377                 return NULL;
 378         }
 379
 380         /*
 381          * Figure out the master PE and put all slave PEs to master
 382          * PE's list to form compound PE.
 383          */
 384         master_pe = NULL;
 385         i = -1;
 386         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
 387                 phb->ioda.total_pe_num) {
 388                 pe = &phb->ioda.pe_array[i];
 389
 390                 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
 391                 if (!master_pe) {
 392                         pe->flags |= PNV_IODA_PE_MASTER;
 393                         INIT_LIST_HEAD(&pe->slaves);
 394                         master_pe = pe;
 395                 } else {
 396                         pe->flags |= PNV_IODA_PE_SLAVE;
 397                         pe->master = master_pe;
 398                         list_add_tail(&pe->list, &master_pe->slaves);
 399                 }
 400
 401                 /*
 402                  * P7IOC supports M64DT, which helps mapping M64 segment
 403                  * to one particular PE#. However, PHB3 has fixed mapping
 404                  * between M64 segment and PE#. In order to have same logic
 405                  * for P7IOC and PHB3, we enforce fixed mapping between M64
 406                  * segment and PE# on P7IOC.
 407                  */
 408                 if (phb->type == PNV_PHB_IODA1) {
 409                         int64_t rc;
 410
 411                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 412                                         pe->pe_number, OPAL_M64_WINDOW_TYPE,
 413                                         pe->pe_number / PNV_IODA1_M64_SEGS,
 414                                         pe->pe_number % PNV_IODA1_M64_SEGS);
 415                         if (rc != OPAL_SUCCESS)
 416                                 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
 417                                         __func__, rc, phb->hose->global_number,
 418                                         pe->pe_number);
 419                 }
 420         }
 421
 422         kfree(pe_alloc);
 423         return master_pe;
 424 }
 425
 426 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 427 {
 428         struct pci_controller *hose = phb->hose;
 429         struct device_node *dn = hose->dn;
 430         struct resource *res;
 431         u32 m64_range[2], i;
 432         const __be32 *r;
 433         u64 pci_addr;
 434
 435         if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
 436                 pr_info("  Not support M64 window\n");
 437                 return;
 438         }
 439
 440         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 441                 pr_info("  Firmware too old to support M64 window\n");
 442                 return;
 443         }
 444
 445         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 446         if (!r) {
 447                 pr_info("  No <ibm,opal-m64-window> on %pOF\n",
 448                         dn);
 449                 return;
 450         }
 451
 452         /*
 453          * Find the available M64 BAR range and pickup the last one for
 454          * covering the whole 64-bits space. We support only one range.
 455          */
 456         if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
 457                                        m64_range, 2)) {
 458                 /* In absence of the property, assume 0..15 */
 459                 m64_range[0] = 0;
 460                 m64_range[1] = 16;
 461         }
 462         /* We only support 64 bits in our allocator */
 463         if (m64_range[1] > 63) {
 464                 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
 465                         __func__, m64_range[1], phb->hose->global_number);
 466                 m64_range[1] = 63;
 467         }
 468         /* Empty range, no m64 */
 469         if (m64_range[1] <= m64_range[0]) {
 470                 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
 471                         __func__, phb->hose->global_number);
 472                 return;
 473         }
 474
 475         /* Configure M64 informations */
 476         res = &hose->mem_resources[1];
 477         res->name = dn->full_name;
 478         res->start = of_translate_address(dn, r + 2);
 479         res->end = res->start + of_read_number(r + 4, 2) - 1;
 480         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 481         pci_addr = of_read_number(r, 2);
 482         hose->mem_offset[1] = res->start - pci_addr;
 483
 484         phb->ioda.m64_size = resource_size(res);
 485         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
 486         phb->ioda.m64_base = pci_addr;
 487
 488         /* This lines up nicely with the display from processing OF ranges */
 489         pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
 490                 res->start, res->end, pci_addr, m64_range[0],
 491                 m64_range[0] + m64_range[1] - 1);
 492
 493         /* Mark all M64 used up by default */
 494         phb->ioda.m64_bar_alloc = (unsigned long)-1;
 495
 496         /* Use last M64 BAR to cover M64 window */
 497         m64_range[1]--;
 498         phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
 499
 500         pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
 501
 502         /* Mark remaining ones free */
 503         for (i = m64_range[0]; i < m64_range[1]; i++)
 504                 clear_bit(i, &phb->ioda.m64_bar_alloc);
 505
 506         /*
 507          * Setup init functions for M64 based on IODA version, IODA3 uses
 508          * the IODA2 code.
 509          */
 510         if (phb->type == PNV_PHB_IODA1)
 511                 phb->init_m64 = pnv_ioda1_init_m64;
 512         else
 513                 phb->init_m64 = pnv_ioda2_init_m64;
 514         phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
 515         phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
 516 }
 517
 518 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 519 {
 520         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 521         struct pnv_ioda_pe *slave;
 522         s64 rc;
 523
 524         /* Fetch master PE */
 525         if (pe->flags & PNV_IODA_PE_SLAVE) {
 526                 pe = pe->master;
 527                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 528                         return;
 529
 530                 pe_no = pe->pe_number;
 531         }
 532
 533         /* Freeze master PE */
 534         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 535                                      pe_no,
 536                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 537         if (rc != OPAL_SUCCESS) {
 538                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 539                         __func__, rc, phb->hose->global_number, pe_no);
 540                 return;
 541         }
 542
 543         /* Freeze slave PEs */
 544         if (!(pe->flags & PNV_IODA_PE_MASTER))
 545                 return;
 546
 547         list_for_each_entry(slave, &pe->slaves, list) {
 548                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 549                                              slave->pe_number,
 550                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 551                 if (rc != OPAL_SUCCESS)
 552                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 553                                 __func__, rc, phb->hose->global_number,
 554                                 slave->pe_number);
 555         }
 556 }
 557
 558 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 559 {
 560         struct pnv_ioda_pe *pe, *slave;
 561         s64 rc;
 562
 563         /* Find master PE */
 564         pe = &phb->ioda.pe_array[pe_no];
 565         if (pe->flags & PNV_IODA_PE_SLAVE) {
 566                 pe = pe->master;
 567                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 568                 pe_no = pe->pe_number;
 569         }
 570
 571         /* Clear frozen state for master PE */
 572         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 573         if (rc != OPAL_SUCCESS) {
 574                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 575                         __func__, rc, opt, phb->hose->global_number, pe_no);
 576                 return -EIO;
 577         }
 578
 579         if (!(pe->flags & PNV_IODA_PE_MASTER))
 580                 return 0;
 581
 582         /* Clear frozen state for slave PEs */
 583         list_for_each_entry(slave, &pe->slaves, list) {
 584                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 585                                              slave->pe_number,
 586                                              opt);
 587                 if (rc != OPAL_SUCCESS) {
 588                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 589                                 __func__, rc, opt, phb->hose->global_number,
 590                                 slave->pe_number);
 591                         return -EIO;
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 599 {
 600         struct pnv_ioda_pe *slave, *pe;
 601         u8 fstate = 0, state;
 602         __be16 pcierr = 0;
 603         s64 rc;
 604
 605         /* Sanity check on PE number */
 606         if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
 607                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 608
 609         /*
 610          * Fetch the master PE and the PE instance might be
 611          * not initialized yet.
 612          */
 613         pe = &phb->ioda.pe_array[pe_no];
 614         if (pe->flags & PNV_IODA_PE_SLAVE) {
 615                 pe = pe->master;
 616                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 617                 pe_no = pe->pe_number;
 618         }
 619
 620         /* Check the master PE */
 621         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 622                                         &state, &pcierr, NULL);
 623         if (rc != OPAL_SUCCESS) {
 624                 pr_warn("%s: Failure %lld getting "
 625                         "PHB#%x-PE#%x state\n",
 626                         __func__, rc,
 627                         phb->hose->global_number, pe_no);
 628                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 629         }
 630
 631         /* Check the slave PE */
 632         if (!(pe->flags & PNV_IODA_PE_MASTER))
 633                 return state;
 634
 635         list_for_each_entry(slave, &pe->slaves, list) {
 636                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 637                                                 slave->pe_number,
 638                                                 &fstate,
 639                                                 &pcierr,
 640                                                 NULL);
 641                 if (rc != OPAL_SUCCESS) {
 642                         pr_warn("%s: Failure %lld getting "
 643                                 "PHB#%x-PE#%x state\n",
 644                                 __func__, rc,
 645                                 phb->hose->global_number, slave->pe_number);
 646                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 647                 }
 648
 649                 /*
 650                  * Override the result based on the ascending
 651                  * priority.
 652                  */
 653                 if (fstate > state)
 654                         state = fstate;
 655         }
 656
 657         return state;
 658 }
 659
 660 /* Currently those 2 are only used when MSIs are enabled, this will change
 661  * but in the meantime, we need to protect them to avoid warnings
 662  */
 663 #ifdef CONFIG_PCI_MSI
 664 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 665 {
 666         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 667         struct pnv_phb *phb = hose->private_data;
 668         struct pci_dn *pdn = pci_get_pdn(dev);
 669
 670         if (!pdn)
 671                 return NULL;
 672         if (pdn->pe_number == IODA_INVALID_PE)
 673                 return NULL;
 674         return &phb->ioda.pe_array[pdn->pe_number];
 675 }
 676 #endif /* CONFIG_PCI_MSI */
 677
 678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 679                                   struct pnv_ioda_pe *parent,
 680                                   struct pnv_ioda_pe *child,
 681                                   bool is_add)
 682 {
 683         const char *desc = is_add ? "adding" : "removing";
 684         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 685                               OPAL_REMOVE_PE_FROM_DOMAIN;
 686         struct pnv_ioda_pe *slave;
 687         long rc;
 688
 689         /* Parent PE affects child PE */
 690         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 691                                 child->pe_number, op);
 692         if (rc != OPAL_SUCCESS) {
 693                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 694                         rc, desc);
 695                 return -ENXIO;
 696         }
 697
 698         if (!(child->flags & PNV_IODA_PE_MASTER))
 699                 return 0;
 700
 701         /* Compound case: parent PE affects slave PEs */
 702         list_for_each_entry(slave, &child->slaves, list) {
 703                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 704                                         slave->pe_number, op);
 705                 if (rc != OPAL_SUCCESS) {
 706                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 707                                 rc, desc);
 708                         return -ENXIO;
 709                 }
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 716                               struct pnv_ioda_pe *pe,
 717                               bool is_add)
 718 {
 719         struct pnv_ioda_pe *slave;
 720         struct pci_dev *pdev = NULL;
 721         int ret;
 722
 723         /*
 724          * Clear PE frozen state. If it's master PE, we need
 725          * clear slave PE frozen state as well.
 726          */
 727         if (is_add) {
 728                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 729                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 730                 if (pe->flags & PNV_IODA_PE_MASTER) {
 731                         list_for_each_entry(slave, &pe->slaves, list)
 732                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 733                                                           slave->pe_number,
 734                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 735                 }
 736         }
 737
 738         /*
 739          * Associate PE in PELT. We need add the PE into the
 740          * corresponding PELT-V as well. Otherwise, the error
 741          * originated from the PE might contribute to other
 742          * PEs.
 743          */
 744         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 745         if (ret)
 746                 return ret;
 747
 748         /* For compound PEs, any one affects all of them */
 749         if (pe->flags & PNV_IODA_PE_MASTER) {
 750                 list_for_each_entry(slave, &pe->slaves, list) {
 751                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 752                         if (ret)
 753                                 return ret;
 754                 }
 755         }
 756
 757         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 758                 pdev = pe->pbus->self;
 759         else if (pe->flags & PNV_IODA_PE_DEV)
 760                 pdev = pe->pdev->bus->self;
 761 #ifdef CONFIG_PCI_IOV
 762         else if (pe->flags & PNV_IODA_PE_VF)
 763                 pdev = pe->parent_dev;
 764 #endif /* CONFIG_PCI_IOV */
 765         while (pdev) {
 766                 struct pci_dn *pdn = pci_get_pdn(pdev);
 767                 struct pnv_ioda_pe *parent;
 768
 769                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 770                         parent = &phb->ioda.pe_array[pdn->pe_number];
 771                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 772                         if (ret)
 773                                 return ret;
 774                 }
 775
 776                 pdev = pdev->bus->self;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 783 {
 784         struct pci_dev *parent;
 785         uint8_t bcomp, dcomp, fcomp;
 786         int64_t rc;
 787         long rid_end, rid;
 788
 789         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 790         if (pe->pbus) {
 791                 int count;
 792
 793                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 794                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 795                 parent = pe->pbus->self;
 796                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 797                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 798                 else
 799                         count = 1;
 800
 801                 switch(count) {
 802                 case  1: bcomp = OpalPciBusAll;         break;
 803                 case  2: bcomp = OpalPciBus7Bits;       break;
 804                 case  4: bcomp = OpalPciBus6Bits;       break;
 805                 case  8: bcomp = OpalPciBus5Bits;       break;
 806                 case 16: bcomp = OpalPciBus4Bits;       break;
 807                 case 32: bcomp = OpalPciBus3Bits;       break;
 808                 default:
 809                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 810                                 count);
 811                         /* Do an exact match only */
 812                         bcomp = OpalPciBusAll;
 813                 }
 814                 rid_end = pe->rid + (count << 8);
 815         } else {
 816 #ifdef CONFIG_PCI_IOV
 817                 if (pe->flags & PNV_IODA_PE_VF)
 818                         parent = pe->parent_dev;
 819                 else
 820 #endif
 821                         parent = pe->pdev->bus->self;
 822                 bcomp = OpalPciBusAll;
 823                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 824                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 825                 rid_end = pe->rid + 1;
 826         }
 827
 828         /* Clear the reverse map */
 829         for (rid = pe->rid; rid < rid_end; rid++)
 830                 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
 831
 832         /* Release from all parents PELT-V */
 833         while (parent) {
 834                 struct pci_dn *pdn = pci_get_pdn(parent);
 835                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 836                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 837                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 838                         /* XXX What to do in case of error ? */
 839                 }
 840                 parent = parent->bus->self;
 841         }
 842
 843         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 844                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 845
 846         /* Disassociate PE in PELT */
 847         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 848                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 849         if (rc)
 850                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 851         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 852                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 853         if (rc)
 854                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 855
 856         pe->pbus = NULL;
 857         pe->pdev = NULL;
 858 #ifdef CONFIG_PCI_IOV
 859         pe->parent_dev = NULL;
 860 #endif
 861
 862         return 0;
 863 }
 864
 865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 866 {
 867         struct pci_dev *parent;
 868         uint8_t bcomp, dcomp, fcomp;
 869         long rc, rid_end, rid;
 870
 871         /* Bus validation ? */
 872         if (pe->pbus) {
 873                 int count;
 874
 875                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 876                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 877                 parent = pe->pbus->self;
 878                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 879                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 880                 else
 881                         count = 1;
 882
 883                 switch(count) {
 884                 case  1: bcomp = OpalPciBusAll;         break;
 885                 case  2: bcomp = OpalPciBus7Bits;       break;
 886                 case  4: bcomp = OpalPciBus6Bits;       break;
 887                 case  8: bcomp = OpalPciBus5Bits;       break;
 888                 case 16: bcomp = OpalPciBus4Bits;       break;
 889                 case 32: bcomp = OpalPciBus3Bits;       break;
 890                 default:
 891                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 892                                 count);
 893                         /* Do an exact match only */
 894                         bcomp = OpalPciBusAll;
 895                 }
 896                 rid_end = pe->rid + (count << 8);
 897         } else {
 898 #ifdef CONFIG_PCI_IOV
 899                 if (pe->flags & PNV_IODA_PE_VF)
 900                         parent = pe->parent_dev;
 901                 else
 902 #endif /* CONFIG_PCI_IOV */
 903                         parent = pe->pdev->bus->self;
 904                 bcomp = OpalPciBusAll;
 905                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 906                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 907                 rid_end = pe->rid + 1;
 908         }
 909
 910         /*
 911          * Associate PE in PELT. We need add the PE into the
 912          * corresponding PELT-V as well. Otherwise, the error
 913          * originated from the PE might contribute to other
 914          * PEs.
 915          */
 916         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 917                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 918         if (rc) {
 919                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 920                 return -ENXIO;
 921         }
 922
 923         /*
 924          * Configure PELTV. NPUs don't have a PELTV table so skip
 925          * configuration on them.
 926          */
 927         if (phb->type != PNV_PHB_NPU)
 928                 pnv_ioda_set_peltv(phb, pe, true);
 929
 930         /* Setup reverse map */
 931         for (rid = pe->rid; rid < rid_end; rid++)
 932                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 933
 934         /* Setup one MVTs on IODA1 */
 935         if (phb->type != PNV_PHB_IODA1) {
 936                 pe->mve_number = 0;
 937                 goto out;
 938         }
 939
 940         pe->mve_number = pe->pe_number;
 941         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 942         if (rc != OPAL_SUCCESS) {
 943                 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
 944                        rc, pe->mve_number);
 945                 pe->mve_number = -1;
 946         } else {
 947                 rc = opal_pci_set_mve_enable(phb->opal_id,
 948                                              pe->mve_number, OPAL_ENABLE_MVE);
 949                 if (rc) {
 950                         pe_err(pe, "OPAL error %ld enabling MVE %x\n",
 951                                rc, pe->mve_number);
 952                         pe->mve_number = -1;
 953                 }
 954         }
 955
 956 out:
 957         return 0;
 958 }
 959
 960 #ifdef CONFIG_PCI_IOV
 961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 962 {
 963         struct pci_dn *pdn = pci_get_pdn(dev);
 964         int i;
 965         struct resource *res, res2;
 966         resource_size_t size;
 967         u16 num_vfs;
 968
 969         if (!dev->is_physfn)
 970                 return -EINVAL;
 971
 972         /*
 973          * "offset" is in VFs.  The M64 windows are sized so that when they
 974          * are segmented, each segment is the same size as the IOV BAR.
 975          * Each segment is in a separate PE, and the high order bits of the
 976          * address are the PE number.  Therefore, each VF's BAR is in a
 977          * separate PE, and changing the IOV BAR start address changes the
 978          * range of PEs the VFs are in.
 979          */
 980         num_vfs = pdn->num_vfs;
 981         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 982                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 983                 if (!res->flags || !res->parent)
 984                         continue;
 985
 986                 /*
 987                  * The actual IOV BAR range is determined by the start address
 988                  * and the actual size for num_vfs VFs BAR.  This check is to
 989                  * make sure that after shifting, the range will not overlap
 990                  * with another device.
 991                  */
 992                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 993                 res2.flags = res->flags;
 994                 res2.start = res->start + (size * offset);
 995                 res2.end = res2.start + (size * num_vfs) - 1;
 996
 997                 if (res2.end > res->end) {
 998                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 999                                 i, &res2, res, num_vfs, offset);
1000                         return -EBUSY;
1001                 }
1002         }
1003
1004         /*
1005          * After doing so, there would be a "hole" in the /proc/iomem when
1006          * offset is a positive value. It looks like the device return some
1007          * mmio back to the system, which actually no one could use it.
1008          */
1009         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1010                 res = &dev->resource[i + PCI_IOV_RESOURCES];
1011                 if (!res->flags || !res->parent)
1012                         continue;
1013
1014                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1015                 res2 = *res;
1016                 res->start += size * offset;
1017
1018                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1019                          i, &res2, res, (offset > 0) ? "En" : "Dis",
1020                          num_vfs, offset);
1021                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1022         }
1023         return 0;
1024 }
1025 #endif /* CONFIG_PCI_IOV */
1026
1027 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1028 {
1029         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1030         struct pnv_phb *phb = hose->private_data;
1031         struct pci_dn *pdn = pci_get_pdn(dev);
1032         struct pnv_ioda_pe *pe;
1033
1034         if (!pdn) {
1035                 pr_err("%s: Device tree node not associated properly\n",
1036                            pci_name(dev));
1037                 return NULL;
1038         }
1039         if (pdn->pe_number != IODA_INVALID_PE)
1040                 return NULL;
1041
1042         pe = pnv_ioda_alloc_pe(phb);
1043         if (!pe) {
1044                 pr_warning("%s: Not enough PE# available, disabling device\n",
1045                            pci_name(dev));
1046                 return NULL;
1047         }
1048
1049         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1050          * pointer in the PE data structure, both should be destroyed at the
1051          * same time. However, this needs to be looked at more closely again
1052          * once we actually start removing things (Hotplug, SR-IOV, ...)
1053          *
1054          * At some point we want to remove the PDN completely anyways
1055          */
1056         pci_dev_get(dev);
1057         pdn->pcidev = dev;
1058         pdn->pe_number = pe->pe_number;
1059         pe->flags = PNV_IODA_PE_DEV;
1060         pe->pdev = dev;
1061         pe->pbus = NULL;
1062         pe->mve_number = -1;
1063         pe->rid = dev->bus->number << 8 | pdn->devfn;
1064
1065         pe_info(pe, "Associated device to PE\n");
1066
1067         if (pnv_ioda_configure_pe(phb, pe)) {
1068                 /* XXX What do we do here ? */
1069                 pnv_ioda_free_pe(pe);
1070                 pdn->pe_number = IODA_INVALID_PE;
1071                 pe->pdev = NULL;
1072                 pci_dev_put(dev);
1073                 return NULL;
1074         }
1075
1076         /* Put PE to the list */
1077         list_add_tail(&pe->list, &phb->ioda.pe_list);
1078
1079         return pe;
1080 }
1081
1082 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1083 {
1084         struct pci_dev *dev;
1085
1086         list_for_each_entry(dev, &bus->devices, bus_list) {
1087                 struct pci_dn *pdn = pci_get_pdn(dev);
1088
1089                 if (pdn == NULL) {
1090                         pr_warn("%s: No device node associated with device !\n",
1091                                 pci_name(dev));
1092                         continue;
1093                 }
1094
1095                 /*
1096                  * In partial hotplug case, the PCI device might be still
1097                  * associated with the PE and needn't attach it to the PE
1098                  * again.
1099                  */
1100                 if (pdn->pe_number != IODA_INVALID_PE)
1101                         continue;
1102
1103                 pe->device_count++;
1104                 pdn->pcidev = dev;
1105                 pdn->pe_number = pe->pe_number;
1106                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1107                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1108         }
1109 }
1110
1111 /*
1112  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1113  * single PCI bus. Another one that contains the primary PCI bus and its
1114  * subordinate PCI devices and buses. The second type of PE is normally
1115  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1116  */
1117 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1118 {
1119         struct pci_controller *hose = pci_bus_to_host(bus);
1120         struct pnv_phb *phb = hose->private_data;
1121         struct pnv_ioda_pe *pe = NULL;
1122         unsigned int pe_num;
1123
1124         /*
1125          * In partial hotplug case, the PE instance might be still alive.
1126          * We should reuse it instead of allocating a new one.
1127          */
1128         pe_num = phb->ioda.pe_rmap[bus->number << 8];
1129         if (pe_num != IODA_INVALID_PE) {
1130                 pe = &phb->ioda.pe_array[pe_num];
1131                 pnv_ioda_setup_same_PE(bus, pe);
1132                 return NULL;
1133         }
1134
1135         /* PE number for root bus should have been reserved */
1136         if (pci_is_root_bus(bus) &&
1137             phb->ioda.root_pe_idx != IODA_INVALID_PE)
1138                 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1139
1140         /* Check if PE is determined by M64 */
1141         if (!pe && phb->pick_m64_pe)
1142                 pe = phb->pick_m64_pe(bus, all);
1143
1144         /* The PE number isn't pinned by M64 */
1145         if (!pe)
1146                 pe = pnv_ioda_alloc_pe(phb);
1147
1148         if (!pe) {
1149                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1150                         __func__, pci_domain_nr(bus), bus->number);
1151                 return NULL;
1152         }
1153
1154         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1155         pe->pbus = bus;
1156         pe->pdev = NULL;
1157         pe->mve_number = -1;
1158         pe->rid = bus->busn_res.start << 8;
1159
1160         if (all)
1161                 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1162                         bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1163         else
1164                 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1165                         bus->busn_res.start, pe->pe_number);
1166
1167         if (pnv_ioda_configure_pe(phb, pe)) {
1168                 /* XXX What do we do here ? */
1169                 pnv_ioda_free_pe(pe);
1170                 pe->pbus = NULL;
1171                 return NULL;
1172         }
1173
1174         /* Associate it with all child devices */
1175         pnv_ioda_setup_same_PE(bus, pe);
1176
1177         /* Put PE to the list */
1178         list_add_tail(&pe->list, &phb->ioda.pe_list);
1179
1180         return pe;
1181 }
1182
1183 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1184 {
1185         int pe_num, found_pe = false, rc;
1186         long rid;
1187         struct pnv_ioda_pe *pe;
1188         struct pci_dev *gpu_pdev;
1189         struct pci_dn *npu_pdn;
1190         struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1191         struct pnv_phb *phb = hose->private_data;
1192
1193         /*
1194          * Due to a hardware errata PE#0 on the NPU is reserved for
1195          * error handling. This means we only have three PEs remaining
1196          * which need to be assigned to four links, implying some
1197          * links must share PEs.
1198          *
1199          * To achieve this we assign PEs such that NPUs linking the
1200          * same GPU get assigned the same PE.
1201          */
1202         gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1203         for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1204                 pe = &phb->ioda.pe_array[pe_num];
1205                 if (!pe->pdev)
1206                         continue;
1207
1208                 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1209                         /*
1210                          * This device has the same peer GPU so should
1211                          * be assigned the same PE as the existing
1212                          * peer NPU.
1213                          */
1214                         dev_info(&npu_pdev->dev,
1215                                 "Associating to existing PE %x\n", pe_num);
1216                         pci_dev_get(npu_pdev);
1217                         npu_pdn = pci_get_pdn(npu_pdev);
1218                         rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1219                         npu_pdn->pcidev = npu_pdev;
1220                         npu_pdn->pe_number = pe_num;
1221                         phb->ioda.pe_rmap[rid] = pe->pe_number;
1222
1223                         /* Map the PE to this link */
1224                         rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1225                                         OpalPciBusAll,
1226                                         OPAL_COMPARE_RID_DEVICE_NUMBER,
1227                                         OPAL_COMPARE_RID_FUNCTION_NUMBER,
1228                                         OPAL_MAP_PE);
1229                         WARN_ON(rc != OPAL_SUCCESS);
1230                         found_pe = true;
1231                         break;
1232                 }
1233         }
1234
1235         if (!found_pe)
1236                 /*
1237                  * Could not find an existing PE so allocate a new
1238                  * one.
1239                  */
1240                 return pnv_ioda_setup_dev_PE(npu_pdev);
1241         else
1242                 return pe;
1243 }
1244
1245 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1246 {
1247         struct pci_dev *pdev;
1248
1249         list_for_each_entry(pdev, &bus->devices, bus_list)
1250                 pnv_ioda_setup_npu_PE(pdev);
1251 }
1252
1253 static void pnv_pci_ioda_setup_PEs(void)
1254 {
1255         struct pci_controller *hose, *tmp;
1256         struct pnv_phb *phb;
1257
1258         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1259                 phb = hose->private_data;
1260                 if (phb->type == PNV_PHB_NPU) {
1261                         /* PE#0 is needed for error reporting */
1262                         pnv_ioda_reserve_pe(phb, 0);
1263                         pnv_ioda_setup_npu_PEs(hose->bus);
1264                         if (phb->model == PNV_PHB_MODEL_NPU2)
1265                                 pnv_npu2_init(phb);
1266                 }
1267         }
1268 }
1269
1270 #ifdef CONFIG_PCI_IOV
1271 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1272 {
1273         struct pci_bus        *bus;
1274         struct pci_controller *hose;
1275         struct pnv_phb        *phb;
1276         struct pci_dn         *pdn;
1277         int                    i, j;
1278         int                    m64_bars;
1279
1280         bus = pdev->bus;
1281         hose = pci_bus_to_host(bus);
1282         phb = hose->private_data;
1283         pdn = pci_get_pdn(pdev);
1284
1285         if (pdn->m64_single_mode)
1286                 m64_bars = num_vfs;
1287         else
1288                 m64_bars = 1;
1289
1290         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1291                 for (j = 0; j < m64_bars; j++) {
1292                         if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1293                                 continue;
1294                         opal_pci_phb_mmio_enable(phb->opal_id,
1295                                 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1296                         clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1297                         pdn->m64_map[j][i] = IODA_INVALID_M64;
1298                 }
1299
1300         kfree(pdn->m64_map);
1301         return 0;
1302 }
1303
1304 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1305 {
1306         struct pci_bus        *bus;
1307         struct pci_controller *hose;
1308         struct pnv_phb        *phb;
1309         struct pci_dn         *pdn;
1310         unsigned int           win;
1311         struct resource       *res;
1312         int                    i, j;
1313         int64_t                rc;
1314         int                    total_vfs;
1315         resource_size_t        size, start;
1316         int                    pe_num;
1317         int                    m64_bars;
1318
1319         bus = pdev->bus;
1320         hose = pci_bus_to_host(bus);
1321         phb = hose->private_data;
1322         pdn = pci_get_pdn(pdev);
1323         total_vfs = pci_sriov_get_totalvfs(pdev);
1324
1325         if (pdn->m64_single_mode)
1326                 m64_bars = num_vfs;
1327         else
1328                 m64_bars = 1;
1329
1330         pdn->m64_map = kmalloc_array(m64_bars,
1331                                      sizeof(*pdn->m64_map),
1332                                      GFP_KERNEL);
1333         if (!pdn->m64_map)
1334                 return -ENOMEM;
1335         /* Initialize the m64_map to IODA_INVALID_M64 */
1336         for (i = 0; i < m64_bars ; i++)
1337                 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1338                         pdn->m64_map[i][j] = IODA_INVALID_M64;
1339
1340
1341         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1342                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1343                 if (!res->flags || !res->parent)
1344                         continue;
1345
1346                 for (j = 0; j < m64_bars; j++) {
1347                         do {
1348                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1349                                                 phb->ioda.m64_bar_idx + 1, 0);
1350
1351                                 if (win >= phb->ioda.m64_bar_idx + 1)
1352                                         goto m64_failed;
1353                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1354
1355                         pdn->m64_map[j][i] = win;
1356
1357                         if (pdn->m64_single_mode) {
1358                                 size = pci_iov_resource_size(pdev,
1359                                                         PCI_IOV_RESOURCES + i);
1360                                 start = res->start + size * j;
1361                         } else {
1362                                 size = resource_size(res);
1363                                 start = res->start;
1364                         }
1365
1366                         /* Map the M64 here */
1367                         if (pdn->m64_single_mode) {
1368                                 pe_num = pdn->pe_num_map[j];
1369                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1370                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1371                                                 pdn->m64_map[j][i], 0);
1372                         }
1373
1374                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1375                                                  OPAL_M64_WINDOW_TYPE,
1376                                                  pdn->m64_map[j][i],
1377                                                  start,
1378                                                  0, /* unused */
1379                                                  size);
1380
1381
1382                         if (rc != OPAL_SUCCESS) {
1383                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1384                                         win, rc);
1385                                 goto m64_failed;
1386                         }
1387
1388                         if (pdn->m64_single_mode)
1389                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1390                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1391                         else
1392                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1393                                      OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1394
1395                         if (rc != OPAL_SUCCESS) {
1396                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1397                                         win, rc);
1398                                 goto m64_failed;
1399                         }
1400                 }
1401         }
1402         return 0;
1403
1404 m64_failed:
1405         pnv_pci_vf_release_m64(pdev, num_vfs);
1406         return -EBUSY;
1407 }
1408
1409 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1410                 int num);
1411
1412 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1413 {
1414         struct iommu_table    *tbl;
1415         int64_t               rc;
1416
1417         tbl = pe->table_group.tables[0];
1418         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1419         if (rc)
1420                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1421
1422         pnv_pci_ioda2_set_bypass(pe, false);
1423         if (pe->table_group.group) {
1424                 iommu_group_put(pe->table_group.group);
1425                 BUG_ON(pe->table_group.group);
1426         }
1427         iommu_tce_table_put(tbl);
1428 }
1429
1430 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1431 {
1432         struct pci_bus        *bus;
1433         struct pci_controller *hose;
1434         struct pnv_phb        *phb;
1435         struct pnv_ioda_pe    *pe, *pe_n;
1436         struct pci_dn         *pdn;
1437
1438         bus = pdev->bus;
1439         hose = pci_bus_to_host(bus);
1440         phb = hose->private_data;
1441         pdn = pci_get_pdn(pdev);
1442
1443         if (!pdev->is_physfn)
1444                 return;
1445
1446         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1447                 if (pe->parent_dev != pdev)
1448                         continue;
1449
1450                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1451
1452                 /* Remove from list */
1453                 mutex_lock(&phb->ioda.pe_list_mutex);
1454                 list_del(&pe->list);
1455                 mutex_unlock(&phb->ioda.pe_list_mutex);
1456
1457                 pnv_ioda_deconfigure_pe(phb, pe);
1458
1459                 pnv_ioda_free_pe(pe);
1460         }
1461 }
1462
1463 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1464 {
1465         struct pci_bus        *bus;
1466         struct pci_controller *hose;
1467         struct pnv_phb        *phb;
1468         struct pnv_ioda_pe    *pe;
1469         struct pci_dn         *pdn;
1470         u16                    num_vfs, i;
1471
1472         bus = pdev->bus;
1473         hose = pci_bus_to_host(bus);
1474         phb = hose->private_data;
1475         pdn = pci_get_pdn(pdev);
1476         num_vfs = pdn->num_vfs;
1477
1478         /* Release VF PEs */
1479         pnv_ioda_release_vf_PE(pdev);
1480
1481         if (phb->type == PNV_PHB_IODA2) {
1482                 if (!pdn->m64_single_mode)
1483                         pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1484
1485                 /* Release M64 windows */
1486                 pnv_pci_vf_release_m64(pdev, num_vfs);
1487
1488                 /* Release PE numbers */
1489                 if (pdn->m64_single_mode) {
1490                         for (i = 0; i < num_vfs; i++) {
1491                                 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1492                                         continue;
1493
1494                                 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1495                                 pnv_ioda_free_pe(pe);
1496                         }
1497                 } else
1498                         bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1499                 /* Releasing pe_num_map */
1500                 kfree(pdn->pe_num_map);
1501         }
1502 }
1503
1504 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1505                                        struct pnv_ioda_pe *pe);
1506 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1507 {
1508         struct pci_bus        *bus;
1509         struct pci_controller *hose;
1510         struct pnv_phb        *phb;
1511         struct pnv_ioda_pe    *pe;
1512         int                    pe_num;
1513         u16                    vf_index;
1514         struct pci_dn         *pdn;
1515
1516         bus = pdev->bus;
1517         hose = pci_bus_to_host(bus);
1518         phb = hose->private_data;
1519         pdn = pci_get_pdn(pdev);
1520
1521         if (!pdev->is_physfn)
1522                 return;
1523
1524         /* Reserve PE for each VF */
1525         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1526                 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1527                 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1528                 struct pci_dn *vf_pdn;
1529
1530                 if (pdn->m64_single_mode)
1531                         pe_num = pdn->pe_num_map[vf_index];
1532                 else
1533                         pe_num = *pdn->pe_num_map + vf_index;
1534
1535                 pe = &phb->ioda.pe_array[pe_num];
1536                 pe->pe_number = pe_num;
1537                 pe->phb = phb;
1538                 pe->flags = PNV_IODA_PE_VF;
1539                 pe->pbus = NULL;
1540                 pe->parent_dev = pdev;
1541                 pe->mve_number = -1;
1542                 pe->rid = (vf_bus << 8) | vf_devfn;
1543
1544                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1545                         hose->global_number, pdev->bus->number,
1546                         PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1547
1548                 if (pnv_ioda_configure_pe(phb, pe)) {
1549                         /* XXX What do we do here ? */
1550                         pnv_ioda_free_pe(pe);
1551                         pe->pdev = NULL;
1552                         continue;
1553                 }
1554
1555                 /* Put PE to the list */
1556                 mutex_lock(&phb->ioda.pe_list_mutex);
1557                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1558                 mutex_unlock(&phb->ioda.pe_list_mutex);
1559
1560                 /* associate this pe to it's pdn */
1561                 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1562                         if (vf_pdn->busno == vf_bus &&
1563                             vf_pdn->devfn == vf_devfn) {
1564                                 vf_pdn->pe_number = pe_num;
1565                                 break;
1566                         }
1567                 }
1568
1569                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1570         }
1571 }
1572
1573 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1574 {
1575         struct pci_bus        *bus;
1576         struct pci_controller *hose;
1577         struct pnv_phb        *phb;
1578         struct pnv_ioda_pe    *pe;
1579         struct pci_dn         *pdn;
1580         int                    ret;
1581         u16                    i;
1582
1583         bus = pdev->bus;
1584         hose = pci_bus_to_host(bus);
1585         phb = hose->private_data;
1586         pdn = pci_get_pdn(pdev);
1587
1588         if (phb->type == PNV_PHB_IODA2) {
1589                 if (!pdn->vfs_expanded) {
1590                         dev_info(&pdev->dev, "don't support this SRIOV device"
1591                                 " with non 64bit-prefetchable IOV BAR\n");
1592                         return -ENOSPC;
1593                 }
1594
1595                 /*
1596                  * When M64 BARs functions in Single PE mode, the number of VFs
1597                  * could be enabled must be less than the number of M64 BARs.
1598                  */
1599                 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1600                         dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1601                         return -EBUSY;
1602                 }
1603
1604                 /* Allocating pe_num_map */
1605                 if (pdn->m64_single_mode)
1606                         pdn->pe_num_map = kmalloc_array(num_vfs,
1607                                                         sizeof(*pdn->pe_num_map),
1608                                                         GFP_KERNEL);
1609                 else
1610                         pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1611
1612                 if (!pdn->pe_num_map)
1613                         return -ENOMEM;
1614
1615                 if (pdn->m64_single_mode)
1616                         for (i = 0; i < num_vfs; i++)
1617                                 pdn->pe_num_map[i] = IODA_INVALID_PE;
1618
1619                 /* Calculate available PE for required VFs */
1620                 if (pdn->m64_single_mode) {
1621                         for (i = 0; i < num_vfs; i++) {
1622                                 pe = pnv_ioda_alloc_pe(phb);
1623                                 if (!pe) {
1624                                         ret = -EBUSY;
1625                                         goto m64_failed;
1626                                 }
1627
1628                                 pdn->pe_num_map[i] = pe->pe_number;
1629                         }
1630                 } else {
1631                         mutex_lock(&phb->ioda.pe_alloc_mutex);
1632                         *pdn->pe_num_map = bitmap_find_next_zero_area(
1633                                 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1634                                 0, num_vfs, 0);
1635                         if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1636                                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1637                                 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1638                                 kfree(pdn->pe_num_map);
1639                                 return -EBUSY;
1640                         }
1641                         bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1642                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1643                 }
1644                 pdn->num_vfs = num_vfs;
1645
1646                 /* Assign M64 window accordingly */
1647                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1648                 if (ret) {
1649                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1650                         goto m64_failed;
1651                 }
1652
1653                 /*
1654                  * When using one M64 BAR to map one IOV BAR, we need to shift
1655                  * the IOV BAR according to the PE# allocated to the VFs.
1656                  * Otherwise, the PE# for the VF will conflict with others.
1657                  */
1658                 if (!pdn->m64_single_mode) {
1659                         ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1660                         if (ret)
1661                                 goto m64_failed;
1662                 }
1663         }
1664
1665         /* Setup VF PEs */
1666         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1667
1668         return 0;
1669
1670 m64_failed:
1671         if (pdn->m64_single_mode) {
1672                 for (i = 0; i < num_vfs; i++) {
1673                         if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1674                                 continue;
1675
1676                         pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1677                         pnv_ioda_free_pe(pe);
1678                 }
1679         } else
1680                 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1681
1682         /* Releasing pe_num_map */
1683         kfree(pdn->pe_num_map);
1684
1685         return ret;
1686 }
1687
1688 int pcibios_sriov_disable(struct pci_dev *pdev)
1689 {
1690         pnv_pci_sriov_disable(pdev);
1691
1692         /* Release PCI data */
1693         remove_dev_pci_data(pdev);
1694         return 0;
1695 }
1696
1697 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1698 {
1699         /* Allocate PCI data */
1700         add_dev_pci_data(pdev);
1701
1702         return pnv_pci_sriov_enable(pdev, num_vfs);
1703 }
1704 #endif /* CONFIG_PCI_IOV */
1705
1706 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1707 {
1708         struct pci_dn *pdn = pci_get_pdn(pdev);
1709         struct pnv_ioda_pe *pe;
1710
1711         /*
1712          * The function can be called while the PE#
1713          * hasn't been assigned. Do nothing for the
1714          * case.
1715          */
1716         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1717                 return;
1718
1719         pe = &phb->ioda.pe_array[pdn->pe_number];
1720         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1721         set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1722         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1723         /*
1724          * Note: iommu_add_device() will fail here as
1725          * for physical PE: the device is already added by now;
1726          * for virtual PE: sysfs entries are not ready yet and
1727          * tce_iommu_bus_notifier will add the device to a group later.
1728          */
1729 }
1730
1731 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1732 {
1733         unsigned short vendor = 0;
1734         struct pci_dev *pdev;
1735
1736         if (pe->device_count == 1)
1737                 return true;
1738
1739         /* pe->pdev should be set if it's a single device, pe->pbus if not */
1740         if (!pe->pbus)
1741                 return true;
1742
1743         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1744                 if (!vendor) {
1745                         vendor = pdev->vendor;
1746                         continue;
1747                 }
1748
1749                 if (pdev->vendor != vendor)
1750                         return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 /*
1757  * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1758  *
1759  * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1760  * Devices can only access more than that if bit 59 of the PCI address is set
1761  * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1762  * Many PCI devices are not capable of addressing that many bits, and as a
1763  * result are limited to the 4GB of virtual memory made available to 32-bit
1764  * devices in TVE#0.
1765  *
1766  * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1767  * devices by configuring the virtual memory past the first 4GB inaccessible
1768  * by 64-bit DMAs.  This should only be used by devices that want more than
1769  * 4GB, and only on PEs that have no 32-bit devices.
1770  *
1771  * Currently this will only work on PHB3 (POWER8).
1772  */
1773 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1774 {
1775         u64 window_size, table_size, tce_count, addr;
1776         struct page *table_pages;
1777         u64 tce_order = 28; /* 256MB TCEs */
1778         __be64 *tces;
1779         s64 rc;
1780
1781         /*
1782          * Window size needs to be a power of two, but needs to account for
1783          * shifting memory by the 4GB offset required to skip 32bit space.
1784          */
1785         window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1786         tce_count = window_size >> tce_order;
1787         table_size = tce_count << 3;
1788
1789         if (table_size < PAGE_SIZE)
1790                 table_size = PAGE_SIZE;
1791
1792         table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1793                                        get_order(table_size));
1794         if (!table_pages)
1795                 goto err;
1796
1797         tces = page_address(table_pages);
1798         if (!tces)
1799                 goto err;
1800
1801         memset(tces, 0, table_size);
1802
1803         for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1804                 tces[(addr + (1ULL << 32)) >> tce_order] =
1805                         cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1806         }
1807
1808         rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1809                                         pe->pe_number,
1810                                         /* reconfigure window 0 */
1811                                         (pe->pe_number << 1) + 0,
1812                                         1,
1813                                         __pa(tces),
1814                                         table_size,
1815                                         1 << tce_order);
1816         if (rc == OPAL_SUCCESS) {
1817                 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1818                 return 0;
1819         }
1820 err:
1821         pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1822         return -EIO;
1823 }
1824
1825 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1826 {
1827         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1828         struct pnv_phb *phb = hose->private_data;
1829         struct pci_dn *pdn = pci_get_pdn(pdev);
1830         struct pnv_ioda_pe *pe;
1831         uint64_t top;
1832         bool bypass = false;
1833         s64 rc;
1834
1835         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1836                 return -ENODEV;;
1837
1838         pe = &phb->ioda.pe_array[pdn->pe_number];
1839         if (pe->tce_bypass_enabled) {
1840                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1841                 bypass = (dma_mask >= top);
1842         }
1843
1844         if (bypass) {
1845                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1846                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1847         } else {
1848                 /*
1849                  * If the device can't set the TCE bypass bit but still wants
1850                  * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1851                  * bypass the 32-bit region and be usable for 64-bit DMAs.
1852                  * The device needs to be able to address all of this space.
1853                  */
1854                 if (dma_mask >> 32 &&
1855                     dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1856                     pnv_pci_ioda_pe_single_vendor(pe) &&
1857                     phb->model == PNV_PHB_MODEL_PHB3) {
1858                         /* Configure the bypass mode */
1859                         rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1860                         if (rc)
1861                                 return rc;
1862                         /* 4GB offset bypasses 32-bit space */
1863                         set_dma_offset(&pdev->dev, (1ULL << 32));
1864                         set_dma_ops(&pdev->dev, &dma_direct_ops);
1865                 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1866                         /*
1867                          * Fail the request if a DMA mask between 32 and 64 bits
1868                          * was requested but couldn't be fulfilled. Ideally we
1869                          * would do this for 64-bits but historically we have
1870                          * always fallen back to 32-bits.
1871                          */
1872                         return -ENOMEM;
1873                 } else {
1874                         dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1875                         set_dma_ops(&pdev->dev, &dma_iommu_ops);
1876                 }
1877         }
1878         *pdev->dev.dma_mask = dma_mask;
1879
1880         /* Update peer npu devices */
1881         pnv_npu_try_dma_set_bypass(pdev, bypass);
1882
1883         return 0;
1884 }
1885
1886 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1887 {
1888         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1889         struct pnv_phb *phb = hose->private_data;
1890         struct pci_dn *pdn = pci_get_pdn(pdev);
1891         struct pnv_ioda_pe *pe;
1892         u64 end, mask;
1893
1894         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1895                 return 0;
1896
1897         pe = &phb->ioda.pe_array[pdn->pe_number];
1898         if (!pe->tce_bypass_enabled)
1899                 return __dma_get_required_mask(&pdev->dev);
1900
1901
1902         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1903         mask = 1ULL << (fls64(end) - 1);
1904         mask += mask - 1;
1905
1906         return mask;
1907 }
1908
1909 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1910                                    struct pci_bus *bus,
1911                                    bool add_to_group)
1912 {
1913         struct pci_dev *dev;
1914
1915         list_for_each_entry(dev, &bus->devices, bus_list) {
1916                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1917                 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1918                 if (add_to_group)
1919                         iommu_add_device(&dev->dev);
1920
1921                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1922                         pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1923                                         add_to_group);
1924         }
1925 }
1926
1927 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1928                                                      bool real_mode)
1929 {
1930         return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1931                 (phb->regs + 0x210);
1932 }
1933
1934 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1935                 unsigned long index, unsigned long npages, bool rm)
1936 {
1937         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1938                         &tbl->it_group_list, struct iommu_table_group_link,
1939                         next);
1940         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1941                         struct pnv_ioda_pe, table_group);
1942         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1943         unsigned long start, end, inc;
1944
1945         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1946         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1947                         npages - 1);
1948
1949         /* p7ioc-style invalidation, 2 TCEs per write */
1950         start |= (1ull << 63);
1951         end |= (1ull << 63);
1952         inc = 16;
1953         end |= inc - 1; /* round up end to be different than start */
1954
1955         mb(); /* Ensure above stores are visible */
1956         while (start <= end) {
1957                 if (rm)
1958                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1959                 else
1960                         __raw_writeq(cpu_to_be64(start), invalidate);
1961                 start += inc;
1962         }
1963
1964         /*
1965          * The iommu layer will do another mb() for us on build()
1966          * and we don't care on free()
1967          */
1968 }
1969
1970 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1971                 long npages, unsigned long uaddr,
1972                 enum dma_data_direction direction,
1973                 unsigned long attrs)
1974 {
1975         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1976                         attrs);
1977
1978         if (!ret)
1979                 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1980
1981         return ret;
1982 }
1983
1984 #ifdef CONFIG_IOMMU_API
1985 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1986                 unsigned long *hpa, enum dma_data_direction *direction)
1987 {
1988         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1989
1990         if (!ret)
1991                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1992
1993         return ret;
1994 }
1995
1996 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1997                 unsigned long *hpa, enum dma_data_direction *direction)
1998 {
1999         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2000
2001         if (!ret)
2002                 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2003
2004         return ret;
2005 }
2006 #endif
2007
2008 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2009                 long npages)
2010 {
2011         pnv_tce_free(tbl, index, npages);
2012
2013         pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2014 }
2015
2016 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2017         .set = pnv_ioda1_tce_build,
2018 #ifdef CONFIG_IOMMU_API
2019         .exchange = pnv_ioda1_tce_xchg,
2020         .exchange_rm = pnv_ioda1_tce_xchg_rm,
2021 #endif
2022         .clear = pnv_ioda1_tce_free,
2023         .get = pnv_tce_get,
2024 };
2025
2026 #define PHB3_TCE_KILL_INVAL_ALL         PPC_BIT(0)
2027 #define PHB3_TCE_KILL_INVAL_PE          PPC_BIT(1)
2028 #define PHB3_TCE_KILL_INVAL_ONE         PPC_BIT(2)
2029
2030 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2031 {
2032         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2033         const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2034
2035         mb(); /* Ensure previous TCE table stores are visible */
2036         if (rm)
2037                 __raw_rm_writeq(cpu_to_be64(val), invalidate);
2038         else
2039                 __raw_writeq(cpu_to_be64(val), invalidate);
2040 }
2041
2042 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2043 {
2044         /* 01xb - invalidate TCEs that match the specified PE# */
2045         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2046         unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2047
2048         mb(); /* Ensure above stores are visible */
2049         __raw_writeq(cpu_to_be64(val), invalidate);
2050 }
2051
2052 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2053                                         unsigned shift, unsigned long index,
2054                                         unsigned long npages)
2055 {
2056         __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2057         unsigned long start, end, inc;
2058
2059         /* We'll invalidate DMA address in PE scope */
2060         start = PHB3_TCE_KILL_INVAL_ONE;
2061         start |= (pe->pe_number & 0xFF);
2062         end = start;
2063
2064         /* Figure out the start, end and step */
2065         start |= (index << shift);
2066         end |= ((index + npages - 1) << shift);
2067         inc = (0x1ull << shift);
2068         mb();
2069
2070         while (start <= end) {
2071                 if (rm)
2072                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
2073                 else
2074                         __raw_writeq(cpu_to_be64(start), invalidate);
2075                 start += inc;
2076         }
2077 }
2078
2079 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2080 {
2081         struct pnv_phb *phb = pe->phb;
2082
2083         if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2084                 pnv_pci_phb3_tce_invalidate_pe(pe);
2085         else
2086                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2087                                   pe->pe_number, 0, 0, 0);
2088 }
2089
2090 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2091                 unsigned long index, unsigned long npages, bool rm)
2092 {
2093         struct iommu_table_group_link *tgl;
2094
2095         list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2096                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2097                                 struct pnv_ioda_pe, table_group);
2098                 struct pnv_phb *phb = pe->phb;
2099                 unsigned int shift = tbl->it_page_shift;
2100
2101                 /*
2102                  * NVLink1 can use the TCE kill register directly as
2103                  * it's the same as PHB3. NVLink2 is different and
2104                  * should go via the OPAL call.
2105                  */
2106                 if (phb->model == PNV_PHB_MODEL_NPU) {
2107                         /*
2108                          * The NVLink hardware does not support TCE kill
2109                          * per TCE entry so we have to invalidate
2110                          * the entire cache for it.
2111                          */
2112                         pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2113                         continue;
2114                 }
2115                 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2116                         pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2117                                                     index, npages);
2118                 else
2119                         opal_pci_tce_kill(phb->opal_id,
2120                                           OPAL_PCI_TCE_KILL_PAGES,
2121                                           pe->pe_number, 1u << shift,
2122                                           index << shift, npages);
2123         }
2124 }
2125
2126 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2127 {
2128         if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2129                 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2130         else
2131                 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2132 }
2133
2134 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2135                 long npages, unsigned long uaddr,
2136                 enum dma_data_direction direction,
2137                 unsigned long attrs)
2138 {
2139         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2140                         attrs);
2141
2142         if (!ret)
2143                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2144
2145         return ret;
2146 }
2147
2148 #ifdef CONFIG_IOMMU_API
2149 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2150                 unsigned long *hpa, enum dma_data_direction *direction)
2151 {
2152         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2153
2154         if (!ret)
2155                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2156
2157         return ret;
2158 }
2159
2160 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2161                 unsigned long *hpa, enum dma_data_direction *direction)
2162 {
2163         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2164
2165         if (!ret)
2166                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2167
2168         return ret;
2169 }
2170 #endif
2171
2172 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2173                 long npages)
2174 {
2175         pnv_tce_free(tbl, index, npages);
2176
2177         pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2178 }
2179
2180 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2181 {
2182         pnv_pci_ioda2_table_free_pages(tbl);
2183 }
2184
2185 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2186         .set = pnv_ioda2_tce_build,
2187 #ifdef CONFIG_IOMMU_API
2188         .exchange = pnv_ioda2_tce_xchg,
2189         .exchange_rm = pnv_ioda2_tce_xchg_rm,
2190 #endif
2191         .clear = pnv_ioda2_tce_free,
2192         .get = pnv_tce_get,
2193         .free = pnv_ioda2_table_free,
2194 };
2195
2196 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2197 {
2198         unsigned int *weight = (unsigned int *)data;
2199
2200         /* This is quite simplistic. The "base" weight of a device
2201          * is 10. 0 means no DMA is to be accounted for it.
2202          */
2203         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2204                 return 0;
2205
2206         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2207             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2208             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2209                 *weight += 3;
2210         else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2211                 *weight += 15;
2212         else
2213                 *weight += 10;
2214
2215         return 0;
2216 }
2217
2218 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2219 {
2220         unsigned int weight = 0;
2221
2222         /* SRIOV VF has same DMA32 weight as its PF */
2223 #ifdef CONFIG_PCI_IOV
2224         if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2225                 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2226                 return weight;
2227         }
2228 #endif
2229
2230         if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2231                 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2232         } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2233                 struct pci_dev *pdev;
2234
2235                 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2236                         pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2237         } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2238                 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2239         }
2240
2241         return weight;
2242 }
2243
2244 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2245                                        struct pnv_ioda_pe *pe)
2246 {
2247
2248         struct page *tce_mem = NULL;
2249         struct iommu_table *tbl;
2250         unsigned int weight, total_weight = 0;
2251         unsigned int tce32_segsz, base, segs, avail, i;
2252         int64_t rc;
2253         void *addr;
2254
2255         /* XXX FIXME: Handle 64-bit only DMA devices */
2256         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2257         /* XXX FIXME: Allocate multi-level tables on PHB3 */
2258         weight = pnv_pci_ioda_pe_dma_weight(pe);
2259         if (!weight)
2260                 return;
2261
2262         pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2263                      &total_weight);
2264         segs = (weight * phb->ioda.dma32_count) / total_weight;
2265         if (!segs)
2266                 segs = 1;
2267
2268         /*
2269          * Allocate contiguous DMA32 segments. We begin with the expected
2270          * number of segments. With one more attempt, the number of DMA32
2271          * segments to be allocated is decreased by one until one segment
2272          * is allocated successfully.
2273          */
2274         do {
2275                 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2276                         for (avail = 0, i = base; i < base + segs; i++) {
2277                                 if (phb->ioda.dma32_segmap[i] ==
2278                                     IODA_INVALID_PE)
2279                                         avail++;
2280                         }
2281
2282                         if (avail == segs)
2283                                 goto found;
2284                 }
2285         } while (--segs);
2286
2287         if (!segs) {
2288                 pe_warn(pe, "No available DMA32 segments\n");
2289                 return;
2290         }
2291
2292 found:
2293         tbl = pnv_pci_table_alloc(phb->hose->node);
2294         if (WARN_ON(!tbl))
2295                 return;
2296
2297         iommu_register_group(&pe->table_group, phb->hose->global_number,
2298                         pe->pe_number);
2299         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2300
2301         /* Grab a 32-bit TCE table */
2302         pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2303                 weight, total_weight, base, segs);
2304         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2305                 base * PNV_IODA1_DMA32_SEGSIZE,
2306                 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2307
2308         /* XXX Currently, we allocate one big contiguous table for the
2309          * TCEs. We only really need one chunk per 256M of TCE space
2310          * (ie per segment) but that's an optimization for later, it
2311          * requires some added smarts with our get/put_tce implementation
2312          *
2313          * Each TCE page is 4KB in size and each TCE entry occupies 8
2314          * bytes
2315          */
2316         tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2317         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2318                                    get_order(tce32_segsz * segs));
2319         if (!tce_mem) {
2320                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2321                 goto fail;
2322         }
2323         addr = page_address(tce_mem);
2324         memset(addr, 0, tce32_segsz * segs);
2325
2326         /* Configure HW */
2327         for (i = 0; i < segs; i++) {
2328                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2329                                               pe->pe_number,
2330                                               base + i, 1,
2331                                               __pa(addr) + tce32_segsz * i,
2332                                               tce32_segsz, IOMMU_PAGE_SIZE_4K);
2333                 if (rc) {
2334                         pe_err(pe, " Failed to configure 32-bit TCE table,"
2335                                " err %ld\n", rc);
2336                         goto fail;
2337                 }
2338         }
2339
2340         /* Setup DMA32 segment mapping */
2341         for (i = base; i < base + segs; i++)
2342                 phb->ioda.dma32_segmap[i] = pe->pe_number;
2343
2344         /* Setup linux iommu table */
2345         pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2346                                   base * PNV_IODA1_DMA32_SEGSIZE,
2347                                   IOMMU_PAGE_SHIFT_4K);
2348
2349         tbl->it_ops = &pnv_ioda1_iommu_ops;
2350         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2351         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2352         iommu_init_table(tbl, phb->hose->node);
2353
2354         if (pe->flags & PNV_IODA_PE_DEV) {
2355                 /*
2356                  * Setting table base here only for carrying iommu_group
2357                  * further down to let iommu_add_device() do the job.
2358                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2359                  */
2360                 set_iommu_table_base(&pe->pdev->dev, tbl);
2361                 iommu_add_device(&pe->pdev->dev);
2362         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2363                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2364
2365         return;
2366  fail:
2367         /* XXX Failure: Try to fallback to 64-bit only ? */
2368         if (tce_mem)
2369                 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2370         if (tbl) {
2371                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2372                 iommu_tce_table_put(tbl);
2373         }
2374 }
2375
2376 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2377                 int num, struct iommu_table *tbl)
2378 {
2379         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2380                         table_group);
2381         struct pnv_phb *phb = pe->phb;
2382         int64_t rc;
2383         const unsigned long size = tbl->it_indirect_levels ?
2384                         tbl->it_level_size : tbl->it_size;
2385         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2386         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2387
2388         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2389                         start_addr, start_addr + win_size - 1,
2390                         IOMMU_PAGE_SIZE(tbl));
2391
2392         /*
2393          * Map TCE table through TVT. The TVE index is the PE number
2394          * shifted by 1 bit for 32-bits DMA space.
2395          */
2396         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2397                         pe->pe_number,
2398                         (pe->pe_number << 1) + num,
2399                         tbl->it_indirect_levels + 1,
2400                         __pa(tbl->it_base),
2401                         size << 3,
2402                         IOMMU_PAGE_SIZE(tbl));
2403         if (rc) {
2404                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2405                 return rc;
2406         }
2407
2408         pnv_pci_link_table_and_group(phb->hose->node, num,
2409                         tbl, &pe->table_group);
2410         pnv_pci_ioda2_tce_invalidate_pe(pe);
2411
2412         return 0;
2413 }
2414
2415 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2416 {
2417         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2418         int64_t rc;
2419
2420         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2421         if (enable) {
2422                 phys_addr_t top = memblock_end_of_DRAM();
2423
2424                 top = roundup_pow_of_two(top);
2425                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2426                                                      pe->pe_number,
2427                                                      window_id,
2428                                                      pe->tce_bypass_base,
2429                                                      top);
2430         } else {
2431                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2432                                                      pe->pe_number,
2433                                                      window_id,
2434                                                      pe->tce_bypass_base,
2435                                                      0);
2436         }
2437         if (rc)
2438                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2439         else
2440                 pe->tce_bypass_enabled = enable;
2441 }
2442
2443 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2444                 __u32 page_shift, __u64 window_size, __u32 levels,
2445                 struct iommu_table *tbl);
2446
2447 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2448                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2449                 struct iommu_table **ptbl)
2450 {
2451         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2452                         table_group);
2453         int nid = pe->phb->hose->node;
2454         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2455         long ret;
2456         struct iommu_table *tbl;
2457
2458         tbl = pnv_pci_table_alloc(nid);
2459         if (!tbl)
2460                 return -ENOMEM;
2461
2462         tbl->it_ops = &pnv_ioda2_iommu_ops;
2463
2464         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2465                         bus_offset, page_shift, window_size,
2466                         levels, tbl);
2467         if (ret) {
2468                 iommu_tce_table_put(tbl);
2469                 return ret;
2470         }
2471
2472         *ptbl = tbl;
2473
2474         return 0;
2475 }
2476
2477 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2478 {
2479         struct iommu_table *tbl = NULL;
2480         long rc;
2481
2482         /*
2483          * crashkernel= specifies the kdump kernel's maximum memory at
2484          * some offset and there is no guaranteed the result is a power
2485          * of 2, which will cause errors later.
2486          */
2487         const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2488
2489         /*
2490          * In memory constrained environments, e.g. kdump kernel, the
2491          * DMA window can be larger than available memory, which will
2492          * cause errors later.
2493          */
2494         const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2495
2496         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2497                         IOMMU_PAGE_SHIFT_4K,
2498                         window_size,
2499                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2500         if (rc) {
2501                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2502                                 rc);
2503                 return rc;
2504         }
2505
2506         iommu_init_table(tbl, pe->phb->hose->node);
2507
2508         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2509         if (rc) {
2510                 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2511                                 rc);
2512                 iommu_tce_table_put(tbl);
2513                 return rc;
2514         }
2515
2516         if (!pnv_iommu_bypass_disabled)
2517                 pnv_pci_ioda2_set_bypass(pe, true);
2518
2519         /*
2520          * Setting table base here only for carrying iommu_group
2521          * further down to let iommu_add_device() do the job.
2522          * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2523          */
2524         if (pe->flags & PNV_IODA_PE_DEV)
2525                 set_iommu_table_base(&pe->pdev->dev, tbl);
2526
2527         return 0;
2528 }
2529
2530 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2531 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2532                 int num)
2533 {
2534         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2535                         table_group);
2536         struct pnv_phb *phb = pe->phb;
2537         long ret;
2538
2539         pe_info(pe, "Removing DMA window #%d\n", num);
2540
2541         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2542                         (pe->pe_number << 1) + num,
2543                         0/* levels */, 0/* table address */,
2544                         0/* table size */, 0/* page size */);
2545         if (ret)
2546                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2547         else
2548                 pnv_pci_ioda2_tce_invalidate_pe(pe);
2549
2550         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2551
2552         return ret;
2553 }
2554 #endif
2555
2556 #ifdef CONFIG_IOMMU_API
2557 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2558                 __u64 window_size, __u32 levels)
2559 {
2560         unsigned long bytes = 0;
2561         const unsigned window_shift = ilog2(window_size);
2562         unsigned entries_shift = window_shift - page_shift;
2563         unsigned table_shift = entries_shift + 3;
2564         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2565         unsigned long direct_table_size;
2566
2567         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2568                         (window_size > memory_hotplug_max()) ||
2569                         !is_power_of_2(window_size))
2570                 return 0;
2571
2572         /* Calculate a direct table size from window_size and levels */
2573         entries_shift = (entries_shift + levels - 1) / levels;
2574         table_shift = entries_shift + 3;
2575         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2576         direct_table_size =  1UL << table_shift;
2577
2578         for ( ; levels; --levels) {
2579                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2580
2581                 tce_table_size /= direct_table_size;
2582                 tce_table_size <<= 3;
2583                 tce_table_size = max_t(unsigned long,
2584                                 tce_table_size, direct_table_size);
2585         }
2586
2587         return bytes;
2588 }
2589
2590 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2591 {
2592         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2593                                                 table_group);
2594         /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2595         struct iommu_table *tbl = pe->table_group.tables[0];
2596
2597         pnv_pci_ioda2_set_bypass(pe, false);
2598         pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2599         if (pe->pbus)
2600                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2601         iommu_tce_table_put(tbl);
2602 }
2603
2604 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2605 {
2606         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2607                                                 table_group);
2608
2609         pnv_pci_ioda2_setup_default_config(pe);
2610         if (pe->pbus)
2611                 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2612 }
2613
2614 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2615         .get_table_size = pnv_pci_ioda2_get_table_size,
2616         .create_table = pnv_pci_ioda2_create_table,
2617         .set_window = pnv_pci_ioda2_set_window,
2618         .unset_window = pnv_pci_ioda2_unset_window,
2619         .take_ownership = pnv_ioda2_take_ownership,
2620         .release_ownership = pnv_ioda2_release_ownership,
2621 };
2622
2623 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2624 {
2625         struct pci_controller *hose;
2626         struct pnv_phb *phb;
2627         struct pnv_ioda_pe **ptmppe = opaque;
2628         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2629         struct pci_dn *pdn = pci_get_pdn(pdev);
2630
2631         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2632                 return 0;
2633
2634         hose = pci_bus_to_host(pdev->bus);
2635         phb = hose->private_data;
2636         if (phb->type != PNV_PHB_NPU)
2637                 return 0;
2638
2639         *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2640
2641         return 1;
2642 }
2643
2644 /*
2645  * This returns PE of associated NPU.
2646  * This assumes that NPU is in the same IOMMU group with GPU and there is
2647  * no other PEs.
2648  */
2649 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2650                 struct iommu_table_group *table_group)
2651 {
2652         struct pnv_ioda_pe *npe = NULL;
2653         int ret = iommu_group_for_each_dev(table_group->group, &npe,
2654                         gpe_table_group_to_npe_cb);
2655
2656         BUG_ON(!ret || !npe);
2657
2658         return npe;
2659 }
2660
2661 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2662                 int num, struct iommu_table *tbl)
2663 {
2664         long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2665
2666         if (ret)
2667                 return ret;
2668
2669         ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2670         if (ret)
2671                 pnv_pci_ioda2_unset_window(table_group, num);
2672
2673         return ret;
2674 }
2675
2676 static long pnv_pci_ioda2_npu_unset_window(
2677                 struct iommu_table_group *table_group,
2678                 int num)
2679 {
2680         long ret = pnv_pci_ioda2_unset_window(table_group, num);
2681
2682         if (ret)
2683                 return ret;
2684
2685         return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2686 }
2687
2688 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2689 {
2690         /*
2691          * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2692          * the iommu_table if 32bit DMA is enabled.
2693          */
2694         pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2695         pnv_ioda2_take_ownership(table_group);
2696 }
2697
2698 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2699         .get_table_size = pnv_pci_ioda2_get_table_size,
2700         .create_table = pnv_pci_ioda2_create_table,
2701         .set_window = pnv_pci_ioda2_npu_set_window,
2702         .unset_window = pnv_pci_ioda2_npu_unset_window,
2703         .take_ownership = pnv_ioda2_npu_take_ownership,
2704         .release_ownership = pnv_ioda2_release_ownership,
2705 };
2706
2707 static void pnv_pci_ioda_setup_iommu_api(void)
2708 {
2709         struct pci_controller *hose, *tmp;
2710         struct pnv_phb *phb;
2711         struct pnv_ioda_pe *pe, *gpe;
2712
2713         /*
2714          * Now we have all PHBs discovered, time to add NPU devices to
2715          * the corresponding IOMMU groups.
2716          */
2717         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2718                 phb = hose->private_data;
2719
2720                 if (phb->type != PNV_PHB_NPU)
2721                         continue;
2722
2723                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2724                         gpe = pnv_pci_npu_setup_iommu(pe);
2725                         if (gpe)
2726                                 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2727                 }
2728         }
2729 }
2730 #else /* !CONFIG_IOMMU_API */
2731 static void pnv_pci_ioda_setup_iommu_api(void) { };
2732 #endif
2733
2734 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2735                 unsigned levels, unsigned long limit,
2736                 unsigned long *current_offset, unsigned long *total_allocated)
2737 {
2738         struct page *tce_mem = NULL;
2739         __be64 *addr, *tmp;
2740         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2741         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2742         unsigned entries = 1UL << (shift - 3);
2743         long i;
2744
2745         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2746         if (!tce_mem) {
2747                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2748                 return NULL;
2749         }
2750         addr = page_address(tce_mem);
2751         memset(addr, 0, allocated);
2752         *total_allocated += allocated;
2753
2754         --levels;
2755         if (!levels) {
2756                 *current_offset += allocated;
2757                 return addr;
2758         }
2759
2760         for (i = 0; i < entries; ++i) {
2761                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2762                                 levels, limit, current_offset, total_allocated);
2763                 if (!tmp)
2764                         break;
2765
2766                 addr[i] = cpu_to_be64(__pa(tmp) |
2767                                 TCE_PCI_READ | TCE_PCI_WRITE);
2768
2769                 if (*current_offset >= limit)
2770                         break;
2771         }
2772
2773         return addr;
2774 }
2775
2776 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2777                 unsigned long size, unsigned level);
2778
2779 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2780                 __u32 page_shift, __u64 window_size, __u32 levels,
2781                 struct iommu_table *tbl)
2782 {
2783         void *addr;
2784         unsigned long offset = 0, level_shift, total_allocated = 0;
2785         const unsigned window_shift = ilog2(window_size);
2786         unsigned entries_shift = window_shift - page_shift;
2787         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2788         const unsigned long tce_table_size = 1UL << table_shift;
2789
2790         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2791                 return -EINVAL;
2792
2793         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2794                 return -EINVAL;
2795
2796         /* Adjust direct table size from window_size and levels */
2797         entries_shift = (entries_shift + levels - 1) / levels;
2798         level_shift = entries_shift + 3;
2799         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2800
2801         if ((level_shift - 3) * levels + page_shift >= 55)
2802                 return -EINVAL;
2803
2804         /* Allocate TCE table */
2805         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2806                         levels, tce_table_size, &offset, &total_allocated);
2807
2808         /* addr==NULL means that the first level allocation failed */
2809         if (!addr)
2810                 return -ENOMEM;
2811
2812         /*
2813          * First level was allocated but some lower level failed as
2814          * we did not allocate as much as we wanted,
2815          * release partially allocated table.
2816          */
2817         if (offset < tce_table_size) {
2818                 pnv_pci_ioda2_table_do_free_pages(addr,
2819                                 1ULL << (level_shift - 3), levels - 1);
2820                 return -ENOMEM;
2821         }
2822
2823         /* Setup linux iommu table */
2824         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2825                         page_shift);
2826         tbl->it_level_size = 1ULL << (level_shift - 3);
2827         tbl->it_indirect_levels = levels - 1;
2828         tbl->it_allocated_size = total_allocated;
2829
2830         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2831                         window_size, tce_table_size, bus_offset);
2832
2833         return 0;
2834 }
2835
2836 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2837                 unsigned long size, unsigned level)
2838 {
2839         const unsigned long addr_ul = (unsigned long) addr &
2840                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2841
2842         if (level) {
2843                 long i;
2844                 u64 *tmp = (u64 *) addr_ul;
2845
2846                 for (i = 0; i < size; ++i) {
2847                         unsigned long hpa = be64_to_cpu(tmp[i]);
2848
2849                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2850                                 continue;
2851
2852                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2853                                         level - 1);
2854                 }
2855         }
2856
2857         free_pages(addr_ul, get_order(size << 3));
2858 }
2859
2860 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2861 {
2862         const unsigned long size = tbl->it_indirect_levels ?
2863                         tbl->it_level_size : tbl->it_size;
2864
2865         if (!tbl->it_size)
2866                 return;
2867
2868         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2869                         tbl->it_indirect_levels);
2870 }
2871
2872 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2873                                        struct pnv_ioda_pe *pe)
2874 {
2875         int64_t rc;
2876
2877         if (!pnv_pci_ioda_pe_dma_weight(pe))
2878                 return;
2879
2880         /* TVE #1 is selected by PCI address bit 59 */
2881         pe->tce_bypass_base = 1ull << 59;
2882
2883         iommu_register_group(&pe->table_group, phb->hose->global_number,
2884                         pe->pe_number);
2885
2886         /* The PE will reserve all possible 32-bits space */
2887         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2888                 phb->ioda.m32_pci_base);
2889
2890         /* Setup linux iommu table */
2891         pe->table_group.tce32_start = 0;
2892         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2893         pe->table_group.max_dynamic_windows_supported =
2894                         IOMMU_TABLE_GROUP_MAX_TABLES;
2895         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2896         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2897 #ifdef CONFIG_IOMMU_API
2898         pe->table_group.ops = &pnv_pci_ioda2_ops;
2899 #endif
2900
2901         rc = pnv_pci_ioda2_setup_default_config(pe);
2902         if (rc)
2903                 return;
2904
2905         if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2906                 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2907 }
2908
2909 #ifdef CONFIG_PCI_MSI
2910 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2911 {
2912         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2913                                            ioda.irq_chip);
2914
2915         return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2916 }
2917
2918 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2919 {
2920         int64_t rc;
2921         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2922         struct irq_chip *chip = irq_data_get_irq_chip(d);
2923
2924         rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2925         WARN_ON_ONCE(rc);
2926
2927         icp_native_eoi(d);
2928 }
2929
2930
2931 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2932 {
2933         struct irq_data *idata;
2934         struct irq_chip *ichip;
2935
2936         /* The MSI EOI OPAL call is only needed on PHB3 */
2937         if (phb->model != PNV_PHB_MODEL_PHB3)
2938                 return;
2939
2940         if (!phb->ioda.irq_chip_init) {
2941                 /*
2942                  * First time we setup an MSI IRQ, we need to setup the
2943                  * corresponding IRQ chip to route correctly.
2944                  */
2945                 idata = irq_get_irq_data(virq);
2946                 ichip = irq_data_get_irq_chip(idata);
2947                 phb->ioda.irq_chip_init = 1;
2948                 phb->ioda.irq_chip = *ichip;
2949                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2950         }
2951         irq_set_chip(virq, &phb->ioda.irq_chip);
2952 }
2953
2954 /*
2955  * Returns true iff chip is something that we could call
2956  * pnv_opal_pci_msi_eoi for.
2957  */
2958 bool is_pnv_opal_msi(struct irq_chip *chip)
2959 {
2960         return chip->irq_eoi == pnv_ioda2_msi_eoi;
2961 }
2962 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2963
2964 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2965                                   unsigned int hwirq, unsigned int virq,
2966                                   unsigned int is_64, struct msi_msg *msg)
2967 {
2968         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2969         unsigned int xive_num = hwirq - phb->msi_base;
2970         __be32 data;
2971         int rc;
2972
2973         /* No PE assigned ? bail out ... no MSI for you ! */
2974         if (pe == NULL)
2975                 return -ENXIO;
2976
2977         /* Check if we have an MVE */
2978         if (pe->mve_number < 0)
2979                 return -ENXIO;
2980
2981         /* Force 32-bit MSI on some broken devices */
2982         if (dev->no_64bit_msi)
2983                 is_64 = 0;
2984
2985         /* Assign XIVE to PE */
2986         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2987         if (rc) {
2988                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2989                         pci_name(dev), rc, xive_num);
2990                 return -EIO;
2991         }
2992
2993         if (is_64) {
2994                 __be64 addr64;
2995
2996                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2997                                      &addr64, &data);
2998                 if (rc) {
2999                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
3000                                 pci_name(dev), rc);
3001                         return -EIO;
3002                 }
3003                 msg->address_hi = be64_to_cpu(addr64) >> 32;
3004                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
3005         } else {
3006                 __be32 addr32;
3007
3008                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
3009                                      &addr32, &data);
3010                 if (rc) {
3011                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
3012                                 pci_name(dev), rc);
3013                         return -EIO;
3014                 }
3015                 msg->address_hi = 0;
3016                 msg->address_lo = be32_to_cpu(addr32);
3017         }
3018         msg->data = be32_to_cpu(data);
3019
3020         pnv_set_msi_irq_chip(phb, virq);
3021
3022         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
3023                  " address=%x_%08x data=%x PE# %x\n",
3024                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
3025                  msg->address_hi, msg->address_lo, data, pe->pe_number);
3026
3027         return 0;
3028 }
3029
3030 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
3031 {
3032         unsigned int count;
3033         const __be32 *prop = of_get_property(phb->hose->dn,
3034                                              "ibm,opal-msi-ranges", NULL);
3035         if (!prop) {
3036                 /* BML Fallback */
3037                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
3038         }
3039         if (!prop)
3040                 return;
3041
3042         phb->msi_base = be32_to_cpup(prop);
3043         count = be32_to_cpup(prop + 1);
3044         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
3045                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
3046                        phb->hose->global_number);
3047                 return;
3048         }
3049
3050         phb->msi_setup = pnv_pci_ioda_msi_setup;
3051         phb->msi32_support = 1;
3052         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
3053                 count, phb->msi_base);
3054 }
3055 #else
3056 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
3057 #endif /* CONFIG_PCI_MSI */
3058
3059 #ifdef CONFIG_PCI_IOV
3060 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
3061 {
3062         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3063         struct pnv_phb *phb = hose->private_data;
3064         const resource_size_t gate = phb->ioda.m64_segsize >> 2;
3065         struct resource *res;
3066         int i;
3067         resource_size_t size, total_vf_bar_sz;
3068         struct pci_dn *pdn;
3069         int mul, total_vfs;
3070
3071         if (!pdev->is_physfn || pdev->is_added)
3072                 return;
3073
3074         pdn = pci_get_pdn(pdev);
3075         pdn->vfs_expanded = 0;
3076         pdn->m64_single_mode = false;
3077
3078         total_vfs = pci_sriov_get_totalvfs(pdev);
3079         mul = phb->ioda.total_pe_num;
3080         total_vf_bar_sz = 0;
3081
3082         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3083                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3084                 if (!res->flags || res->parent)
3085                         continue;
3086                 if (!pnv_pci_is_m64_flags(res->flags)) {
3087                         dev_warn(&pdev->dev, "Don't support SR-IOV with"
3088                                         " non M64 VF BAR%d: %pR. \n",
3089                                  i, res);
3090                         goto truncate_iov;
3091                 }
3092
3093                 total_vf_bar_sz += pci_iov_resource_size(pdev,
3094                                 i + PCI_IOV_RESOURCES);
3095
3096                 /*
3097                  * If bigger than quarter of M64 segment size, just round up
3098                  * power of two.
3099                  *
3100                  * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3101                  * with other devices, IOV BAR size is expanded to be
3102                  * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
3103                  * segment size , the expanded size would equal to half of the
3104                  * whole M64 space size, which will exhaust the M64 Space and
3105                  * limit the system flexibility.  This is a design decision to
3106                  * set the boundary to quarter of the M64 segment size.
3107                  */
3108                 if (total_vf_bar_sz > gate) {
3109                         mul = roundup_pow_of_two(total_vfs);
3110                         dev_info(&pdev->dev,
3111                                 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3112                                 total_vf_bar_sz, gate, mul);
3113                         pdn->m64_single_mode = true;
3114                         break;
3115                 }
3116         }
3117
3118         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3119                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3120                 if (!res->flags || res->parent)
3121                         continue;
3122
3123                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3124                 /*
3125                  * On PHB3, the minimum size alignment of M64 BAR in single
3126                  * mode is 32MB.
3127                  */
3128                 if (pdn->m64_single_mode && (size < SZ_32M))
3129                         goto truncate_iov;
3130                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3131                 res->end = res->start + size * mul - 1;
3132                 dev_dbg(&pdev->dev, "                       %pR\n", res);
3133                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3134                          i, res, mul);
3135         }
3136         pdn->vfs_expanded = mul;
3137
3138         return;
3139
3140 truncate_iov:
3141         /* To save MMIO space, IOV BAR is truncated. */
3142         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3143                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3144                 res->flags = 0;
3145                 res->end = res->start - 1;
3146         }
3147 }
3148 #endif /* CONFIG_PCI_IOV */
3149
3150 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3151                                   struct resource *res)
3152 {
3153         struct pnv_phb *phb = pe->phb;
3154         struct pci_bus_region region;
3155         int index;
3156         int64_t rc;
3157
3158         if (!res || !res->flags || res->start > res->end)
3159                 return;
3160
3161         if (res->flags & IORESOURCE_IO) {
3162                 region.start = res->start - phb->ioda.io_pci_base;
3163                 region.end   = res->end - phb->ioda.io_pci_base;
3164                 index = region.start / phb->ioda.io_segsize;
3165
3166                 while (index < phb->ioda.total_pe_num &&
3167                        region.start <= region.end) {
3168                         phb->ioda.io_segmap[index] = pe->pe_number;
3169                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3170                                 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3171                         if (rc != OPAL_SUCCESS) {
3172                                 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3173                                        __func__, rc, index, pe->pe_number);
3174                                 break;
3175                         }
3176
3177                         region.start += phb->ioda.io_segsize;
3178                         index++;
3179                 }
3180         } else if ((res->flags & IORESOURCE_MEM) &&
3181                    !pnv_pci_is_m64(phb, res)) {
3182                 region.start = res->start -
3183                                phb->hose->mem_offset[0] -
3184                                phb->ioda.m32_pci_base;
3185                 region.end   = res->end -
3186                                phb->hose->mem_offset[0] -
3187                                phb->ioda.m32_pci_base;
3188                 index = region.start / phb->ioda.m32_segsize;
3189
3190                 while (index < phb->ioda.total_pe_num &&
3191                        region.start <= region.end) {
3192                         phb->ioda.m32_segmap[index] = pe->pe_number;
3193                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3194                                 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3195                         if (rc != OPAL_SUCCESS) {
3196                                 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3197                                        __func__, rc, index, pe->pe_number);
3198                                 break;
3199                         }
3200
3201                         region.start += phb->ioda.m32_segsize;
3202                         index++;
3203                 }
3204         }
3205 }
3206
3207 /*
3208  * This function is supposed to be called on basis of PE from top
3209  * to bottom style. So the the I/O or MMIO segment assigned to
3210  * parent PE could be overridden by its child PEs if necessary.
3211  */
3212 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3213 {
3214         struct pci_dev *pdev;
3215         int i;
3216
3217         /*
3218          * NOTE: We only care PCI bus based PE for now. For PCI
3219          * device based PE, for example SRIOV sensitive VF should
3220          * be figured out later.
3221          */
3222         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3223
3224         list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3225                 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3226                         pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3227
3228                 /*
3229                  * If the PE contains all subordinate PCI buses, the
3230                  * windows of the child bridges should be mapped to
3231                  * the PE as well.
3232                  */
3233                 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3234                         continue;
3235                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3236                         pnv_ioda_setup_pe_res(pe,
3237                                 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3238         }
3239 }
3240
3241 #ifdef CONFIG_DEBUG_FS
3242 static int pnv_pci_diag_data_set(void *data, u64 val)
3243 {
3244         struct pci_controller *hose;
3245         struct pnv_phb *phb;
3246         s64 ret;
3247
3248         if (val != 1ULL)
3249                 return -EINVAL;
3250
3251         hose = (struct pci_controller *)data;
3252         if (!hose || !hose->private_data)
3253                 return -ENODEV;
3254
3255         phb = hose->private_data;
3256
3257         /* Retrieve the diag data from firmware */
3258         ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3259                                           phb->diag_data_size);
3260         if (ret != OPAL_SUCCESS)
3261                 return -EIO;
3262
3263         /* Print the diag data to the kernel log */
3264         pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3265         return 0;
3266 }
3267
3268 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3269                         pnv_pci_diag_data_set, "%llu\n");
3270
3271 #endif /* CONFIG_DEBUG_FS */
3272
3273 static void pnv_pci_ioda_create_dbgfs(void)
3274 {
3275 #ifdef CONFIG_DEBUG_FS
3276         struct pci_controller *hose, *tmp;
3277         struct pnv_phb *phb;
3278         char name[16];
3279
3280         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3281                 phb = hose->private_data;
3282
3283                 /* Notify initialization of PHB done */
3284                 phb->initialized = 1;
3285
3286                 sprintf(name, "PCI%04x", hose->global_number);
3287                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3288                 if (!phb->dbgfs) {
3289                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3290                                 __func__, hose->global_number);
3291                         continue;
3292                 }
3293
3294                 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3295                                     &pnv_pci_diag_data_fops);
3296         }
3297 #endif /* CONFIG_DEBUG_FS */
3298 }
3299
3300 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3301 {
3302         struct pci_dev *dev = bus->self;
3303         struct pci_bus *child;
3304
3305         /* Empty bus ? bail */
3306         if (list_empty(&bus->devices))
3307                 return;
3308
3309         /*
3310          * If there's a bridge associated with that bus enable it. This works
3311          * around races in the generic code if the enabling is done during
3312          * parallel probing. This can be removed once those races have been
3313          * fixed.
3314          */
3315         if (dev) {
3316                 int rc = pci_enable_device(dev);
3317                 if (rc)
3318                         pci_err(dev, "Error enabling bridge (%d)\n", rc);
3319                 pci_set_master(dev);
3320         }
3321
3322         /* Perform the same to child busses */
3323         list_for_each_entry(child, &bus->children, node)
3324                 pnv_pci_enable_bridge(child);
3325 }
3326
3327 static void pnv_pci_enable_bridges(void)
3328 {
3329         struct pci_controller *hose;
3330
3331         list_for_each_entry(hose, &hose_list, list_node)
3332                 pnv_pci_enable_bridge(hose->bus);
3333 }
3334
3335 static void pnv_pci_ioda_fixup(void)
3336 {
3337         pnv_pci_ioda_setup_PEs();
3338         pnv_pci_ioda_setup_iommu_api();
3339         pnv_pci_ioda_create_dbgfs();
3340
3341         pnv_pci_enable_bridges();
3342
3343 #ifdef CONFIG_EEH
3344         eeh_init();
3345         eeh_addr_cache_build();
3346 #endif
3347 }
3348
3349 /*
3350  * Returns the alignment for I/O or memory windows for P2P
3351  * bridges. That actually depends on how PEs are segmented.
3352  * For now, we return I/O or M32 segment size for PE sensitive
3353  * P2P bridges. Otherwise, the default values (4KiB for I/O,
3354  * 1MiB for memory) will be returned.
3355  *
3356  * The current PCI bus might be put into one PE, which was
3357  * create against the parent PCI bridge. For that case, we
3358  * needn't enlarge the alignment so that we can save some
3359  * resources.
3360  */
3361 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3362                                                 unsigned long type)
3363 {
3364         struct pci_dev *bridge;
3365         struct pci_controller *hose = pci_bus_to_host(bus);
3366         struct pnv_phb *phb = hose->private_data;
3367         int num_pci_bridges = 0;
3368
3369         bridge = bus->self;
3370         while (bridge) {
3371                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3372                         num_pci_bridges++;
3373                         if (num_pci_bridges >= 2)
3374                                 return 1;
3375                 }
3376
3377                 bridge = bridge->bus->self;
3378         }
3379
3380         /*
3381          * We fall back to M32 if M64 isn't supported. We enforce the M64
3382          * alignment for any 64-bit resource, PCIe doesn't care and
3383          * bridges only do 64-bit prefetchable anyway.
3384          */
3385         if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3386                 return phb->ioda.m64_segsize;
3387         if (type & IORESOURCE_MEM)
3388                 return phb->ioda.m32_segsize;
3389
3390         return phb->ioda.io_segsize;
3391 }
3392
3393 /*
3394  * We are updating root port or the upstream port of the
3395  * bridge behind the root port with PHB's windows in order
3396  * to accommodate the changes on required resources during
3397  * PCI (slot) hotplug, which is connected to either root
3398  * port or the downstream ports of PCIe switch behind the
3399  * root port.
3400  */
3401 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3402                                            unsigned long type)
3403 {
3404         struct pci_controller *hose = pci_bus_to_host(bus);
3405         struct pnv_phb *phb = hose->private_data;
3406         struct pci_dev *bridge = bus->self;
3407         struct resource *r, *w;
3408         bool msi_region = false;
3409         int i;
3410
3411         /* Check if we need apply fixup to the bridge's windows */
3412         if (!pci_is_root_bus(bridge->bus) &&
3413             !pci_is_root_bus(bridge->bus->self->bus))
3414                 return;
3415
3416         /* Fixup the resources */
3417         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3418                 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3419                 if (!r->flags || !r->parent)
3420                         continue;
3421
3422                 w = NULL;
3423                 if (r->flags & type & IORESOURCE_IO)
3424                         w = &hose->io_resource;
3425                 else if (pnv_pci_is_m64(phb, r) &&
3426                          (type & IORESOURCE_PREFETCH) &&
3427                          phb->ioda.m64_segsize)
3428                         w = &hose->mem_resources[1];
3429                 else if (r->flags & type & IORESOURCE_MEM) {
3430                         w = &hose->mem_resources[0];
3431                         msi_region = true;
3432                 }
3433
3434                 r->start = w->start;
3435                 r->end = w->end;
3436
3437                 /* The 64KB 32-bits MSI region shouldn't be included in
3438                  * the 32-bits bridge window. Otherwise, we can see strange
3439                  * issues. One of them is EEH error observed on Garrison.
3440                  *
3441                  * Exclude top 1MB region which is the minimal alignment of
3442                  * 32-bits bridge window.
3443                  */
3444                 if (msi_region) {
3445                         r->end += 0x10000;
3446                         r->end -= 0x100000;
3447                 }
3448         }
3449 }
3450
3451 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3452 {
3453         struct pci_controller *hose = pci_bus_to_host(bus);
3454         struct pnv_phb *phb = hose->private_data;
3455         struct pci_dev *bridge = bus->self;
3456         struct pnv_ioda_pe *pe;
3457         bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3458
3459         /* Extend bridge's windows if necessary */
3460         pnv_pci_fixup_bridge_resources(bus, type);
3461
3462         /* The PE for root bus should be realized before any one else */
3463         if (!phb->ioda.root_pe_populated) {
3464                 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3465                 if (pe) {
3466                         phb->ioda.root_pe_idx = pe->pe_number;
3467                         phb->ioda.root_pe_populated = true;
3468                 }
3469         }
3470
3471         /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3472         if (list_empty(&bus->devices))
3473                 return;
3474
3475         /* Reserve PEs according to used M64 resources */
3476         if (phb->reserve_m64_pe)
3477                 phb->reserve_m64_pe(bus, NULL, all);
3478
3479         /*
3480          * Assign PE. We might run here because of partial hotplug.
3481          * For the case, we just pick up the existing PE and should
3482          * not allocate resources again.
3483          */
3484         pe = pnv_ioda_setup_bus_PE(bus, all);
3485         if (!pe)
3486                 return;
3487
3488         pnv_ioda_setup_pe_seg(pe);
3489         switch (phb->type) {
3490         case PNV_PHB_IODA1:
3491                 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3492                 break;
3493         case PNV_PHB_IODA2:
3494                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3495                 break;
3496         default:
3497                 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3498                         __func__, phb->hose->global_number, phb->type);
3499         }
3500 }
3501
3502 static resource_size_t pnv_pci_default_alignment(void)
3503 {
3504         return PAGE_SIZE;
3505 }
3506
3507 #ifdef CONFIG_PCI_IOV
3508 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3509                                                       int resno)
3510 {
3511         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3512         struct pnv_phb *phb = hose->private_data;
3513         struct pci_dn *pdn = pci_get_pdn(pdev);
3514         resource_size_t align;
3515
3516         /*
3517          * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3518          * SR-IOV. While from hardware perspective, the range mapped by M64
3519          * BAR should be size aligned.
3520          *
3521          * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3522          * powernv-specific hardware restriction is gone. But if just use the
3523          * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3524          * in one segment of M64 #15, which introduces the PE conflict between
3525          * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3526          * m64_segsize.
3527          *
3528          * This function returns the total IOV BAR size if M64 BAR is in
3529          * Shared PE mode or just VF BAR size if not.
3530          * If the M64 BAR is in Single PE mode, return the VF BAR size or
3531          * M64 segment size if IOV BAR size is less.
3532          */
3533         align = pci_iov_resource_size(pdev, resno);
3534         if (!pdn->vfs_expanded)
3535                 return align;
3536         if (pdn->m64_single_mode)
3537                 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3538
3539         return pdn->vfs_expanded * align;
3540 }
3541 #endif /* CONFIG_PCI_IOV */
3542
3543 /* Prevent enabling devices for which we couldn't properly
3544  * assign a PE
3545  */
3546 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3547 {
3548         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3549         struct pnv_phb *phb = hose->private_data;
3550         struct pci_dn *pdn;
3551
3552         /* The function is probably called while the PEs have
3553          * not be created yet. For example, resource reassignment
3554          * during PCI probe period. We just skip the check if
3555          * PEs isn't ready.
3556          */
3557         if (!phb->initialized)
3558                 return true;
3559
3560         pdn = pci_get_pdn(dev);
3561         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3562                 return false;
3563
3564         return true;
3565 }
3566
3567 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3568                                        int num)
3569 {
3570         struct pnv_ioda_pe *pe = container_of(table_group,
3571                                               struct pnv_ioda_pe, table_group);
3572         struct pnv_phb *phb = pe->phb;
3573         unsigned int idx;
3574         long rc;
3575
3576         pe_info(pe, "Removing DMA window #%d\n", num);
3577         for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3578                 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3579                         continue;
3580
3581                 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3582                                                 idx, 0, 0ul, 0ul, 0ul);
3583                 if (rc != OPAL_SUCCESS) {
3584                         pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3585                                 rc, idx);
3586                         return rc;
3587                 }
3588
3589                 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3590         }
3591
3592         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3593         return OPAL_SUCCESS;
3594 }
3595
3596 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3597 {
3598         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3599         struct iommu_table *tbl = pe->table_group.tables[0];
3600         int64_t rc;
3601
3602         if (!weight)
3603                 return;
3604
3605         rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3606         if (rc != OPAL_SUCCESS)
3607                 return;
3608
3609         pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3610         if (pe->table_group.group) {
3611                 iommu_group_put(pe->table_group.group);
3612                 WARN_ON(pe->table_group.group);
3613         }
3614
3615         free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3616         iommu_tce_table_put(tbl);
3617 }
3618
3619 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3620 {
3621         struct iommu_table *tbl = pe->table_group.tables[0];
3622         unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3623 #ifdef CONFIG_IOMMU_API
3624         int64_t rc;
3625 #endif
3626
3627         if (!weight)
3628                 return;
3629
3630 #ifdef CONFIG_IOMMU_API
3631         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3632         if (rc)
3633                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3634 #endif
3635
3636         pnv_pci_ioda2_set_bypass(pe, false);
3637         if (pe->table_group.group) {
3638                 iommu_group_put(pe->table_group.group);
3639                 WARN_ON(pe->table_group.group);
3640         }
3641
3642         iommu_tce_table_put(tbl);
3643 }
3644
3645 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3646                                  unsigned short win,
3647                                  unsigned int *map)
3648 {
3649         struct pnv_phb *phb = pe->phb;
3650         int idx;
3651         int64_t rc;
3652
3653         for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3654                 if (map[idx] != pe->pe_number)
3655                         continue;
3656
3657                 if (win == OPAL_M64_WINDOW_TYPE)
3658                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3659                                         phb->ioda.reserved_pe_idx, win,
3660                                         idx / PNV_IODA1_M64_SEGS,
3661                                         idx % PNV_IODA1_M64_SEGS);
3662                 else
3663                         rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3664                                         phb->ioda.reserved_pe_idx, win, 0, idx);
3665
3666                 if (rc != OPAL_SUCCESS)
3667                         pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3668                                 rc, win, idx);
3669
3670                 map[idx] = IODA_INVALID_PE;
3671         }
3672 }
3673
3674 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3675 {
3676         struct pnv_phb *phb = pe->phb;
3677
3678         if (phb->type == PNV_PHB_IODA1) {
3679                 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3680                                      phb->ioda.io_segmap);
3681                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3682                                      phb->ioda.m32_segmap);
3683                 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3684                                      phb->ioda.m64_segmap);
3685         } else if (phb->type == PNV_PHB_IODA2) {
3686                 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3687                                      phb->ioda.m32_segmap);
3688         }
3689 }
3690
3691 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3692 {
3693         struct pnv_phb *phb = pe->phb;
3694         struct pnv_ioda_pe *slave, *tmp;
3695
3696         list_del(&pe->list);
3697         switch (phb->type) {
3698         case PNV_PHB_IODA1:
3699                 pnv_pci_ioda1_release_pe_dma(pe);
3700                 break;
3701         case PNV_PHB_IODA2:
3702                 pnv_pci_ioda2_release_pe_dma(pe);
3703                 break;
3704         default:
3705                 WARN_ON(1);
3706         }
3707
3708         pnv_ioda_release_pe_seg(pe);
3709         pnv_ioda_deconfigure_pe(pe->phb, pe);
3710
3711         /* Release slave PEs in the compound PE */
3712         if (pe->flags & PNV_IODA_PE_MASTER) {
3713                 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3714                         list_del(&slave->list);
3715                         pnv_ioda_free_pe(slave);
3716                 }
3717         }
3718
3719         /*
3720          * The PE for root bus can be removed because of hotplug in EEH
3721          * recovery for fenced PHB error. We need to mark the PE dead so
3722          * that it can be populated again in PCI hot add path. The PE
3723          * shouldn't be destroyed as it's the global reserved resource.
3724          */
3725         if (phb->ioda.root_pe_populated &&
3726             phb->ioda.root_pe_idx == pe->pe_number)
3727                 phb->ioda.root_pe_populated = false;
3728         else
3729                 pnv_ioda_free_pe(pe);
3730 }
3731
3732 static void pnv_pci_release_device(struct pci_dev *pdev)
3733 {
3734         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3735         struct pnv_phb *phb = hose->private_data;
3736         struct pci_dn *pdn = pci_get_pdn(pdev);
3737         struct pnv_ioda_pe *pe;
3738
3739         if (pdev->is_virtfn)
3740                 return;
3741
3742         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3743                 return;
3744
3745         /*
3746          * PCI hotplug can happen as part of EEH error recovery. The @pdn
3747          * isn't removed and added afterwards in this scenario. We should
3748          * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3749          * device count is decreased on removing devices while failing to
3750          * be increased on adding devices. It leads to unbalanced PE's device
3751          * count and eventually make normal PCI hotplug path broken.
3752          */
3753         pe = &phb->ioda.pe_array[pdn->pe_number];
3754         pdn->pe_number = IODA_INVALID_PE;
3755
3756         WARN_ON(--pe->device_count < 0);
3757         if (pe->device_count == 0)
3758                 pnv_ioda_release_pe(pe);
3759 }
3760
3761 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3762 {
3763         struct pnv_phb *phb = hose->private_data;
3764
3765         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3766                        OPAL_ASSERT_RESET);
3767 }
3768
3769 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3770         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3771         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3772 #ifdef CONFIG_PCI_MSI
3773         .setup_msi_irqs         = pnv_setup_msi_irqs,
3774         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3775 #endif
3776         .enable_device_hook     = pnv_pci_enable_device_hook,
3777         .release_device         = pnv_pci_release_device,
3778         .window_alignment       = pnv_pci_window_alignment,
3779         .setup_bridge           = pnv_pci_setup_bridge,
3780         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3781         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3782         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3783         .shutdown               = pnv_pci_ioda_shutdown,
3784 };
3785
3786 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3787 {
3788         dev_err_once(&npdev->dev,
3789                         "%s operation unsupported for NVLink devices\n",
3790                         __func__);
3791         return -EPERM;
3792 }
3793
3794 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3795         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3796 #ifdef CONFIG_PCI_MSI
3797         .setup_msi_irqs         = pnv_setup_msi_irqs,
3798         .teardown_msi_irqs      = pnv_teardown_msi_irqs,
3799 #endif
3800         .enable_device_hook     = pnv_pci_enable_device_hook,
3801         .window_alignment       = pnv_pci_window_alignment,
3802         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3803         .dma_set_mask           = pnv_npu_dma_set_mask,
3804         .shutdown               = pnv_pci_ioda_shutdown,
3805 };
3806
3807 #ifdef CONFIG_CXL_BASE
3808 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3809         .dma_dev_setup          = pnv_pci_dma_dev_setup,
3810         .dma_bus_setup          = pnv_pci_dma_bus_setup,
3811 #ifdef CONFIG_PCI_MSI
3812         .setup_msi_irqs         = pnv_cxl_cx4_setup_msi_irqs,
3813         .teardown_msi_irqs      = pnv_cxl_cx4_teardown_msi_irqs,
3814 #endif
3815         .enable_device_hook     = pnv_cxl_enable_device_hook,
3816         .disable_device         = pnv_cxl_disable_device,
3817         .release_device         = pnv_pci_release_device,
3818         .window_alignment       = pnv_pci_window_alignment,
3819         .setup_bridge           = pnv_pci_setup_bridge,
3820         .reset_secondary_bus    = pnv_pci_reset_secondary_bus,
3821         .dma_set_mask           = pnv_pci_ioda_dma_set_mask,
3822         .dma_get_required_mask  = pnv_pci_ioda_dma_get_required_mask,
3823         .shutdown               = pnv_pci_ioda_shutdown,
3824 };
3825 #endif
3826
3827 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3828                                          u64 hub_id, int ioda_type)
3829 {
3830         struct pci_controller *hose;
3831         struct pnv_phb *phb;
3832         unsigned long size, m64map_off, m32map_off, pemap_off;
3833         unsigned long iomap_off = 0, dma32map_off = 0;
3834         struct resource r;
3835         const __be64 *prop64;
3836         const __be32 *prop32;
3837         int len;
3838         unsigned int segno;
3839         u64 phb_id;
3840         void *aux;
3841         long rc;
3842
3843         if (!of_device_is_available(np))
3844                 return;
3845
3846         pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3847
3848         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3849         if (!prop64) {
3850                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3851                 return;
3852         }
3853         phb_id = be64_to_cpup(prop64);
3854         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3855
3856         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3857
3858         /* Allocate PCI controller */
3859         phb->hose = hose = pcibios_alloc_controller(np);
3860         if (!phb->hose) {
3861                 pr_err("  Can't allocate PCI controller for %pOF\n",
3862                        np);
3863                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3864                 return;
3865         }
3866
3867         spin_lock_init(&phb->lock);
3868         prop32 = of_get_property(np, "bus-range", &len);
3869         if (prop32 && len == 8) {
3870                 hose->first_busno = be32_to_cpu(prop32[0]);
3871                 hose->last_busno = be32_to_cpu(prop32[1]);
3872         } else {
3873                 pr_warn("  Broken <bus-range> on %pOF\n", np);
3874                 hose->first_busno = 0;
3875                 hose->last_busno = 0xff;
3876         }
3877         hose->private_data = phb;
3878         phb->hub_id = hub_id;
3879         phb->opal_id = phb_id;
3880         phb->type = ioda_type;
3881         mutex_init(&phb->ioda.pe_alloc_mutex);
3882
3883         /* Detect specific models for error handling */
3884         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3885                 phb->model = PNV_PHB_MODEL_P7IOC;
3886         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3887                 phb->model = PNV_PHB_MODEL_PHB3;
3888         else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3889                 phb->model = PNV_PHB_MODEL_NPU;
3890         else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3891                 phb->model = PNV_PHB_MODEL_NPU2;
3892         else
3893                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3894
3895         /* Initialize diagnostic data buffer */
3896         prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3897         if (prop32)
3898                 phb->diag_data_size = be32_to_cpup(prop32);
3899         else
3900                 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3901
3902         phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0);
3903
3904         /* Parse 32-bit and IO ranges (if any) */
3905         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3906
3907         /* Get registers */
3908         if (!of_address_to_resource(np, 0, &r)) {
3909                 phb->regs_phys = r.start;
3910                 phb->regs = ioremap(r.start, resource_size(&r));
3911                 if (phb->regs == NULL)
3912                         pr_err("  Failed to map registers !\n");
3913         }
3914
3915         /* Initialize more IODA stuff */
3916         phb->ioda.total_pe_num = 1;
3917         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3918         if (prop32)
3919                 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3920         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3921         if (prop32)
3922                 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3923
3924         /* Invalidate RID to PE# mapping */
3925         for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3926                 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3927
3928         /* Parse 64-bit MMIO range */
3929         pnv_ioda_parse_m64_window(phb);
3930
3931         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3932         /* FW Has already off top 64k of M32 space (MSI space) */
3933         phb->ioda.m32_size += 0x10000;
3934
3935         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3936         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3937         phb->ioda.io_size = hose->pci_io_size;
3938         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3939         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3940
3941         /* Calculate how many 32-bit TCE segments we have */
3942         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3943                                 PNV_IODA1_DMA32_SEGSIZE;
3944
3945         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3946         size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3947                         sizeof(unsigned long));
3948         m64map_off = size;
3949         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3950         m32map_off = size;
3951         size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3952         if (phb->type == PNV_PHB_IODA1) {
3953                 iomap_off = size;
3954                 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3955                 dma32map_off = size;
3956                 size += phb->ioda.dma32_count *
3957                         sizeof(phb->ioda.dma32_segmap[0]);
3958         }
3959         pemap_off = size;
3960         size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3961         aux = memblock_virt_alloc(size, 0);
3962         phb->ioda.pe_alloc = aux;
3963         phb->ioda.m64_segmap = aux + m64map_off;
3964         phb->ioda.m32_segmap = aux + m32map_off;
3965         for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3966                 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3967                 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3968         }
3969         if (phb->type == PNV_PHB_IODA1) {
3970                 phb->ioda.io_segmap = aux + iomap_off;
3971                 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3972                         phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3973
3974                 phb->ioda.dma32_segmap = aux + dma32map_off;
3975                 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3976                         phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3977         }
3978         phb->ioda.pe_array = aux + pemap_off;
3979
3980         /*
3981          * Choose PE number for root bus, which shouldn't have
3982          * M64 resources consumed by its child devices. To pick
3983          * the PE number adjacent to the reserved one if possible.
3984          */
3985         pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3986         if (phb->ioda.reserved_pe_idx == 0) {
3987                 phb->ioda.root_pe_idx = 1;
3988                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3989         } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3990                 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3991                 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3992         } else {
3993                 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3994         }
3995
3996         INIT_LIST_HEAD(&phb->ioda.pe_list);
3997         mutex_init(&phb->ioda.pe_list_mutex);
3998
3999         /* Calculate how many 32-bit TCE segments we have */
4000         phb->ioda.dma32_count = phb->ioda.m32_pci_base /
4001                                 PNV_IODA1_DMA32_SEGSIZE;
4002
4003 #if 0 /* We should really do that ... */
4004         rc = opal_pci_set_phb_mem_window(opal->phb_id,
4005                                          window_type,
4006                                          window_num,
4007                                          starting_real_address,
4008                                          starting_pci_address,
4009                                          segment_size);
4010 #endif
4011
4012         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
4013                 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
4014                 phb->ioda.m32_size, phb->ioda.m32_segsize);
4015         if (phb->ioda.m64_size)
4016                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
4017                         phb->ioda.m64_size, phb->ioda.m64_segsize);
4018         if (phb->ioda.io_size)
4019                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
4020                         phb->ioda.io_size, phb->ioda.io_segsize);
4021
4022
4023         phb->hose->ops = &pnv_pci_ops;
4024         phb->get_pe_state = pnv_ioda_get_pe_state;
4025         phb->freeze_pe = pnv_ioda_freeze_pe;
4026         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
4027
4028         /* Setup MSI support */
4029         pnv_pci_init_ioda_msis(phb);
4030
4031         /*
4032          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
4033          * to let the PCI core do resource assignment. It's supposed
4034          * that the PCI core will do correct I/O and MMIO alignment
4035          * for the P2P bridge bars so that each PCI bus (excluding
4036          * the child P2P bridges) can form individual PE.
4037          */
4038         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
4039
4040         if (phb->type == PNV_PHB_NPU) {
4041                 hose->controller_ops = pnv_npu_ioda_controller_ops;
4042         } else {
4043                 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
4044                 hose->controller_ops = pnv_pci_ioda_controller_ops;
4045         }
4046
4047         ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
4048
4049 #ifdef CONFIG_PCI_IOV
4050         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
4051         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
4052 #endif
4053
4054         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
4055
4056         /* Reset IODA tables to a clean state */
4057         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
4058         if (rc)
4059                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
4060
4061         /*
4062          * If we're running in kdump kernel, the previous kernel never
4063          * shutdown PCI devices correctly. We already got IODA table
4064          * cleaned out. So we have to issue PHB reset to stop all PCI
4065          * transactions from previous kernel.
4066          */
4067         if (is_kdump_kernel()) {
4068                 pr_info("  Issue PHB reset ...\n");
4069                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
4070                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
4071         }
4072
4073         /* Remove M64 resource if we can't configure it successfully */
4074         if (!phb->init_m64 || phb->init_m64(phb))
4075                 hose->mem_resources[1].flags = 0;
4076 }
4077
4078 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4079 {
4080         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4081 }
4082
4083 void __init pnv_pci_init_npu_phb(struct device_node *np)
4084 {
4085         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
4086 }
4087
4088 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4089 {
4090         struct device_node *phbn;
4091         const __be64 *prop64;
4092         u64 hub_id;
4093
4094         pr_info("Probing IODA IO-Hub %pOF\n", np);
4095
4096         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4097         if (!prop64) {
4098                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4099                 return;
4100         }
4101         hub_id = be64_to_cpup(prop64);
4102         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4103
4104         /* Count child PHBs */
4105         for_each_child_of_node(np, phbn) {
4106                 /* Look for IODA1 PHBs */
4107                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4108                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4109         }
4110 }