2 * Copyright 2014-2016 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/module.h>
11 #include <asm/pnv-pci.h>
16 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
18 struct pci_controller *hose = pci_bus_to_host(dev->bus);
19 struct pnv_phb *phb = hose->private_data;
20 struct pnv_ioda_pe *pe;
23 pe = pnv_ioda_get_pe(dev);
27 pe_info(pe, "Switching PHB to CXL\n");
29 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
30 if (rc == OPAL_UNSUPPORTED)
31 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
33 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
37 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
39 /* Find PHB for cxl dev and allocate MSI hwirqs?
40 * Returns the absolute hardware IRQ number
42 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
44 struct pci_controller *hose = pci_bus_to_host(dev->bus);
45 struct pnv_phb *phb = hose->private_data;
46 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
49 dev_warn(&dev->dev, "Failed to find a free MSI\n");
53 return phb->msi_base + hwirq;
55 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
57 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
59 struct pci_controller *hose = pci_bus_to_host(dev->bus);
60 struct pnv_phb *phb = hose->private_data;
62 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
64 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
66 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
69 struct pci_controller *hose = pci_bus_to_host(dev->bus);
70 struct pnv_phb *phb = hose->private_data;
73 for (i = 1; i < CXL_IRQ_RANGES; i++) {
76 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
79 hwirq = irqs->offset[i] - phb->msi_base;
80 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
84 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
86 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
87 struct pci_dev *dev, int num)
89 struct pci_controller *hose = pci_bus_to_host(dev->bus);
90 struct pnv_phb *phb = hose->private_data;
93 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
95 /* 0 is reserved for the multiplexed PSL DSI interrupt */
96 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
99 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
107 irqs->offset[i] = phb->msi_base + hwirq;
108 irqs->range[i] = try;
109 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
110 i, irqs->offset[i], irqs->range[i]);
118 pnv_cxl_release_hwirq_ranges(irqs, dev);
121 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
123 int pnv_cxl_get_irq_count(struct pci_dev *dev)
125 struct pci_controller *hose = pci_bus_to_host(dev->bus);
126 struct pnv_phb *phb = hose->private_data;
128 return phb->msi_bmp.irq_count;
130 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
132 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
135 struct pci_controller *hose = pci_bus_to_host(dev->bus);
136 struct pnv_phb *phb = hose->private_data;
137 unsigned int xive_num = hwirq - phb->msi_base;
138 struct pnv_ioda_pe *pe;
141 if (!(pe = pnv_ioda_get_pe(dev)))
144 /* Assign XIVE to PE */
145 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
147 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
148 "hwirq 0x%x XIVE 0x%x PE\n",
149 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
152 pnv_set_msi_irq_chip(phb, virq);
156 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
158 #if IS_MODULE(CONFIG_CXL)
159 static inline int get_cxl_module(void)
161 struct module *cxl_module;
163 mutex_lock(&module_mutex);
165 cxl_module = find_module("cxl");
167 __module_get(cxl_module);
169 mutex_unlock(&module_mutex);
177 static inline int get_cxl_module(void) { return 0; }