2 * The file intends to implement the platform dependent EEH operations on
3 * powernv platform. Actually, the powernv was created in order to fully
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/atomic.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/list.h>
21 #include <linux/msi.h>
23 #include <linux/pci.h>
24 #include <linux/proc_fs.h>
25 #include <linux/rbtree.h>
26 #include <linux/sched.h>
27 #include <linux/seq_file.h>
28 #include <linux/spinlock.h>
31 #include <asm/eeh_event.h>
32 #include <asm/firmware.h>
34 #include <asm/iommu.h>
35 #include <asm/machdep.h>
36 #include <asm/msi_bitmap.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/pnv-pci.h>
44 static int eeh_event_irq = -EINVAL;
46 void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
48 struct pci_dn *pdn = pci_get_pdn(pdev);
54 * The following operations will fail if VF's sysfs files
55 * aren't created or its resources aren't finalized.
57 eeh_add_device_early(pdn);
58 eeh_add_device_late(pdev);
59 eeh_sysfs_add_device(pdev);
62 static int pnv_eeh_init(void)
64 struct pci_controller *hose;
66 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE;
68 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
69 pr_warn("%s: OPAL is required !\n",
75 eeh_add_flag(EEH_PROBE_MODE_DEV);
78 * P7IOC blocks PCI config access to frozen PE, but PHB3
79 * doesn't do that. So we have to selectively enable I/O
80 * prior to collecting error log.
82 list_for_each_entry(hose, &hose_list, list_node) {
83 phb = hose->private_data;
85 if (phb->model == PNV_PHB_MODEL_P7IOC)
86 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
88 if (phb->diag_data_size > max_diag_size)
89 max_diag_size = phb->diag_data_size;
92 * PE#0 should be regarded as valid by EEH core
93 * if it's not the reserved one. Currently, we
94 * have the reserved PE#255 and PE#127 for PHB3
95 * and P7IOC separately. So we should regard
96 * PE#0 as valid for PHB3 and P7IOC.
98 if (phb->ioda.reserved_pe_idx != 0)
99 eeh_add_flag(EEH_VALID_PE_ZERO);
104 eeh_set_pe_aux_size(max_diag_size);
105 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device;
110 static irqreturn_t pnv_eeh_event(int irq, void *data)
113 * We simply send a special EEH event if EEH has been
114 * enabled. We don't care about EEH events until we've
115 * finished processing the outstanding ones. Event processing
116 * gets unmasked in next_error() if EEH is enabled.
118 disable_irq_nosync(irq);
121 eeh_send_failure_event(NULL);
126 #ifdef CONFIG_DEBUG_FS
127 static ssize_t pnv_eeh_ei_write(struct file *filp,
128 const char __user *user_buf,
129 size_t count, loff_t *ppos)
131 struct pci_controller *hose = filp->private_data;
133 int pe_no, type, func;
134 unsigned long addr, mask;
138 if (!eeh_ops || !eeh_ops->err_inject)
141 /* Copy over argument buffer */
142 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
146 /* Retrieve parameters */
147 ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
148 &pe_no, &type, &func, &addr, &mask);
153 pe = eeh_pe_get(hose, pe_no, 0);
157 /* Do error injection */
158 ret = eeh_ops->err_inject(pe, type, func, addr, mask);
159 return ret < 0 ? ret : count;
162 static const struct file_operations pnv_eeh_ei_fops = {
165 .write = pnv_eeh_ei_write,
168 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
170 struct pci_controller *hose = data;
171 struct pnv_phb *phb = hose->private_data;
173 out_be64(phb->regs + offset, val);
177 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
179 struct pci_controller *hose = data;
180 struct pnv_phb *phb = hose->private_data;
182 *val = in_be64(phb->regs + offset);
186 #define PNV_EEH_DBGFS_ENTRY(name, reg) \
187 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \
189 return pnv_eeh_dbgfs_set(data, reg, val); \
192 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \
194 return pnv_eeh_dbgfs_get(data, reg, val); \
197 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \
198 pnv_eeh_dbgfs_get_##name, \
199 pnv_eeh_dbgfs_set_##name, \
202 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
203 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
204 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
206 #endif /* CONFIG_DEBUG_FS */
209 * pnv_eeh_post_init - EEH platform dependent post initialization
211 * EEH platform dependent post initialization on powernv. When
212 * the function is called, the EEH PEs and devices should have
213 * been built. If the I/O cache staff has been built, EEH is
214 * ready to supply service.
216 int pnv_eeh_post_init(void)
218 struct pci_controller *hose;
222 /* Probe devices & build address cache */
224 eeh_addr_cache_build();
226 if (eeh_has_flag(EEH_POSTPONED_PROBE)) {
227 eeh_clear_flag(EEH_POSTPONED_PROBE);
229 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
231 pr_info("EEH: No capable adapters found\n");
234 /* Register OPAL event notifier */
235 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
236 if (eeh_event_irq < 0) {
237 pr_err("%s: Can't register OPAL event interrupt (%d)\n",
238 __func__, eeh_event_irq);
239 return eeh_event_irq;
242 ret = request_irq(eeh_event_irq, pnv_eeh_event,
243 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
245 irq_dispose_mapping(eeh_event_irq);
246 pr_err("%s: Can't request OPAL event interrupt (%d)\n",
247 __func__, eeh_event_irq);
252 disable_irq(eeh_event_irq);
254 list_for_each_entry(hose, &hose_list, list_node) {
255 phb = hose->private_data;
258 * If EEH is enabled, we're going to rely on that.
259 * Otherwise, we restore to conventional mechanism
260 * to clear frozen PE during PCI config access.
263 phb->flags |= PNV_PHB_FLAG_EEH;
265 phb->flags &= ~PNV_PHB_FLAG_EEH;
267 /* Create debugfs entries */
268 #ifdef CONFIG_DEBUG_FS
269 if (phb->has_dbgfs || !phb->dbgfs)
273 debugfs_create_file("err_injct", 0200,
277 debugfs_create_file("err_injct_outbound", 0600,
279 &pnv_eeh_dbgfs_ops_outb);
280 debugfs_create_file("err_injct_inboundA", 0600,
282 &pnv_eeh_dbgfs_ops_inbA);
283 debugfs_create_file("err_injct_inboundB", 0600,
285 &pnv_eeh_dbgfs_ops_inbB);
286 #endif /* CONFIG_DEBUG_FS */
292 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
294 int pos = PCI_CAPABILITY_LIST;
295 int cnt = 48; /* Maximal number of capabilities */
301 /* Check if the device supports capabilities */
302 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
303 if (!(status & PCI_STATUS_CAP_LIST))
307 pnv_pci_cfg_read(pdn, pos, 1, &pos);
312 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
321 pos += PCI_CAP_LIST_NEXT;
327 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
329 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
331 int pos = 256, ttl = (4096 - 256) / 8;
333 if (!edev || !edev->pcie_cap)
335 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
341 if (PCI_EXT_CAP_ID(header) == cap && pos)
344 pos = PCI_EXT_CAP_NEXT(header);
348 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
356 * pnv_eeh_probe - Do probe on PCI device
357 * @pdn: PCI device node
360 * When EEH module is installed during system boot, all PCI devices
361 * are checked one by one to see if it supports EEH. The function
362 * is introduced for the purpose. By default, EEH has been enabled
363 * on all PCI devices. That's to say, we only need do necessary
364 * initialization on the corresponding eeh device and create PE
367 * It's notable that's unsafe to retrieve the EEH device through
368 * the corresponding PCI device. During the PCI device hotplug, which
369 * was possiblly triggered by EEH core, the binding between EEH device
370 * and the PCI device isn't built yet.
372 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
374 struct pci_controller *hose = pdn->phb;
375 struct pnv_phb *phb = hose->private_data;
376 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
379 int config_addr = (pdn->busno << 8) | (pdn->devfn);
382 * When probing the root bridge, which doesn't have any
383 * subordinate PCI devices. We don't have OF node for
384 * the root bridge. So it's not reasonable to continue
387 if (!edev || edev->pe)
390 /* Skip for PCI-ISA bridge */
391 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
394 /* Skip if we haven't probed yet */
395 if (phb->ioda.pe_rmap[config_addr] == IODA_INVALID_PE) {
396 eeh_add_flag(EEH_POSTPONED_PROBE);
400 /* Initialize eeh device */
401 edev->class_code = pdn->class_code;
402 edev->mode &= 0xFFFFFF00;
403 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
404 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
405 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
406 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
407 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
408 edev->mode |= EEH_DEV_BRIDGE;
409 if (edev->pcie_cap) {
410 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
412 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
413 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
414 edev->mode |= EEH_DEV_ROOT_PORT;
415 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
416 edev->mode |= EEH_DEV_DS_PORT;
420 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
423 ret = eeh_add_to_parent_pe(edev);
425 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n",
426 __func__, hose->global_number, pdn->busno,
427 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
432 * If the PE contains any one of following adapters, the
433 * PCI config space can't be accessed when dumping EEH log.
434 * Otherwise, we will run into fenced PHB caused by shortage
435 * of outbound credits in the adapter. The PCI config access
436 * should be blocked until PE reset. MMIO access is dropped
437 * by hardware certainly. In order to drop PCI config requests,
438 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
439 * will be checked in the backend for PE state retrival. If
440 * the PE becomes frozen for the first time and the flag has
441 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
442 * that PE to block its config space.
444 * Broadcom BCM5718 2-ports NICs (14e4:1656)
445 * Broadcom Austin 4-ports NICs (14e4:1657)
446 * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
447 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
449 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
450 pdn->device_id == 0x1656) ||
451 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
452 pdn->device_id == 0x1657) ||
453 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
454 pdn->device_id == 0x168a) ||
455 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
456 pdn->device_id == 0x168e))
457 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
460 * Cache the PE primary bus, which can't be fetched when
461 * full hotplug is in progress. In that case, all child
462 * PCI devices of the PE are expected to be removed prior
465 if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
466 edev->pe->bus = pci_find_bus(hose->global_number,
469 edev->pe->state |= EEH_PE_PRI_BUS;
473 * Enable EEH explicitly so that we will do EEH check
474 * while accessing I/O stuff
476 eeh_add_flag(EEH_ENABLED);
478 /* Save memory bars */
485 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
487 * @option: operation to be issued
489 * The function is used to control the EEH functionality globally.
490 * Currently, following options are support according to PAPR:
491 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
493 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
495 struct pci_controller *hose = pe->phb;
496 struct pnv_phb *phb = hose->private_data;
497 bool freeze_pe = false;
502 case EEH_OPT_DISABLE:
506 case EEH_OPT_THAW_MMIO:
507 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
509 case EEH_OPT_THAW_DMA:
510 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
512 case EEH_OPT_FREEZE_PE:
514 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
517 pr_warn("%s: Invalid option %d\n", __func__, option);
521 /* Freeze master and slave PEs if PHB supports compound PEs */
523 if (phb->freeze_pe) {
524 phb->freeze_pe(phb, pe->addr);
528 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
529 if (rc != OPAL_SUCCESS) {
530 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
531 __func__, rc, phb->hose->global_number,
539 /* Unfreeze master and slave PEs if PHB supports */
540 if (phb->unfreeze_pe)
541 return phb->unfreeze_pe(phb, pe->addr, opt);
543 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
544 if (rc != OPAL_SUCCESS) {
545 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
546 __func__, rc, option, phb->hose->global_number,
555 * pnv_eeh_get_pe_addr - Retrieve PE address
558 * Retrieve the PE address according to the given tranditional
559 * PCI BDF (Bus/Device/Function) address.
561 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
566 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
568 struct pnv_phb *phb = pe->phb->private_data;
571 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
572 phb->diag_data_size);
573 if (rc != OPAL_SUCCESS)
574 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
575 __func__, rc, pe->phb->global_number);
578 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
580 struct pnv_phb *phb = pe->phb->private_data;
586 rc = opal_pci_eeh_freeze_status(phb->opal_id,
591 if (rc != OPAL_SUCCESS) {
592 pr_warn("%s: Failure %lld getting PHB#%x state\n",
593 __func__, rc, phb->hose->global_number);
594 return EEH_STATE_NOT_SUPPORT;
598 * Check PHB state. If the PHB is frozen for the
599 * first time, to dump the PHB diag-data.
601 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
602 result = (EEH_STATE_MMIO_ACTIVE |
603 EEH_STATE_DMA_ACTIVE |
604 EEH_STATE_MMIO_ENABLED |
605 EEH_STATE_DMA_ENABLED);
606 } else if (!(pe->state & EEH_PE_ISOLATED)) {
607 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
608 pnv_eeh_get_phb_diag(pe);
610 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
611 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
617 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
619 struct pnv_phb *phb = pe->phb->private_data;
626 * We don't clobber hardware frozen state until PE
627 * reset is completed. In order to keep EEH core
628 * moving forward, we have to return operational
629 * state during PE reset.
631 if (pe->state & EEH_PE_RESET) {
632 result = (EEH_STATE_MMIO_ACTIVE |
633 EEH_STATE_DMA_ACTIVE |
634 EEH_STATE_MMIO_ENABLED |
635 EEH_STATE_DMA_ENABLED);
640 * Fetch PE state from hardware. If the PHB
641 * supports compound PE, let it handle that.
643 if (phb->get_pe_state) {
644 fstate = phb->get_pe_state(phb, pe->addr);
646 rc = opal_pci_eeh_freeze_status(phb->opal_id,
651 if (rc != OPAL_SUCCESS) {
652 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
653 __func__, rc, phb->hose->global_number,
655 return EEH_STATE_NOT_SUPPORT;
659 /* Figure out state */
661 case OPAL_EEH_STOPPED_NOT_FROZEN:
662 result = (EEH_STATE_MMIO_ACTIVE |
663 EEH_STATE_DMA_ACTIVE |
664 EEH_STATE_MMIO_ENABLED |
665 EEH_STATE_DMA_ENABLED);
667 case OPAL_EEH_STOPPED_MMIO_FREEZE:
668 result = (EEH_STATE_DMA_ACTIVE |
669 EEH_STATE_DMA_ENABLED);
671 case OPAL_EEH_STOPPED_DMA_FREEZE:
672 result = (EEH_STATE_MMIO_ACTIVE |
673 EEH_STATE_MMIO_ENABLED);
675 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
678 case OPAL_EEH_STOPPED_RESET:
679 result = EEH_STATE_RESET_ACTIVE;
681 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
682 result = EEH_STATE_UNAVAILABLE;
684 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
685 result = EEH_STATE_NOT_SUPPORT;
688 result = EEH_STATE_NOT_SUPPORT;
689 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
690 __func__, phb->hose->global_number,
695 * If PHB supports compound PE, to freeze all
696 * slave PEs for consistency.
698 * If the PE is switching to frozen state for the
699 * first time, to dump the PHB diag-data.
701 if (!(result & EEH_STATE_NOT_SUPPORT) &&
702 !(result & EEH_STATE_UNAVAILABLE) &&
703 !(result & EEH_STATE_MMIO_ACTIVE) &&
704 !(result & EEH_STATE_DMA_ACTIVE) &&
705 !(pe->state & EEH_PE_ISOLATED)) {
707 phb->freeze_pe(phb, pe->addr);
709 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
710 pnv_eeh_get_phb_diag(pe);
712 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
713 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
720 * pnv_eeh_get_state - Retrieve PE state
722 * @delay: delay while PE state is temporarily unavailable
724 * Retrieve the state of the specified PE. For IODA-compitable
725 * platform, it should be retrieved from IODA table. Therefore,
726 * we prefer passing down to hardware implementation to handle
729 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
733 if (pe->type & EEH_PE_PHB)
734 ret = pnv_eeh_get_phb_state(pe);
736 ret = pnv_eeh_get_pe_state(pe);
742 * If the PE state is temporarily unavailable,
743 * to inform the EEH core delay for default
747 if (ret & EEH_STATE_UNAVAILABLE)
753 static s64 pnv_eeh_poll(unsigned long id)
755 s64 rc = OPAL_HARDWARE;
758 rc = opal_pci_poll(id);
762 if (system_state < SYSTEM_RUNNING)
771 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
773 struct pnv_phb *phb = hose->private_data;
774 s64 rc = OPAL_HARDWARE;
776 pr_debug("%s: Reset PHB#%x, option=%d\n",
777 __func__, hose->global_number, option);
779 /* Issue PHB complete reset request */
780 if (option == EEH_RESET_FUNDAMENTAL ||
781 option == EEH_RESET_HOT)
782 rc = opal_pci_reset(phb->opal_id,
783 OPAL_RESET_PHB_COMPLETE,
785 else if (option == EEH_RESET_DEACTIVATE)
786 rc = opal_pci_reset(phb->opal_id,
787 OPAL_RESET_PHB_COMPLETE,
788 OPAL_DEASSERT_RESET);
793 * Poll state of the PHB until the request is done
794 * successfully. The PHB reset is usually PHB complete
795 * reset followed by hot reset on root bus. So we also
796 * need the PCI bus settlement delay.
799 rc = pnv_eeh_poll(phb->opal_id);
800 if (option == EEH_RESET_DEACTIVATE) {
801 if (system_state < SYSTEM_RUNNING)
802 udelay(1000 * EEH_PE_RST_SETTLE_TIME);
804 msleep(EEH_PE_RST_SETTLE_TIME);
807 if (rc != OPAL_SUCCESS)
813 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
815 struct pnv_phb *phb = hose->private_data;
816 s64 rc = OPAL_HARDWARE;
818 pr_debug("%s: Reset PHB#%x, option=%d\n",
819 __func__, hose->global_number, option);
822 * During the reset deassert time, we needn't care
823 * the reset scope because the firmware does nothing
824 * for fundamental or hot reset during deassert phase.
826 if (option == EEH_RESET_FUNDAMENTAL)
827 rc = opal_pci_reset(phb->opal_id,
828 OPAL_RESET_PCI_FUNDAMENTAL,
830 else if (option == EEH_RESET_HOT)
831 rc = opal_pci_reset(phb->opal_id,
834 else if (option == EEH_RESET_DEACTIVATE)
835 rc = opal_pci_reset(phb->opal_id,
837 OPAL_DEASSERT_RESET);
841 /* Poll state of the PHB until the request is done */
843 rc = pnv_eeh_poll(phb->opal_id);
844 if (option == EEH_RESET_DEACTIVATE)
845 msleep(EEH_PE_RST_SETTLE_TIME);
847 if (rc != OPAL_SUCCESS)
853 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
855 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
856 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
857 int aer = edev ? edev->aer_cap : 0;
860 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
861 __func__, pci_domain_nr(dev->bus),
862 dev->bus->number, option);
865 case EEH_RESET_FUNDAMENTAL:
867 /* Don't report linkDown event */
869 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
871 ctrl |= PCI_ERR_UNC_SURPDN;
872 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
876 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
877 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
878 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
880 msleep(EEH_PE_RST_HOLD_TIME);
882 case EEH_RESET_DEACTIVATE:
883 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
884 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
885 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
887 msleep(EEH_PE_RST_SETTLE_TIME);
889 /* Continue reporting linkDown event */
891 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
893 ctrl &= ~PCI_ERR_UNC_SURPDN;
894 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
904 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
906 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
907 struct pnv_phb *phb = hose->private_data;
908 struct device_node *dn = pci_device_to_OF_node(pdev);
909 uint64_t id = PCI_SLOT_ID(phb->opal_id,
910 (pdev->bus->number << 8) | pdev->devfn);
914 /* Hot reset to the bus if firmware cannot handle */
915 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
916 return __pnv_eeh_bridge_reset(pdev, option);
919 case EEH_RESET_FUNDAMENTAL:
920 scope = OPAL_RESET_PCI_FUNDAMENTAL;
923 scope = OPAL_RESET_PCI_HOT;
925 case EEH_RESET_DEACTIVATE:
928 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
933 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
934 if (rc <= OPAL_SUCCESS)
937 rc = pnv_eeh_poll(id);
939 return (rc == OPAL_SUCCESS) ? 0 : -EIO;
942 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
944 struct pci_controller *hose;
946 if (pci_is_root_bus(dev->bus)) {
947 hose = pci_bus_to_host(dev->bus);
948 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
949 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
951 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
952 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
956 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
961 /* Wait for Transaction Pending bit to be cleared */
962 for (i = 0; i < 4; i++) {
963 eeh_ops->read_config(pdn, pos, 2, &status);
964 if (!(status & mask))
967 msleep((1 << i) * 100);
970 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
972 pdn->phb->global_number, pdn->busno,
973 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
976 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
978 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
981 if (WARN_ON(!edev->pcie_cap))
984 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);
985 if (!(reg & PCI_EXP_DEVCAP_FLR))
990 case EEH_RESET_FUNDAMENTAL:
991 pnv_eeh_wait_for_pending(pdn, "",
992 edev->pcie_cap + PCI_EXP_DEVSTA,
993 PCI_EXP_DEVSTA_TRPND);
994 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
996 reg |= PCI_EXP_DEVCTL_BCR_FLR;
997 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
999 msleep(EEH_PE_RST_HOLD_TIME);
1001 case EEH_RESET_DEACTIVATE:
1002 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1004 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
1005 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1007 msleep(EEH_PE_RST_SETTLE_TIME);
1014 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
1016 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1019 if (WARN_ON(!edev->af_cap))
1022 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
1023 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
1028 case EEH_RESET_FUNDAMENTAL:
1030 * Wait for Transaction Pending bit to clear. A word-aligned
1031 * test is used, so we use the conrol offset rather than status
1032 * and shift the test bit to match.
1034 pnv_eeh_wait_for_pending(pdn, "AF",
1035 edev->af_cap + PCI_AF_CTRL,
1036 PCI_AF_STATUS_TP << 8);
1037 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
1038 1, PCI_AF_CTRL_FLR);
1039 msleep(EEH_PE_RST_HOLD_TIME);
1041 case EEH_RESET_DEACTIVATE:
1042 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
1043 msleep(EEH_PE_RST_SETTLE_TIME);
1050 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1052 struct eeh_dev *edev;
1056 /* The VF PE should have only one child device */
1057 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
1058 pdn = eeh_dev_to_pdn(edev);
1062 ret = pnv_eeh_do_flr(pdn, option);
1066 return pnv_eeh_do_af_flr(pdn, option);
1070 * pnv_eeh_reset - Reset the specified PE
1072 * @option: reset option
1074 * Do reset on the indicated PE. For PCI bus sensitive PE,
1075 * we need to reset the parent p2p bridge. The PHB has to
1076 * be reinitialized if the p2p bridge is root bridge. For
1077 * PCI device sensitive PE, we will try to reset the device
1078 * through FLR. For now, we don't have OPAL APIs to do HARD
1079 * reset yet, so all reset would be SOFT (HOT) reset.
1081 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1083 struct pci_controller *hose = pe->phb;
1084 struct pnv_phb *phb;
1085 struct pci_bus *bus;
1089 * For PHB reset, we always have complete reset. For those PEs whose
1090 * primary bus derived from root complex (root bus) or root port
1091 * (usually bus#1), we apply hot or fundamental reset on the root port.
1092 * For other PEs, we always have hot reset on the PE primary bus.
1094 * Here, we have different design to pHyp, which always clear the
1095 * frozen state during PE reset. However, the good idea here from
1096 * benh is to keep frozen state before we get PE reset done completely
1097 * (until BAR restore). With the frozen state, HW drops illegal IO
1098 * or MMIO access, which can incur recrusive frozen PE during PE
1099 * reset. The side effect is that EEH core has to clear the frozen
1100 * state explicitly after BAR restore.
1102 if (pe->type & EEH_PE_PHB)
1103 return pnv_eeh_phb_reset(hose, option);
1106 * The frozen PE might be caused by PAPR error injection
1107 * registers, which are expected to be cleared after hitting
1108 * frozen PE as stated in the hardware spec. Unfortunately,
1109 * that's not true on P7IOC. So we have to clear it manually
1110 * to avoid recursive EEH errors during recovery.
1112 phb = hose->private_data;
1113 if (phb->model == PNV_PHB_MODEL_P7IOC &&
1114 (option == EEH_RESET_HOT ||
1115 option == EEH_RESET_FUNDAMENTAL)) {
1116 rc = opal_pci_reset(phb->opal_id,
1117 OPAL_RESET_PHB_ERROR,
1119 if (rc != OPAL_SUCCESS) {
1120 pr_warn("%s: Failure %lld clearing error injection registers\n",
1126 if (pe->type & EEH_PE_VF)
1127 return pnv_eeh_reset_vf_pe(pe, option);
1129 bus = eeh_pe_bus_get(pe);
1131 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n",
1132 __func__, pe->phb->global_number, pe->addr);
1137 * If dealing with the root bus (or the bus underneath the
1138 * root port), we reset the bus underneath the root port.
1140 * The cxl driver depends on this behaviour for bi-modal card
1143 if (pci_is_root_bus(bus) ||
1144 pci_is_root_bus(bus->parent))
1145 return pnv_eeh_root_reset(hose, option);
1147 return pnv_eeh_bridge_reset(bus->self, option);
1151 * pnv_eeh_wait_state - Wait for PE state
1153 * @max_wait: maximal period in millisecond
1155 * Wait for the state of associated PE. It might take some time
1156 * to retrieve the PE's state.
1158 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
1164 ret = pnv_eeh_get_state(pe, &mwait);
1167 * If the PE's state is temporarily unavailable,
1168 * we have to wait for the specified time. Otherwise,
1169 * the PE's state will be returned immediately.
1171 if (ret != EEH_STATE_UNAVAILABLE)
1174 if (max_wait <= 0) {
1175 pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1176 __func__, pe->addr, max_wait);
1177 return EEH_STATE_NOT_SUPPORT;
1184 return EEH_STATE_NOT_SUPPORT;
1188 * pnv_eeh_get_log - Retrieve error log
1190 * @severity: temporary or permanent error log
1191 * @drv_log: driver log to be combined with retrieved error log
1192 * @len: length of driver log
1194 * Retrieve the temporary or permanent error from the PE.
1196 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1197 char *drv_log, unsigned long len)
1199 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1200 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1206 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1209 * The function will be called to reconfigure the bridges included
1210 * in the specified PE so that the mulfunctional PE would be recovered
1213 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1219 * pnv_pe_err_inject - Inject specified error to the indicated PE
1220 * @pe: the indicated PE
1222 * @func: specific error type
1224 * @mask: address mask
1226 * The routine is called to inject specified error, which is
1227 * determined by @type and @func, to the indicated PE for
1230 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1231 unsigned long addr, unsigned long mask)
1233 struct pci_controller *hose = pe->phb;
1234 struct pnv_phb *phb = hose->private_data;
1237 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1238 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1239 pr_warn("%s: Invalid error type %d\n",
1244 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1245 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1246 pr_warn("%s: Invalid error function %d\n",
1251 /* Firmware supports error injection ? */
1252 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1253 pr_warn("%s: Firmware doesn't support error injection\n",
1258 /* Do error injection */
1259 rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1260 type, func, addr, mask);
1261 if (rc != OPAL_SUCCESS) {
1262 pr_warn("%s: Failure %lld injecting error "
1263 "%d-%d to PHB#%x-PE#%x\n",
1264 __func__, rc, type, func,
1265 hose->global_number, pe->addr);
1272 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1274 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1276 if (!edev || !edev->pe)
1280 * We will issue FLR or AF FLR to all VFs, which are contained
1281 * in VF PE. It relies on the EEH PCI config accessors. So we
1282 * can't block them during the window.
1284 if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1287 if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1293 static int pnv_eeh_read_config(struct pci_dn *pdn,
1294 int where, int size, u32 *val)
1297 return PCIBIOS_DEVICE_NOT_FOUND;
1299 if (pnv_eeh_cfg_blocked(pdn)) {
1301 return PCIBIOS_SET_FAILED;
1304 return pnv_pci_cfg_read(pdn, where, size, val);
1307 static int pnv_eeh_write_config(struct pci_dn *pdn,
1308 int where, int size, u32 val)
1311 return PCIBIOS_DEVICE_NOT_FOUND;
1313 if (pnv_eeh_cfg_blocked(pdn))
1314 return PCIBIOS_SET_FAILED;
1316 return pnv_pci_cfg_write(pdn, where, size, val);
1319 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1322 if (data->gemXfir || data->gemRfir ||
1323 data->gemRirqfir || data->gemMask || data->gemRwof)
1324 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
1325 be64_to_cpu(data->gemXfir),
1326 be64_to_cpu(data->gemRfir),
1327 be64_to_cpu(data->gemRirqfir),
1328 be64_to_cpu(data->gemMask),
1329 be64_to_cpu(data->gemRwof));
1332 if (data->lemFir || data->lemErrMask ||
1333 data->lemAction0 || data->lemAction1 || data->lemWof)
1334 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
1335 be64_to_cpu(data->lemFir),
1336 be64_to_cpu(data->lemErrMask),
1337 be64_to_cpu(data->lemAction0),
1338 be64_to_cpu(data->lemAction1),
1339 be64_to_cpu(data->lemWof));
1342 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1344 struct pnv_phb *phb = hose->private_data;
1345 struct OpalIoP7IOCErrorData *data =
1346 (struct OpalIoP7IOCErrorData*)phb->diag_data;
1349 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1350 if (rc != OPAL_SUCCESS) {
1351 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1352 __func__, phb->hub_id, rc);
1356 switch (be16_to_cpu(data->type)) {
1357 case OPAL_P7IOC_DIAG_TYPE_RGC:
1358 pr_info("P7IOC diag-data for RGC\n\n");
1359 pnv_eeh_dump_hub_diag_common(data);
1360 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1361 pr_info(" RGC: %016llx %016llx\n",
1362 be64_to_cpu(data->rgc.rgcStatus),
1363 be64_to_cpu(data->rgc.rgcLdcp));
1365 case OPAL_P7IOC_DIAG_TYPE_BI:
1366 pr_info("P7IOC diag-data for BI %s\n\n",
1367 data->bi.biDownbound ? "Downbound" : "Upbound");
1368 pnv_eeh_dump_hub_diag_common(data);
1369 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1370 data->bi.biLdcp2 || data->bi.biFenceStatus)
1371 pr_info(" BI: %016llx %016llx %016llx %016llx\n",
1372 be64_to_cpu(data->bi.biLdcp0),
1373 be64_to_cpu(data->bi.biLdcp1),
1374 be64_to_cpu(data->bi.biLdcp2),
1375 be64_to_cpu(data->bi.biFenceStatus));
1377 case OPAL_P7IOC_DIAG_TYPE_CI:
1378 pr_info("P7IOC diag-data for CI Port %d\n\n",
1380 pnv_eeh_dump_hub_diag_common(data);
1381 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1382 pr_info(" CI: %016llx %016llx\n",
1383 be64_to_cpu(data->ci.ciPortStatus),
1384 be64_to_cpu(data->ci.ciPortLdcp));
1386 case OPAL_P7IOC_DIAG_TYPE_MISC:
1387 pr_info("P7IOC diag-data for MISC\n\n");
1388 pnv_eeh_dump_hub_diag_common(data);
1390 case OPAL_P7IOC_DIAG_TYPE_I2C:
1391 pr_info("P7IOC diag-data for I2C\n\n");
1392 pnv_eeh_dump_hub_diag_common(data);
1395 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1396 __func__, phb->hub_id, data->type);
1400 static int pnv_eeh_get_pe(struct pci_controller *hose,
1401 u16 pe_no, struct eeh_pe **pe)
1403 struct pnv_phb *phb = hose->private_data;
1404 struct pnv_ioda_pe *pnv_pe;
1405 struct eeh_pe *dev_pe;
1408 * If PHB supports compound PE, to fetch
1409 * the master PE because slave PE is invisible
1412 pnv_pe = &phb->ioda.pe_array[pe_no];
1413 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1414 pnv_pe = pnv_pe->master;
1416 !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1417 pe_no = pnv_pe->pe_number;
1420 /* Find the PE according to PE# */
1421 dev_pe = eeh_pe_get(hose, pe_no, 0);
1425 /* Freeze the (compound) PE */
1427 if (!(dev_pe->state & EEH_PE_ISOLATED))
1428 phb->freeze_pe(phb, pe_no);
1431 * At this point, we're sure the (compound) PE should
1432 * have been frozen. However, we still need poke until
1433 * hitting the frozen PE on top level.
1435 dev_pe = dev_pe->parent;
1436 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1438 ret = eeh_ops->get_state(dev_pe, NULL);
1439 if (ret <= 0 || eeh_state_active(ret)) {
1440 dev_pe = dev_pe->parent;
1444 /* Frozen parent PE */
1446 if (!(dev_pe->state & EEH_PE_ISOLATED))
1447 phb->freeze_pe(phb, dev_pe->addr);
1450 dev_pe = dev_pe->parent;
1457 * pnv_eeh_next_error - Retrieve next EEH error to handle
1460 * The function is expected to be called by EEH core while it gets
1461 * special EEH event (without binding PE). The function calls to
1462 * OPAL APIs for next error to handle. The informational error is
1463 * handled internally by platform. However, the dead IOC, dead PHB,
1464 * fenced PHB and frozen PE should be handled by EEH core eventually.
1466 static int pnv_eeh_next_error(struct eeh_pe **pe)
1468 struct pci_controller *hose;
1469 struct pnv_phb *phb;
1470 struct eeh_pe *phb_pe, *parent_pe;
1471 __be64 frozen_pe_no;
1472 __be16 err_type, severity;
1474 int state, ret = EEH_NEXT_ERR_NONE;
1477 * While running here, it's safe to purge the event queue. The
1478 * event should still be masked.
1480 eeh_remove_event(NULL, false);
1482 list_for_each_entry(hose, &hose_list, list_node) {
1484 * If the subordinate PCI buses of the PHB has been
1485 * removed or is exactly under error recovery, we
1486 * needn't take care of it any more.
1488 phb = hose->private_data;
1489 phb_pe = eeh_phb_pe_get(hose);
1490 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1493 rc = opal_pci_next_error(phb->opal_id,
1494 &frozen_pe_no, &err_type, &severity);
1495 if (rc != OPAL_SUCCESS) {
1496 pr_devel("%s: Invalid return value on "
1497 "PHB#%x (0x%lx) from opal_pci_next_error",
1498 __func__, hose->global_number, rc);
1502 /* If the PHB doesn't have error, stop processing */
1503 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1504 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1505 pr_devel("%s: No error found on PHB#%x\n",
1506 __func__, hose->global_number);
1511 * Processing the error. We're expecting the error with
1512 * highest priority reported upon multiple errors on the
1515 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1516 __func__, be16_to_cpu(err_type),
1517 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1518 hose->global_number);
1519 switch (be16_to_cpu(err_type)) {
1520 case OPAL_EEH_IOC_ERROR:
1521 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1522 pr_err("EEH: dead IOC detected\n");
1523 ret = EEH_NEXT_ERR_DEAD_IOC;
1524 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1525 pr_info("EEH: IOC informative error "
1527 pnv_eeh_get_and_dump_hub_diag(hose);
1528 ret = EEH_NEXT_ERR_NONE;
1532 case OPAL_EEH_PHB_ERROR:
1533 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1535 pr_err("EEH: dead PHB#%x detected, "
1537 hose->global_number,
1538 eeh_pe_loc_get(phb_pe));
1539 ret = EEH_NEXT_ERR_DEAD_PHB;
1540 } else if (be16_to_cpu(severity) ==
1541 OPAL_EEH_SEV_PHB_FENCED) {
1543 pr_err("EEH: Fenced PHB#%x detected, "
1545 hose->global_number,
1546 eeh_pe_loc_get(phb_pe));
1547 ret = EEH_NEXT_ERR_FENCED_PHB;
1548 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1549 pr_info("EEH: PHB#%x informative error "
1550 "detected, location: %s\n",
1551 hose->global_number,
1552 eeh_pe_loc_get(phb_pe));
1553 pnv_eeh_get_phb_diag(phb_pe);
1554 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1555 ret = EEH_NEXT_ERR_NONE;
1559 case OPAL_EEH_PE_ERROR:
1561 * If we can't find the corresponding PE, we
1562 * just try to unfreeze.
1564 if (pnv_eeh_get_pe(hose,
1565 be64_to_cpu(frozen_pe_no), pe)) {
1566 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1567 hose->global_number, be64_to_cpu(frozen_pe_no));
1568 pr_info("EEH: PHB location: %s\n",
1569 eeh_pe_loc_get(phb_pe));
1571 /* Dump PHB diag-data */
1572 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1573 phb->diag_data, phb->diag_data_size);
1574 if (rc == OPAL_SUCCESS)
1575 pnv_pci_dump_phb_diag_data(hose,
1578 /* Try best to clear it */
1579 opal_pci_eeh_freeze_clear(phb->opal_id,
1580 be64_to_cpu(frozen_pe_no),
1581 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1582 ret = EEH_NEXT_ERR_NONE;
1583 } else if ((*pe)->state & EEH_PE_ISOLATED ||
1584 eeh_pe_passed(*pe)) {
1585 ret = EEH_NEXT_ERR_NONE;
1587 pr_err("EEH: Frozen PE#%x "
1588 "on PHB#%x detected\n",
1590 (*pe)->phb->global_number);
1591 pr_err("EEH: PE location: %s, "
1592 "PHB location: %s\n",
1593 eeh_pe_loc_get(*pe),
1594 eeh_pe_loc_get(phb_pe));
1595 ret = EEH_NEXT_ERR_FROZEN_PE;
1600 pr_warn("%s: Unexpected error type %d\n",
1601 __func__, be16_to_cpu(err_type));
1605 * EEH core will try recover from fenced PHB or
1606 * frozen PE. In the time for frozen PE, EEH core
1607 * enable IO path for that before collecting logs,
1608 * but it ruins the site. So we have to dump the
1609 * log in advance here.
1611 if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
1612 ret == EEH_NEXT_ERR_FENCED_PHB) &&
1613 !((*pe)->state & EEH_PE_ISOLATED)) {
1614 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1615 pnv_eeh_get_phb_diag(*pe);
1617 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1618 pnv_pci_dump_phb_diag_data((*pe)->phb,
1623 * We probably have the frozen parent PE out there and
1624 * we need have to handle frozen parent PE firstly.
1626 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1627 parent_pe = (*pe)->parent;
1629 /* Hit the ceiling ? */
1630 if (parent_pe->type & EEH_PE_PHB)
1633 /* Frozen parent PE ? */
1634 state = eeh_ops->get_state(parent_pe, NULL);
1635 if (state > 0 && !eeh_state_active(state))
1638 /* Next parent level */
1639 parent_pe = parent_pe->parent;
1642 /* We possibly migrate to another PE */
1643 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1647 * If we have no errors on the specific PHB or only
1648 * informative error there, we continue poking it.
1649 * Otherwise, we need actions to be taken by upper
1652 if (ret > EEH_NEXT_ERR_INF)
1656 /* Unmask the event */
1657 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1658 enable_irq(eeh_event_irq);
1663 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1665 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1666 struct pnv_phb *phb;
1668 int config_addr = (pdn->busno << 8) | (pdn->devfn);
1674 * We have to restore the PCI config space after reset since the
1675 * firmware can't see SRIOV VFs.
1677 * FIXME: The MPS, error routing rules, timeout setting are worthy
1678 * to be exported by firmware in extendible way.
1681 ret = eeh_restore_vf_config(pdn);
1683 phb = pdn->phb->private_data;
1684 ret = opal_pci_reinit(phb->opal_id,
1685 OPAL_REINIT_PCI_DEV, config_addr);
1689 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1690 __func__, config_addr, ret);
1697 static struct eeh_ops pnv_eeh_ops = {
1699 .init = pnv_eeh_init,
1700 .probe = pnv_eeh_probe,
1701 .set_option = pnv_eeh_set_option,
1702 .get_pe_addr = pnv_eeh_get_pe_addr,
1703 .get_state = pnv_eeh_get_state,
1704 .reset = pnv_eeh_reset,
1705 .wait_state = pnv_eeh_wait_state,
1706 .get_log = pnv_eeh_get_log,
1707 .configure_bridge = pnv_eeh_configure_bridge,
1708 .err_inject = pnv_eeh_err_inject,
1709 .read_config = pnv_eeh_read_config,
1710 .write_config = pnv_eeh_write_config,
1711 .next_error = pnv_eeh_next_error,
1712 .restore_config = pnv_eeh_restore_config,
1713 .notify_resume = NULL
1716 #ifdef CONFIG_PCI_IOV
1717 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1719 struct pci_dn *pdn = pci_get_pdn(pdev);
1722 if (!pdev->is_virtfn)
1725 /* Synchronize MPS for VF and PF */
1726 parent_mps = pcie_get_mps(pdev->physfn);
1727 if ((128 << pdev->pcie_mpss) >= parent_mps)
1728 pcie_set_mps(pdev, parent_mps);
1729 pdn->mps = pcie_get_mps(pdev);
1731 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1732 #endif /* CONFIG_PCI_IOV */
1735 * eeh_powernv_init - Register platform dependent EEH operations
1737 * EEH initialization on powernv platform. This function should be
1738 * called before any EEH related functions.
1740 static int __init eeh_powernv_init(void)
1744 ret = eeh_ops_register(&pnv_eeh_ops);
1746 pr_info("EEH: PowerNV platform initialized\n");
1748 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1752 machine_early_initcall(powernv, eeh_powernv_init);