2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/cputable.h>
17 #include <asm/cache.h>
18 #include <asm/thread_info.h>
19 #include <asm/asm-offsets.h>
21 #include <asm/feature-fixups.h>
23 #define MAGIC 0x4c617273 /* 'Lars' */
26 * Structure for storing CPU registers on the stack.
32 #define SL_SPRG0 0x10 /* 4 sprg's */
52 #define SL_R12 0xb0 /* r12 to r31 */
53 #define SL_SIZE (SL_R12 + 80)
58 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
59 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
61 /* This gets called by via-pmu.c late during the sleep process.
62 * The PMU was already send the sleep command and will shut us down
63 * soon. We need to save all that is needed and setup the wakeup
64 * vector that will be called by the ROM on wakeup
66 _GLOBAL(low_sleep_handler)
84 /* Get a stable timebase and save it */
101 stw r4,SL_SPRG0+12(r1)
107 stw r4,SL_DBAT0+4(r1)
111 stw r4,SL_DBAT1+4(r1)
115 stw r4,SL_DBAT2+4(r1)
119 stw r4,SL_DBAT3+4(r1)
123 stw r4,SL_IBAT0+4(r1)
127 stw r4,SL_IBAT1+4(r1)
131 stw r4,SL_IBAT2+4(r1)
135 stw r4,SL_IBAT3+4(r1)
137 BEGIN_MMU_FTR_SECTION
141 stw r4,SL_DBAT4+4(r1)
145 stw r4,SL_DBAT5+4(r1)
149 stw r4,SL_DBAT6+4(r1)
153 stw r4,SL_DBAT7+4(r1)
157 stw r4,SL_IBAT4+4(r1)
161 stw r4,SL_IBAT5+4(r1)
165 stw r4,SL_IBAT6+4(r1)
169 stw r4,SL_IBAT7+4(r1)
170 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
172 /* Backup various CPU config stuffs */
175 /* The ROM can wake us up via 2 different vectors:
176 * - On wallstreet & lombard, we must write a magic
177 * value 'Lars' at address 4 and a pointer to a
178 * memory location containing the PC to resume from
180 * - On Core99, we must store the wakeup vector at
181 * address 0x80 and eventually it's parameters
182 * at address 0x84. I've have some trouble with those
183 * parameters however and I no longer use them.
185 lis r5,grackle_wake_up@ha
186 addi r5,r5,grackle_wake_up@l
196 /* Setup stuffs at 0x80-0x84 for Core99 */
197 lis r3,core99_wake_up@ha
198 addi r3,r3,core99_wake_up@l
202 /* Store a pointer to our backup storage into
205 lis r3,sleep_storage@ha
206 addi r3,r3,sleep_storage@l
211 /* Flush & disable all caches */
212 bl flush_disable_caches
214 /* Turn off data relocation. */
215 mfmsr r3 /* Save MSR in r7 */
216 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
222 /* Flush any pending L2 data prefetches to work around HW bug */
225 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
226 sync /* (caches are disabled at this point) */
227 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
230 * Set the HID0 and MSR for sleep.
233 rlwinm r2,r2,0,10,7 /* clear doze, nap */
234 oris r2,r2,HID0_SLEEP@h
240 /* This loop puts us back to sleep in case we have a spurrious
241 * wakeup so that the host bridge properly stays asleep. The
242 * CPU will be turned off, either after a known time (about 1
243 * second) on wallstreet & lombard, or as soon as the CPU enters
244 * SLEEP mode on core99
254 * Here is the resume code.
259 * Core99 machines resume here
260 * r4 has the physical address of SL_PC(sp) (unused)
262 _GLOBAL(core99_wake_up)
263 /* Make sure HID0 no longer contains any sleep bit and that data cache
267 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
268 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
275 ori r3,r3,MSR_EE|MSR_IP
276 xori r3,r3,MSR_EE|MSR_IP
283 /* Recover sleep storage */
284 lis r3,sleep_storage@ha
285 addi r3,r3,sleep_storage@l
289 /* Pass thru to older resume code ... */
291 * Here is the resume code for older machines.
292 * r1 has the physical address of SL_PC(sp).
297 /* Restore the kernel's segment registers before
298 * we do any r1 memory access as we are not sure they
299 * are in a sane state above the first 256Mb region
301 li r0,16 /* load up segment register values */
302 mtctr r0 /* for context 0 */
303 lis r3,0x2000 /* Ku = 1, VSID = 0 */
306 addi r3,r3,0x111 /* increment VSID */
307 addis r4,r4,0x1000 /* address of next segment */
314 /* Restore various CPU config stuffs */
315 bl __restore_cpu_setup
317 /* Make sure all FPRs have been initialized */
319 bl __init_fpu_registers
321 /* Invalidate & enable L1 cache, we don't care about
322 * whatever the ROM may have tried to write to memory
326 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
331 lwz r4,SL_SPRG0+4(r1)
333 lwz r4,SL_SPRG0+8(r1)
335 lwz r4,SL_SPRG0+12(r1)
340 lwz r4,SL_DBAT0+4(r1)
344 lwz r4,SL_DBAT1+4(r1)
348 lwz r4,SL_DBAT2+4(r1)
352 lwz r4,SL_DBAT3+4(r1)
356 lwz r4,SL_IBAT0+4(r1)
360 lwz r4,SL_IBAT1+4(r1)
364 lwz r4,SL_IBAT2+4(r1)
368 lwz r4,SL_IBAT3+4(r1)
371 BEGIN_MMU_FTR_SECTION
374 lwz r4,SL_DBAT4+4(r1)
378 lwz r4,SL_DBAT5+4(r1)
382 lwz r4,SL_DBAT6+4(r1)
386 lwz r4,SL_DBAT7+4(r1)
390 lwz r4,SL_IBAT4+4(r1)
394 lwz r4,SL_IBAT5+4(r1)
398 lwz r4,SL_IBAT6+4(r1)
402 lwz r4,SL_IBAT7+4(r1)
404 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
408 1: addic. r4,r4,-0x1000
413 /* restore the MSR and turn on the MMU */
417 /* get back the stack pointer */
428 /* Restore the callee-saved registers and return */
447 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
450 .balign L1_CACHE_BYTES
453 .balign L1_CACHE_BYTES, 0
455 #endif /* CONFIG_6xx */