2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/cputable.h>
17 #include <asm/cache.h>
18 #include <asm/thread_info.h>
19 #include <asm/asm-offsets.h>
22 #define MAGIC 0x4c617273 /* 'Lars' */
25 * Structure for storing CPU registers on the stack.
31 #define SL_SPRG0 0x10 /* 4 sprg's */
51 #define SL_R12 0xb0 /* r12 to r31 */
52 #define SL_SIZE (SL_R12 + 80)
57 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
58 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
60 /* This gets called by via-pmu.c late during the sleep process.
61 * The PMU was already send the sleep command and will shut us down
62 * soon. We need to save all that is needed and setup the wakeup
63 * vector that will be called by the ROM on wakeup
65 _GLOBAL(low_sleep_handler)
83 /* Get a stable timebase and save it */
100 stw r4,SL_SPRG0+12(r1)
106 stw r4,SL_DBAT0+4(r1)
110 stw r4,SL_DBAT1+4(r1)
114 stw r4,SL_DBAT2+4(r1)
118 stw r4,SL_DBAT3+4(r1)
122 stw r4,SL_IBAT0+4(r1)
126 stw r4,SL_IBAT1+4(r1)
130 stw r4,SL_IBAT2+4(r1)
134 stw r4,SL_IBAT3+4(r1)
136 BEGIN_MMU_FTR_SECTION
140 stw r4,SL_DBAT4+4(r1)
144 stw r4,SL_DBAT5+4(r1)
148 stw r4,SL_DBAT6+4(r1)
152 stw r4,SL_DBAT7+4(r1)
156 stw r4,SL_IBAT4+4(r1)
160 stw r4,SL_IBAT5+4(r1)
164 stw r4,SL_IBAT6+4(r1)
168 stw r4,SL_IBAT7+4(r1)
169 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
171 /* Backup various CPU config stuffs */
174 /* The ROM can wake us up via 2 different vectors:
175 * - On wallstreet & lombard, we must write a magic
176 * value 'Lars' at address 4 and a pointer to a
177 * memory location containing the PC to resume from
179 * - On Core99, we must store the wakeup vector at
180 * address 0x80 and eventually it's parameters
181 * at address 0x84. I've have some trouble with those
182 * parameters however and I no longer use them.
184 lis r5,grackle_wake_up@ha
185 addi r5,r5,grackle_wake_up@l
195 /* Setup stuffs at 0x80-0x84 for Core99 */
196 lis r3,core99_wake_up@ha
197 addi r3,r3,core99_wake_up@l
201 /* Store a pointer to our backup storage into
204 lis r3,sleep_storage@ha
205 addi r3,r3,sleep_storage@l
210 /* Flush & disable all caches */
211 bl flush_disable_caches
213 /* Turn off data relocation. */
214 mfmsr r3 /* Save MSR in r7 */
215 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
221 /* Flush any pending L2 data prefetches to work around HW bug */
224 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
225 sync /* (caches are disabled at this point) */
226 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
229 * Set the HID0 and MSR for sleep.
232 rlwinm r2,r2,0,10,7 /* clear doze, nap */
233 oris r2,r2,HID0_SLEEP@h
239 /* This loop puts us back to sleep in case we have a spurrious
240 * wakeup so that the host bridge properly stays asleep. The
241 * CPU will be turned off, either after a known time (about 1
242 * second) on wallstreet & lombard, or as soon as the CPU enters
243 * SLEEP mode on core99
253 * Here is the resume code.
258 * Core99 machines resume here
259 * r4 has the physical address of SL_PC(sp) (unused)
261 _GLOBAL(core99_wake_up)
262 /* Make sure HID0 no longer contains any sleep bit and that data cache
266 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
267 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
274 ori r3,r3,MSR_EE|MSR_IP
275 xori r3,r3,MSR_EE|MSR_IP
282 /* Recover sleep storage */
283 lis r3,sleep_storage@ha
284 addi r3,r3,sleep_storage@l
288 /* Pass thru to older resume code ... */
290 * Here is the resume code for older machines.
291 * r1 has the physical address of SL_PC(sp).
296 /* Restore the kernel's segment registers before
297 * we do any r1 memory access as we are not sure they
298 * are in a sane state above the first 256Mb region
300 li r0,16 /* load up segment register values */
301 mtctr r0 /* for context 0 */
302 lis r3,0x2000 /* Ku = 1, VSID = 0 */
305 addi r3,r3,0x111 /* increment VSID */
306 addis r4,r4,0x1000 /* address of next segment */
313 /* Restore various CPU config stuffs */
314 bl __restore_cpu_setup
316 /* Make sure all FPRs have been initialized */
318 bl __init_fpu_registers
320 /* Invalidate & enable L1 cache, we don't care about
321 * whatever the ROM may have tried to write to memory
325 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
330 lwz r4,SL_SPRG0+4(r1)
332 lwz r4,SL_SPRG0+8(r1)
334 lwz r4,SL_SPRG0+12(r1)
339 lwz r4,SL_DBAT0+4(r1)
343 lwz r4,SL_DBAT1+4(r1)
347 lwz r4,SL_DBAT2+4(r1)
351 lwz r4,SL_DBAT3+4(r1)
355 lwz r4,SL_IBAT0+4(r1)
359 lwz r4,SL_IBAT1+4(r1)
363 lwz r4,SL_IBAT2+4(r1)
367 lwz r4,SL_IBAT3+4(r1)
370 BEGIN_MMU_FTR_SECTION
373 lwz r4,SL_DBAT4+4(r1)
377 lwz r4,SL_DBAT5+4(r1)
381 lwz r4,SL_DBAT6+4(r1)
385 lwz r4,SL_DBAT7+4(r1)
389 lwz r4,SL_IBAT4+4(r1)
393 lwz r4,SL_IBAT5+4(r1)
397 lwz r4,SL_IBAT6+4(r1)
401 lwz r4,SL_IBAT7+4(r1)
403 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
407 1: addic. r4,r4,-0x1000
412 /* restore the MSR and turn on the MMU */
416 /* get back the stack pointer */
427 /* Restore the callee-saved registers and return */
446 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
449 .balign L1_CACHE_BYTES
452 .balign L1_CACHE_BYTES, 0
454 #endif /* CONFIG_6xx */