1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains sleep low-level functions for PowerBook G3.
4 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * and Paul Mackerras (paulus@samba.org).
8 #include <asm/processor.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/cputable.h>
12 #include <asm/cache.h>
13 #include <asm/thread_info.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
18 #define MAGIC 0x4c617273 /* 'Lars' */
21 * Structure for storing CPU registers on the stack.
27 #define SL_SPRG0 0x10 /* 4 sprg's */
47 #define SL_R12 0xb0 /* r12 to r31 */
48 #define SL_SIZE (SL_R12 + 80)
53 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
54 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
56 /* This gets called by via-pmu.c late during the sleep process.
57 * The PMU was already send the sleep command and will shut us down
58 * soon. We need to save all that is needed and setup the wakeup
59 * vector that will be called by the ROM on wakeup
61 _GLOBAL(low_sleep_handler)
62 #ifndef CONFIG_PPC_BOOK3S_32
79 /* Get a stable timebase and save it */
96 stw r4,SL_SPRG0+12(r1)
102 stw r4,SL_DBAT0+4(r1)
106 stw r4,SL_DBAT1+4(r1)
110 stw r4,SL_DBAT2+4(r1)
114 stw r4,SL_DBAT3+4(r1)
118 stw r4,SL_IBAT0+4(r1)
122 stw r4,SL_IBAT1+4(r1)
126 stw r4,SL_IBAT2+4(r1)
130 stw r4,SL_IBAT3+4(r1)
132 BEGIN_MMU_FTR_SECTION
136 stw r4,SL_DBAT4+4(r1)
140 stw r4,SL_DBAT5+4(r1)
144 stw r4,SL_DBAT6+4(r1)
148 stw r4,SL_DBAT7+4(r1)
152 stw r4,SL_IBAT4+4(r1)
156 stw r4,SL_IBAT5+4(r1)
160 stw r4,SL_IBAT6+4(r1)
164 stw r4,SL_IBAT7+4(r1)
165 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
167 /* Backup various CPU config stuffs */
170 /* The ROM can wake us up via 2 different vectors:
171 * - On wallstreet & lombard, we must write a magic
172 * value 'Lars' at address 4 and a pointer to a
173 * memory location containing the PC to resume from
175 * - On Core99, we must store the wakeup vector at
176 * address 0x80 and eventually it's parameters
177 * at address 0x84. I've have some trouble with those
178 * parameters however and I no longer use them.
180 lis r5,grackle_wake_up@ha
181 addi r5,r5,grackle_wake_up@l
191 /* Setup stuffs at 0x80-0x84 for Core99 */
192 lis r3,core99_wake_up@ha
193 addi r3,r3,core99_wake_up@l
197 /* Store a pointer to our backup storage into
200 lis r3,sleep_storage@ha
201 addi r3,r3,sleep_storage@l
206 /* Flush & disable all caches */
207 bl flush_disable_caches
209 /* Turn off data relocation. */
210 mfmsr r3 /* Save MSR in r7 */
211 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
217 /* Flush any pending L2 data prefetches to work around HW bug */
220 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
221 sync /* (caches are disabled at this point) */
222 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
225 * Set the HID0 and MSR for sleep.
228 rlwinm r2,r2,0,10,7 /* clear doze, nap */
229 oris r2,r2,HID0_SLEEP@h
235 /* This loop puts us back to sleep in case we have a spurrious
236 * wakeup so that the host bridge properly stays asleep. The
237 * CPU will be turned off, either after a known time (about 1
238 * second) on wallstreet & lombard, or as soon as the CPU enters
239 * SLEEP mode on core99
249 * Here is the resume code.
254 * Core99 machines resume here
255 * r4 has the physical address of SL_PC(sp) (unused)
257 _GLOBAL(core99_wake_up)
258 /* Make sure HID0 no longer contains any sleep bit and that data cache
262 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
263 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
270 ori r3,r3,MSR_EE|MSR_IP
271 xori r3,r3,MSR_EE|MSR_IP
278 /* Recover sleep storage */
279 lis r3,sleep_storage@ha
280 addi r3,r3,sleep_storage@l
284 /* Pass thru to older resume code ... */
286 * Here is the resume code for older machines.
287 * r1 has the physical address of SL_PC(sp).
292 /* Restore the kernel's segment registers before
293 * we do any r1 memory access as we are not sure they
294 * are in a sane state above the first 256Mb region
296 bl load_segment_registers
302 /* Restore various CPU config stuffs */
303 bl __restore_cpu_setup
305 /* Make sure all FPRs have been initialized */
307 bl __init_fpu_registers
309 /* Invalidate & enable L1 cache, we don't care about
310 * whatever the ROM may have tried to write to memory
314 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
319 lwz r4,SL_SPRG0+4(r1)
321 lwz r4,SL_SPRG0+8(r1)
323 lwz r4,SL_SPRG0+12(r1)
328 lwz r4,SL_DBAT0+4(r1)
332 lwz r4,SL_DBAT1+4(r1)
336 lwz r4,SL_DBAT2+4(r1)
340 lwz r4,SL_DBAT3+4(r1)
344 lwz r4,SL_IBAT0+4(r1)
348 lwz r4,SL_IBAT1+4(r1)
352 lwz r4,SL_IBAT2+4(r1)
356 lwz r4,SL_IBAT3+4(r1)
359 BEGIN_MMU_FTR_SECTION
362 lwz r4,SL_DBAT4+4(r1)
366 lwz r4,SL_DBAT5+4(r1)
370 lwz r4,SL_DBAT6+4(r1)
374 lwz r4,SL_DBAT7+4(r1)
378 lwz r4,SL_IBAT4+4(r1)
382 lwz r4,SL_IBAT5+4(r1)
386 lwz r4,SL_IBAT6+4(r1)
390 lwz r4,SL_IBAT7+4(r1)
392 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
396 1: addic. r4,r4,-0x1000
401 /* restore the MSR and turn on the MMU */
405 /* get back the stack pointer */
416 /* Restore the callee-saved registers and return */
435 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
438 .balign L1_CACHE_BYTES
441 .balign L1_CACHE_BYTES, 0
443 #endif /* CONFIG_PPC_BOOK3S_32 */