1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the interrupt controllers found on Power Macintosh,
4 * currently Apple's "Grand Central" interrupt controller in all
5 * it's incarnations. OpenPIC support used on newer machines is
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
13 #include <linux/stddef.h>
14 #include <linux/init.h>
15 #include <linux/sched.h>
16 #include <linux/signal.h>
17 #include <linux/pci.h>
18 #include <linux/interrupt.h>
19 #include <linux/syscore_ops.h>
20 #include <linux/adb.h>
21 #include <linux/minmax.h>
22 #include <linux/pmu.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <asm/sections.h>
30 #include <asm/pci-bridge.h>
32 #include <asm/pmac_feature.h>
46 /* Workaround flags for 32bit powermac machines */
47 unsigned int of_irq_workarounds;
48 struct device_node *of_irq_dflt_pic;
50 /* Default addresses */
51 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
54 static int max_real_irqs;
56 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
58 /* The max irq number this driver deals with is 128; see max_irqs */
59 static DECLARE_BITMAP(ppc_lost_interrupts, 128);
60 static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
61 static int pmac_irq_cascade = -1;
62 static struct irq_domain *pmac_pic_host;
64 static void __pmac_retrigger(unsigned int irq_nr)
66 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
67 __set_bit(irq_nr, ppc_lost_interrupts);
68 irq_nr = pmac_irq_cascade;
71 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
72 atomic_inc(&ppc_n_lost_interrupts);
77 static void pmac_mask_and_ack_irq(struct irq_data *d)
79 unsigned int src = irqd_to_hwirq(d);
80 unsigned long bit = 1UL << (src & 0x1f);
84 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
85 __clear_bit(src, ppc_cached_irq_mask);
86 if (__test_and_clear_bit(src, ppc_lost_interrupts))
87 atomic_dec(&ppc_n_lost_interrupts);
88 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
89 out_le32(&pmac_irq_hw[i]->ack, bit);
91 /* make sure ack gets to controller before we enable
94 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
95 != (ppc_cached_irq_mask[i] & bit));
96 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
99 static void pmac_ack_irq(struct irq_data *d)
101 unsigned int src = irqd_to_hwirq(d);
102 unsigned long bit = 1UL << (src & 0x1f);
106 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
107 if (__test_and_clear_bit(src, ppc_lost_interrupts))
108 atomic_dec(&ppc_n_lost_interrupts);
109 out_le32(&pmac_irq_hw[i]->ack, bit);
110 (void)in_le32(&pmac_irq_hw[i]->ack);
111 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
114 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
116 unsigned long bit = 1UL << (irq_nr & 0x1f);
119 if ((unsigned)irq_nr >= max_irqs)
122 /* enable unmasked interrupts */
123 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
126 /* make sure mask gets to controller before we
129 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
130 != (ppc_cached_irq_mask[i] & bit));
133 * Unfortunately, setting the bit in the enable register
134 * when the device interrupt is already on *doesn't* set
135 * the bit in the flag register or request another interrupt.
137 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
138 __pmac_retrigger(irq_nr);
141 /* When an irq gets requested for the first client, if it's an
142 * edge interrupt, we clear any previous one on the controller
144 static unsigned int pmac_startup_irq(struct irq_data *d)
147 unsigned int src = irqd_to_hwirq(d);
148 unsigned long bit = 1UL << (src & 0x1f);
151 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
152 if (!irqd_is_level_type(d))
153 out_le32(&pmac_irq_hw[i]->ack, bit);
154 __set_bit(src, ppc_cached_irq_mask);
155 __pmac_set_irq_mask(src, 0);
156 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
161 static void pmac_mask_irq(struct irq_data *d)
164 unsigned int src = irqd_to_hwirq(d);
166 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
167 __clear_bit(src, ppc_cached_irq_mask);
168 __pmac_set_irq_mask(src, 1);
169 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
172 static void pmac_unmask_irq(struct irq_data *d)
175 unsigned int src = irqd_to_hwirq(d);
177 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
178 __set_bit(src, ppc_cached_irq_mask);
179 __pmac_set_irq_mask(src, 0);
180 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
183 static int pmac_retrigger(struct irq_data *d)
187 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
188 __pmac_retrigger(irqd_to_hwirq(d));
189 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
193 static struct irq_chip pmac_pic = {
195 .irq_startup = pmac_startup_irq,
196 .irq_mask = pmac_mask_irq,
197 .irq_ack = pmac_ack_irq,
198 .irq_mask_ack = pmac_mask_and_ack_irq,
199 .irq_unmask = pmac_unmask_irq,
200 .irq_retrigger = pmac_retrigger,
203 static irqreturn_t gatwick_action(int cpl, void *dev_id)
209 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
210 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
212 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
213 bits |= in_le32(&pmac_irq_hw[i]->level);
214 bits &= ppc_cached_irq_mask[i];
217 irq += __ilog2(bits);
218 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
219 generic_handle_irq(irq);
220 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
223 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
227 static unsigned int pmac_pic_get_irq(void)
230 unsigned long bits = 0;
233 #ifdef CONFIG_PPC_PMAC32_PSURGE
234 /* IPI's are a hack on the powersurge -- Cort */
235 if (smp_processor_id() != 0) {
236 return psurge_secondary_virq;
238 #endif /* CONFIG_PPC_PMAC32_PSURGE */
239 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
240 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
242 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
243 bits |= in_le32(&pmac_irq_hw[i]->level);
244 bits &= ppc_cached_irq_mask[i];
247 irq += __ilog2(bits);
250 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
251 if (unlikely(irq < 0))
253 return irq_linear_revmap(pmac_pic_host, irq);
256 static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
257 enum irq_domain_bus_token bus_token)
259 /* We match all, we don't always have a node anyway */
263 static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
269 /* Mark level interrupts, set delayed disable for edge ones and set
272 irq_set_status_flags(virq, IRQ_LEVEL);
273 irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
277 static const struct irq_domain_ops pmac_pic_host_ops = {
278 .match = pmac_pic_host_match,
279 .map = pmac_pic_host_map,
280 .xlate = irq_domain_xlate_onecell,
283 static void __init pmac_pic_probe_oldstyle(void)
286 struct device_node *master = NULL;
287 struct device_node *slave = NULL;
291 /* Set our get_irq function */
292 ppc_md.get_irq = pmac_pic_get_irq;
295 * Find the interrupt controller type & node
298 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
299 max_irqs = max_real_irqs = 32;
300 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
301 max_irqs = max_real_irqs = 32;
302 /* We might have a second cascaded ohare */
303 slave = of_find_node_by_name(NULL, "pci106b,7");
306 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
307 max_irqs = max_real_irqs = 64;
309 /* We might have a second cascaded heathrow */
311 /* Compensate for of_node_put() in of_find_node_by_name() */
313 slave = of_find_node_by_name(master, "mac-io");
315 /* Check ordering of master & slave */
316 if (of_device_is_compatible(master, "gatwick")) {
317 BUG_ON(slave == NULL);
321 /* We found a slave */
325 BUG_ON(master == NULL);
328 * Allocate an irq host
330 pmac_pic_host = irq_domain_add_linear(master, max_irqs,
331 &pmac_pic_host_ops, NULL);
332 BUG_ON(pmac_pic_host == NULL);
333 irq_set_default_host(pmac_pic_host);
335 /* Get addresses of first controller if we have a node for it */
336 BUG_ON(of_address_to_resource(master, 0, &r));
338 /* Map interrupts of primary controller */
339 addr = (u8 __iomem *) ioremap(r.start, 0x40);
341 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
343 if (max_real_irqs > 32)
344 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
348 printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
349 master, max_real_irqs);
351 /* Map interrupts of cascaded controller */
352 if (slave && !of_address_to_resource(slave, 0, &r)) {
353 addr = (u8 __iomem *)ioremap(r.start, 0x40);
354 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
358 (volatile struct pmac_irq_hw __iomem *)
360 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
362 printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
363 " cascade: %d\n", slave,
364 max_irqs - max_real_irqs, pmac_irq_cascade);
368 /* Disable all interrupts in all controllers */
369 for (i = 0; i * 32 < max_irqs; ++i)
370 out_le32(&pmac_irq_hw[i]->enable, 0);
372 /* Hookup cascade irq */
373 if (slave && pmac_irq_cascade) {
374 if (request_irq(pmac_irq_cascade, gatwick_action,
375 IRQF_NO_THREAD, "cascade", NULL))
376 pr_err("Failed to register cascade interrupt\n");
379 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
381 i = irq_create_mapping(NULL, 20);
382 if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL))
383 pr_err("Failed to register NMI-XMON interrupt\n");
387 int of_irq_parse_oldworld(const struct device_node *device, int index,
388 struct of_phandle_args *out_irq)
390 const u32 *ints = NULL;
394 * Old machines just have a list of interrupt numbers
395 * and no interrupt-controller nodes. We also have dodgy
396 * cases where the APPL,interrupts property is completely
397 * missing behind pci-pci bridges and we have to get it
398 * from the parent (the bridge itself, as apple just wired
399 * everything together on these)
402 ints = of_get_property(device, "AAPL,interrupts", &intlen);
405 device = device->parent;
406 if (!of_node_is_type(device, "pci"))
411 intlen /= sizeof(u32);
417 out_irq->args[0] = ints[index];
418 out_irq->args_count = 1;
422 #endif /* CONFIG_PPC32 */
424 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
426 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
427 struct device_node* pswitch;
430 pswitch = of_find_node_by_name(NULL, "programmer-switch");
432 nmi_irq = irq_of_parse_and_map(pswitch, 0);
434 mpic_irq_set_priority(nmi_irq, 9);
435 if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD,
437 pr_err("Failed to register NMI-XMON interrupt\n");
439 of_node_put(pswitch);
441 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
444 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
447 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
449 unsigned int flags = master ? 0 : MPIC_SECONDARY;
451 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
453 if (of_get_property(np, "big-endian", NULL))
454 flags |= MPIC_BIG_ENDIAN;
456 /* Primary Big Endian means HT interrupts. This is quite dodgy
457 * but works until I find a better way
459 if (master && (flags & MPIC_BIG_ENDIAN))
460 flags |= MPIC_U3_HT_IRQS;
462 mpic = mpic_alloc(np, 0, flags, 0, 0, name);
471 static int __init pmac_pic_probe_mpic(void)
473 struct mpic *mpic1, *mpic2;
474 struct device_node *np, *master = NULL, *slave = NULL;
476 /* We can have up to 2 MPICs cascaded */
477 for_each_node_by_type(np, "open-pic") {
478 if (master == NULL &&
479 of_get_property(np, "interrupts", NULL) == NULL)
480 master = of_node_get(np);
481 else if (slave == NULL)
482 slave = of_node_get(np);
483 if (master && slave) {
489 /* Check for bogus setups */
490 if (master == NULL && slave != NULL) {
495 /* Not found, default to good old pmac pic */
499 /* Set master handler */
500 ppc_md.get_irq = mpic_get_irq;
503 mpic1 = pmac_setup_one_mpic(master, 1);
504 BUG_ON(mpic1 == NULL);
506 /* Install NMI if any */
507 pmac_pic_setup_mpic_nmi(mpic1);
511 /* Set up a cascaded controller, if present */
513 mpic2 = pmac_setup_one_mpic(slave, 0);
515 printk(KERN_ERR "Failed to setup slave MPIC\n");
523 void __init pmac_pic_init(void)
525 /* We configure the OF parsing based on our oldworld vs. newworld
526 * platform type and whether we were booted by BootX.
530 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
531 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
532 of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
534 /* If we don't have phandles on a newworld, then try to locate a
535 * default interrupt controller (happens when booting with BootX).
536 * We do a first match here, hopefully, that only ever happens on
537 * machines with one controller.
539 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
540 struct device_node *np;
542 for_each_node_with_property(np, "interrupt-controller") {
543 /* Skip /chosen/interrupt-controller */
544 if (of_node_name_eq(np, "chosen"))
546 /* It seems like at least one person wants
547 * to use BootX on a machine with an AppleKiwi
548 * controller which happens to pretend to be an
549 * interrupt controller too. */
550 if (of_node_name_eq(np, "AppleKiwi"))
552 /* I think we found one ! */
553 of_irq_dflt_pic = np;
557 #endif /* CONFIG_PPC32 */
559 /* We first try to detect Apple's new Core99 chipset, since mac-io
560 * is quite different on those machines and contains an IBM MPIC2.
562 if (pmac_pic_probe_mpic() == 0)
566 pmac_pic_probe_oldstyle();
570 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
572 * These procedures are used in implementing sleep on the powerbooks.
573 * sleep_save_intrs() saves the states of all interrupt enables
574 * and disables all interrupts except for the nominated one.
575 * sleep_restore_intrs() restores the states of all interrupt enables.
577 unsigned long sleep_save_mask[2];
579 /* This used to be passed by the PMU driver but that link got
580 * broken with the new driver model. We use this tweak for now...
581 * We really want to do things differently though...
583 static int pmacpic_find_viaint(void)
587 #ifdef CONFIG_ADB_PMU
588 struct device_node *np;
590 if (pmu_get_model() != PMU_OHARE_BASED)
592 np = of_find_node_by_name(NULL, "via-pmu");
595 viaint = irq_of_parse_and_map(np, 0);
599 #endif /* CONFIG_ADB_PMU */
603 static int pmacpic_suspend(void)
605 int viaint = pmacpic_find_viaint();
607 sleep_save_mask[0] = ppc_cached_irq_mask[0];
608 sleep_save_mask[1] = ppc_cached_irq_mask[1];
609 ppc_cached_irq_mask[0] = 0;
610 ppc_cached_irq_mask[1] = 0;
612 set_bit(viaint, ppc_cached_irq_mask);
613 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
614 if (max_real_irqs > 32)
615 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
616 (void)in_le32(&pmac_irq_hw[0]->event);
617 /* make sure mask gets to controller before we return to caller */
619 (void)in_le32(&pmac_irq_hw[0]->enable);
624 static void pmacpic_resume(void)
628 out_le32(&pmac_irq_hw[0]->enable, 0);
629 if (max_real_irqs > 32)
630 out_le32(&pmac_irq_hw[1]->enable, 0);
632 for (i = 0; i < max_real_irqs; ++i)
633 if (test_bit(i, sleep_save_mask))
634 pmac_unmask_irq(irq_get_irq_data(i));
637 static struct syscore_ops pmacpic_syscore_ops = {
638 .suspend = pmacpic_suspend,
639 .resume = pmacpic_resume,
642 static int __init init_pmacpic_syscore(void)
645 register_syscore_ops(&pmacpic_syscore_ops);
649 machine_subsys_initcall(powermac, init_pmacpic_syscore);
651 #endif /* CONFIG_PM && CONFIG_PPC32 */