1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/types.h>
3 #include <linux/init.h>
4 #include <linux/delay.h>
5 #include <linux/kernel.h>
6 #include <linux/interrupt.h>
7 #include <linux/spinlock.h>
8 #include <linux/of_irq.h>
10 #include <asm/pmac_feature.h>
11 #include <asm/pmac_pfunc.h>
15 #define DBG(fmt...) printk(fmt)
20 static irqreturn_t macio_gpio_irq(int irq, void *data)
27 static int macio_do_gpio_irq_enable(struct pmf_function *func)
29 unsigned int irq = irq_of_parse_and_map(func->node, 0);
32 return request_irq(irq, macio_gpio_irq, 0, func->node->name, func);
35 static int macio_do_gpio_irq_disable(struct pmf_function *func)
37 unsigned int irq = irq_of_parse_and_map(func->node, 0);
44 static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
46 u8 __iomem *addr = (u8 __iomem *)func->driver_data;
51 if (args && args->count && !args->u[0].v)
55 raw_spin_lock_irqsave(&feature_lock, flags);
57 tmp = (tmp & ~mask) | (value & mask);
58 DBG("Do write 0x%02x to GPIO %pOF (%p)\n",
59 tmp, func->node, addr);
61 raw_spin_unlock_irqrestore(&feature_lock, flags);
66 static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor)
68 u8 __iomem *addr = (u8 __iomem *)func->driver_data;
71 /* Check if we have room for reply */
72 if (args == NULL || args->count == 0 || args->u[0].p == NULL)
76 *args->u[0].p = ((value & mask) >> rshift) ^ xor;
81 static int macio_do_delay(PMF_STD_ARGS, u32 duration)
83 /* assume we can sleep ! */
84 msleep((duration + 999) / 1000);
88 static struct pmf_handlers macio_gpio_handlers = {
89 .irq_enable = macio_do_gpio_irq_enable,
90 .irq_disable = macio_do_gpio_irq_disable,
91 .write_gpio = macio_do_gpio_write,
92 .read_gpio = macio_do_gpio_read,
93 .delay = macio_do_delay,
96 static void __init macio_gpio_init_one(struct macio_chip *macio)
98 struct device_node *gparent, *gp;
101 * Find the "gpio" parent node
104 for_each_child_of_node(macio->of_node, gparent)
105 if (of_node_name_eq(gparent, "gpio"))
110 DBG("Installing GPIO functions for macio %pOF\n",
114 * Ok, got one, we dont need anything special to track them down, so
115 * we just create them all
117 for_each_child_of_node(gparent, gp) {
118 const u32 *reg = of_get_property(gp, "reg", NULL);
119 unsigned long offset;
123 /* Deal with old style device-tree. We can safely hard code the
124 * offset for now too even if it's a bit gross ...
128 offset += (unsigned long)macio->base;
129 pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
132 DBG("Calling initial GPIO functions for macio %pOF\n",
135 /* And now we run all the init ones */
136 for_each_child_of_node(gparent, gp)
137 pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
139 /* Note: We do not at this point implement the "at sleep" or "at wake"
140 * functions. I yet to find any for GPIOs anyway
144 static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
146 struct macio_chip *macio = func->driver_data;
149 raw_spin_lock_irqsave(&feature_lock, flags);
150 MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask));
151 raw_spin_unlock_irqrestore(&feature_lock, flags);
155 static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset)
157 struct macio_chip *macio = func->driver_data;
159 /* Check if we have room for reply */
160 if (args == NULL || args->count == 0 || args->u[0].p == NULL)
163 *args->u[0].p = MACIO_IN32(offset);
167 static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
169 struct macio_chip *macio = func->driver_data;
172 raw_spin_lock_irqsave(&feature_lock, flags);
173 MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask));
174 raw_spin_unlock_irqrestore(&feature_lock, flags);
178 static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset)
180 struct macio_chip *macio = func->driver_data;
182 /* Check if we have room for reply */
183 if (args == NULL || args->count == 0 || args->u[0].p == NULL)
186 *((u8 *)(args->u[0].p)) = MACIO_IN8(offset);
190 static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
193 struct macio_chip *macio = func->driver_data;
195 /* Check if we have room for reply */
196 if (args == NULL || args->count == 0 || args->u[0].p == NULL)
199 *args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor;
203 static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
206 struct macio_chip *macio = func->driver_data;
208 /* Check if we have room for reply */
209 if (args == NULL || args->count == 0 || args->u[0].p == NULL)
212 *((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor;
216 static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
219 struct macio_chip *macio = func->driver_data;
224 if (args == NULL || args->count == 0)
227 raw_spin_lock_irqsave(&feature_lock, flags);
228 tmp = MACIO_IN32(offset);
229 val = args->u[0].v << shift;
230 tmp = (tmp & ~mask) | (val & mask);
231 MACIO_OUT32(offset, tmp);
232 raw_spin_unlock_irqrestore(&feature_lock, flags);
236 static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
239 struct macio_chip *macio = func->driver_data;
244 if (args == NULL || args->count == 0)
247 raw_spin_lock_irqsave(&feature_lock, flags);
248 tmp = MACIO_IN8(offset);
249 val = args->u[0].v << shift;
250 tmp = (tmp & ~mask) | (val & mask);
251 MACIO_OUT8(offset, tmp);
252 raw_spin_unlock_irqrestore(&feature_lock, flags);
256 static struct pmf_handlers macio_mmio_handlers = {
257 .write_reg32 = macio_do_write_reg32,
258 .read_reg32 = macio_do_read_reg32,
259 .write_reg8 = macio_do_write_reg8,
260 .read_reg8 = macio_do_read_reg8,
261 .read_reg32_msrx = macio_do_read_reg32_msrx,
262 .read_reg8_msrx = macio_do_read_reg8_msrx,
263 .write_reg32_slm = macio_do_write_reg32_slm,
264 .write_reg8_slm = macio_do_write_reg8_slm,
265 .delay = macio_do_delay,
268 static void __init macio_mmio_init_one(struct macio_chip *macio)
270 DBG("Installing MMIO functions for macio %pOF\n",
273 pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio);
276 static struct device_node *unin_hwclock;
278 static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
282 raw_spin_lock_irqsave(&feature_lock, flags);
283 /* This is fairly bogus in darwin, but it should work for our needs
284 * implemeted that way:
286 UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask));
287 raw_spin_unlock_irqrestore(&feature_lock, flags);
292 static struct pmf_handlers unin_mmio_handlers = {
293 .write_reg32 = unin_do_write_reg32,
294 .delay = macio_do_delay,
297 static void __init uninorth_install_pfunc(void)
299 struct device_node *np;
301 DBG("Installing functions for UniN %pOF\n",
305 * Install handlers for the bridge itself
307 pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL);
308 pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
312 * Install handlers for the hwclock child if any
314 for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;)
315 if (of_node_name_eq(np, "hw-clock")) {
320 DBG("Installing functions for UniN clock %pOF\n",
322 pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL);
323 pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT,
328 /* We export this as the SMP code might init us early */
329 int __init pmac_pfunc_base_install(void)
331 static int pfbase_inited;
338 if (!machine_is(powermac))
341 DBG("Installing base platform functions...\n");
344 * Locate mac-io chips and install handlers
346 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
347 if (macio_chips[i].of_node) {
348 macio_mmio_init_one(&macio_chips[i]);
349 macio_gpio_init_one(&macio_chips[i]);
354 * Install handlers for northbridge and direct mapped hwclock
355 * if any. We do not implement the config space access callback
356 * which is only ever used for functions that we do not call in
357 * the current driver (enabling/disabling cells in U2, mostly used
358 * to restore the PCI settings, we do that differently)
360 if (uninorth_node && uninorth_base)
361 uninorth_install_pfunc();
363 DBG("All base functions installed\n");
367 machine_arch_initcall(powermac, pmac_pfunc_base_install);
371 /* Those can be called by pmac_feature. Ultimately, I should use a sysdev
372 * or a device, but for now, that's good enough until I sort out some
373 * ordering issues. Also, we do not bother with GPIOs, as so far I yet have
374 * to see a case where a GPIO function has the on-suspend or on-resume bit
376 void pmac_pfunc_base_suspend(void)
380 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
381 if (macio_chips[i].of_node)
382 pmf_do_functions(macio_chips[i].of_node, NULL, 0,
383 PMF_FLAGS_ON_SLEEP, NULL);
386 pmf_do_functions(uninorth_node, NULL, 0,
387 PMF_FLAGS_ON_SLEEP, NULL);
389 pmf_do_functions(unin_hwclock, NULL, 0,
390 PMF_FLAGS_ON_SLEEP, NULL);
393 void pmac_pfunc_base_resume(void)
398 pmf_do_functions(unin_hwclock, NULL, 0,
399 PMF_FLAGS_ON_WAKE, NULL);
401 pmf_do_functions(uninorth_node, NULL, 0,
402 PMF_FLAGS_ON_WAKE, NULL);
403 for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
404 if (macio_chips[i].of_node)
405 pmf_do_functions(macio_chips[i].of_node, NULL, 0,
406 PMF_FLAGS_ON_WAKE, NULL);
410 #endif /* CONFIG_PM */