2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Authors: Kip Walker, PA Semi
5 * Olof Johansson, PA Semi
7 * Maintained by: Olof Johansson <olof@lixom.net>
9 * Based on arch/powerpc/platforms/maple/setup.c
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/errno.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/console.h>
29 #include <linux/export.h>
30 #include <linux/pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/gfp.h>
35 #include <asm/iommu.h>
36 #include <asm/machdep.h>
41 #include <asm/debug.h>
43 #include <pcmcia/ss.h>
44 #include <pcmcia/cistpl.h>
45 #include <pcmcia/ds.h>
49 /* SDC reset register, must be pre-mapped at reset time */
50 static void __iomem *reset_reg;
52 /* Various error status registers, must be pre-mapped at MCE time */
54 #define MAX_MCE_REGS 32
60 static struct mce_regs mce_regs[MAX_MCE_REGS];
61 static int num_mce_regs;
62 static int nmi_virq = 0;
65 static void __noreturn pas_restart(char *cmd)
67 /* Need to put others cpu in hold loop so they're not sleeping */
70 printk("Restarting...\n");
72 out_le32(reset_reg, 0x6000000);
76 static arch_spinlock_t timebase_lock;
77 static unsigned long timebase;
79 static void pas_give_timebase(void)
83 local_irq_save(flags);
85 arch_spin_lock(&timebase_lock);
86 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
89 arch_spin_unlock(&timebase_lock);
93 mtspr(SPRN_TBCTL, TBCTL_RESTART);
94 local_irq_restore(flags);
97 static void pas_take_timebase(void)
102 arch_spin_lock(&timebase_lock);
103 set_tb(timebase >> 32, timebase & 0xffffffff);
105 arch_spin_unlock(&timebase_lock);
108 static struct smp_ops_t pas_smp_ops = {
109 .probe = smp_mpic_probe,
110 .message_pass = smp_mpic_message_pass,
111 .kick_cpu = smp_generic_kick_cpu,
112 .setup_cpu = smp_mpic_setup_cpu,
113 .give_timebase = pas_give_timebase,
114 .take_timebase = pas_take_timebase,
116 #endif /* CONFIG_SMP */
118 static void __init pas_setup_arch(void)
121 /* Setup SMP callback */
122 smp_ops = &pas_smp_ops;
124 /* Lookup PCI hosts */
127 #ifdef CONFIG_DUMMY_CONSOLE
128 conswitchp = &dummy_con;
131 /* Remap SDC register for doing reset */
132 /* XXXOJN This should maybe come out of the device tree */
133 reset_reg = ioremap(0xfc101100, 4);
136 static int __init pas_setup_mce_regs(void)
141 /* Remap various SoC status registers for use by the MCE handler */
145 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
146 while (dev && reg < MAX_MCE_REGS) {
147 mce_regs[reg].name = kasprintf(GFP_KERNEL,
148 "mc%d_mcdebug_errsta", reg);
149 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
150 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
154 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
155 if (dev && reg+4 < MAX_MCE_REGS) {
156 mce_regs[reg].name = "iobdbg_IntStatus1";
157 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
159 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
160 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
162 mce_regs[reg].name = "iobiom_IntStatus";
163 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
165 mce_regs[reg].name = "iobiom_IntDbgReg";
166 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
170 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
171 if (dev && reg+2 < MAX_MCE_REGS) {
172 mce_regs[reg].name = "l2csts_IntStatus";
173 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
175 mce_regs[reg].name = "l2csts_Cnt";
176 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
184 machine_device_initcall(pasemi, pas_setup_mce_regs);
186 static __init void pas_init_IRQ(void)
188 struct device_node *np;
189 struct device_node *root, *mpic_node;
190 unsigned long openpic_addr;
191 const unsigned int *opprop;
194 const unsigned int *nmiprop;
199 for_each_node_by_type(np, "interrupt-controller")
200 if (of_device_is_compatible(np, "open-pic")) {
205 for_each_node_by_type(np, "open-pic") {
210 pr_err("Failed to locate the MPIC interrupt controller\n");
214 /* Find address list in /platform-open-pic */
215 root = of_find_node_by_path("/");
216 naddr = of_n_addr_cells(root);
217 opprop = of_get_property(root, "platform-open-pic", &opplen);
219 pr_err("No platform-open-pic property.\n");
223 openpic_addr = of_read_number(opprop, naddr);
224 pr_debug("OpenPIC addr: %lx\n", openpic_addr);
226 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;
228 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
230 mpic_flags |= MPIC_ENABLE_MCK;
232 mpic = mpic_alloc(mpic_node, openpic_addr,
233 mpic_flags, 0, 0, "PASEMI-OPIC");
236 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000);
238 /* The NMI/MCK source needs to be prio 15 */
240 nmi_virq = irq_create_mapping(NULL, *nmiprop);
241 mpic_irq_set_priority(nmi_virq, 15);
242 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
243 mpic_unmask_irq(irq_get_irq_data(nmi_virq));
246 of_node_put(mpic_node);
250 static void __init pas_progress(char *s, unsigned short hex)
252 printk("[%04x] : %s\n", hex, s ? s : "");
256 static int pas_machine_check_handler(struct pt_regs *regs)
258 int cpu = smp_processor_id();
259 unsigned long srr0, srr1, dsisr;
266 if (nmi_virq && mpic_get_mcirq() == nmi_virq) {
267 pr_err("NMI delivered\n");
269 mpic_end_irq(irq_get_irq_data(nmi_virq));
273 dsisr = mfspr(SPRN_DSISR);
274 pr_err("Machine Check on CPU %d\n", cpu);
275 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
276 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
277 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
278 mfspr(SPRN_PA6T_MER));
279 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
280 mfspr(SPRN_PA6T_DER));
284 pr_err("Signalled by SDC\n");
286 if (srr1 & 0x100000) {
287 pr_err("Load/Store detected error:\n");
289 pr_err("D-cache ECC double-bit error or bus error\n");
291 pr_err("LSU snoop response error\n");
292 if (dsisr & 0x2000) {
293 pr_err("MMU SLB multi-hit or invalid B field\n");
297 pr_err("Recoverable Duptags\n");
299 pr_err("Recoverable D-cache parity error count overflow\n");
301 pr_err("TLB parity error count overflow\n");
305 pr_err("Bus Error\n");
307 if (srr1 & 0x40000) {
308 pr_err("I-side SLB multiple hit\n");
313 pr_err("I-cache parity error hit\n");
315 if (num_mce_regs == 0)
316 pr_err("No MCE registers mapped yet, can't dump\n");
318 pr_err("SoC debug registers:\n");
320 for (i = 0; i < num_mce_regs; i++)
321 pr_err("%s: 0x%08x\n", mce_regs[i].name,
322 in_le32(mce_regs[i].addr));
328 pr_err("slb contents:\n");
329 for (i = 0; i < mmu_slb_size; i++) {
330 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
331 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
332 pr_err("%02d %016lx %016lx\n", i, e, v);
337 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
338 return !!(srr1 & 0x2);
342 static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
345 struct device *dev = data;
346 struct device *parent;
347 struct pcmcia_device *pdev = to_pcmcia_dev(dev);
349 /* We are only intereted in device addition */
350 if (action != BUS_NOTIFY_ADD_DEVICE)
353 parent = pdev->socket->dev.parent;
355 /* We know electra_cf devices will always have of_node set, since
356 * electra_cf is an of_platform driver.
358 if (!parent->of_node)
361 if (!of_device_is_compatible(parent->of_node, "electra-cf"))
364 /* We use the direct ops for localbus */
365 dev->dma_ops = &dma_nommu_ops;
370 static struct notifier_block pcmcia_notifier = {
371 .notifier_call = pcmcia_notify,
374 static inline void pasemi_pcmcia_init(void)
376 extern struct bus_type pcmcia_bus_type;
378 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
383 static inline void pasemi_pcmcia_init(void)
390 static const struct of_device_id pasemi_bus_ids[] = {
391 /* Unfortunately needed for legacy firmwares */
392 { .type = "localbus", },
394 /* These are the proper entries, which newer firmware uses */
395 { .compatible = "pasemi,localbus", },
396 { .compatible = "pasemi,sdc", },
400 static int __init pasemi_publish_devices(void)
402 pasemi_pcmcia_init();
404 /* Publish OF platform devices for SDC and other non-PCI devices */
405 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
409 machine_device_initcall(pasemi, pasemi_publish_devices);
413 * Called very early, MMU is off, device-tree isn't unflattened
415 static int __init pas_probe(void)
417 if (!of_machine_is_compatible("PA6T-1682M") &&
418 !of_machine_is_compatible("pasemi,pwrficient"))
421 iommu_init_early_pasemi();
426 define_machine(pasemi) {
427 .name = "PA Semi PWRficient",
429 .setup_arch = pas_setup_arch,
430 .init_IRQ = pas_init_IRQ,
431 .get_irq = mpic_get_irq,
432 .restart = pas_restart,
433 .get_boot_time = pas_get_boot_time,
434 .calibrate_decr = generic_calibrate_decr,
435 .progress = pas_progress,
436 .machine_check_exception = pas_machine_check_handler,