1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/irq.h>
16 #include <asm/sections.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/machdep.h>
21 #include <asm/iommu.h>
22 #include <asm/ppc-pci.h>
23 #include <asm/isa-bridge.h>
28 #define DBG(x...) printk(x)
33 static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
35 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
37 for (; node; node = node->sibling) {
39 const unsigned int *class_code;
42 /* For PCI<->PCI bridges or CardBus bridges, we go down */
43 class_code = of_get_property(node, "class-code", NULL);
44 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
45 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
47 bus_range = of_get_property(node, "bus-range", &len);
48 if (bus_range != NULL && len > 2 * sizeof(int)) {
49 if (bus_range[1] > higher)
50 higher = bus_range[1];
52 higher = fixup_one_level_bus_range(node->child, higher);
57 /* This routine fixes the "bus-range" property of all bridges in the
58 * system since they tend to have their "last" member wrong on macs
60 * Note that the bus numbers manipulated here are OF bus numbers, they
61 * are not Linux bus numbers.
63 static void __init fixup_bus_range(struct device_node *bridge)
66 struct property *prop;
69 /* Lookup the "bus-range" property for the hose */
70 prop = of_find_property(bridge, "bus-range", &len);
71 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) {
72 printk(KERN_WARNING "Can't get bus-range for %pOF\n",
76 bus_range = prop->value;
77 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
81 static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
83 return (1 << (unsigned long)PCI_SLOT(devfn)) |
84 ((unsigned long)PCI_FUNC(devfn) << 8) |
85 ((unsigned long)off & 0xFCUL);
88 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
90 return ((unsigned long)bus << 16) |
91 ((unsigned long)devfn << 8) |
92 ((unsigned long)off & 0xFCUL) |
96 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
97 u8 bus, u8 dev_fn, u8 offset)
101 if (bus == hose->first_busno) {
102 if (dev_fn < (11 << 3))
104 caddr = u3_agp_cfa0(dev_fn, offset);
106 caddr = u3_agp_cfa1(bus, dev_fn, offset);
108 /* Uninorth will return garbage if we don't read back the value ! */
110 out_le32(hose->cfg_addr, caddr);
111 } while (in_le32(hose->cfg_addr) != caddr);
114 return hose->cfg_data + offset;
117 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
118 int offset, int len, u32 *val)
120 struct pci_controller *hose;
121 volatile void __iomem *addr;
123 hose = pci_bus_to_host(bus);
125 return PCIBIOS_DEVICE_NOT_FOUND;
127 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
129 return PCIBIOS_DEVICE_NOT_FOUND;
131 * Note: the caller has already checked that offset is
132 * suitably aligned and that len is 1, 2 or 4.
139 *val = in_le16(addr);
142 *val = in_le32(addr);
145 return PCIBIOS_SUCCESSFUL;
148 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
149 int offset, int len, u32 val)
151 struct pci_controller *hose;
152 volatile void __iomem *addr;
154 hose = pci_bus_to_host(bus);
156 return PCIBIOS_DEVICE_NOT_FOUND;
158 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
160 return PCIBIOS_DEVICE_NOT_FOUND;
162 * Note: the caller has already checked that offset is
163 * suitably aligned and that len is 1, 2 or 4.
176 return PCIBIOS_SUCCESSFUL;
179 static struct pci_ops u3_agp_pci_ops =
181 .read = u3_agp_read_config,
182 .write = u3_agp_write_config,
185 static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
187 return (devfn << 8) | off;
190 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
192 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
195 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
196 u8 bus, u8 devfn, u8 offset)
198 if (bus == hose->first_busno) {
199 if (PCI_SLOT(devfn) == 0)
201 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
203 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
206 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
209 volatile void __iomem *addr;
211 addr = hose->cfg_addr;
212 addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
219 *val = in_be16(addr);
222 *val = in_be32(addr);
226 return PCIBIOS_SUCCESSFUL;
229 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
232 volatile void __iomem *addr;
234 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
236 if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
237 return PCIBIOS_SUCCESSFUL;
251 return PCIBIOS_SUCCESSFUL;
254 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
255 int offset, int len, u32 *val)
257 struct pci_controller *hose;
258 volatile void __iomem *addr;
260 hose = pci_bus_to_host(bus);
262 return PCIBIOS_DEVICE_NOT_FOUND;
264 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
265 return u3_ht_root_read_config(hose, offset, len, val);
268 return PCIBIOS_BAD_REGISTER_NUMBER;
270 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
272 return PCIBIOS_DEVICE_NOT_FOUND;
275 * Note: the caller has already checked that offset is
276 * suitably aligned and that len is 1, 2 or 4.
283 *val = in_le16(addr);
286 *val = in_le32(addr);
289 return PCIBIOS_SUCCESSFUL;
292 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
293 int offset, int len, u32 val)
295 struct pci_controller *hose;
296 volatile void __iomem *addr;
298 hose = pci_bus_to_host(bus);
300 return PCIBIOS_DEVICE_NOT_FOUND;
302 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
303 return u3_ht_root_write_config(hose, offset, len, val);
306 return PCIBIOS_BAD_REGISTER_NUMBER;
308 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
310 return PCIBIOS_DEVICE_NOT_FOUND;
312 * Note: the caller has already checked that offset is
313 * suitably aligned and that len is 1, 2 or 4.
326 return PCIBIOS_SUCCESSFUL;
329 static struct pci_ops u3_ht_pci_ops =
331 .read = u3_ht_read_config,
332 .write = u3_ht_write_config,
335 static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
337 return (1 << PCI_SLOT(devfn)) |
338 (PCI_FUNC(devfn) << 8) |
343 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
352 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
353 u8 bus, u8 dev_fn, int offset)
357 if (bus == hose->first_busno)
358 caddr = u4_pcie_cfa0(dev_fn, offset);
360 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
362 /* Uninorth will return garbage if we don't read back the value ! */
364 out_le32(hose->cfg_addr, caddr);
365 } while (in_le32(hose->cfg_addr) != caddr);
368 return hose->cfg_data + offset;
371 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
372 int offset, int len, u32 *val)
374 struct pci_controller *hose;
375 volatile void __iomem *addr;
377 hose = pci_bus_to_host(bus);
379 return PCIBIOS_DEVICE_NOT_FOUND;
380 if (offset >= 0x1000)
381 return PCIBIOS_BAD_REGISTER_NUMBER;
382 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
384 return PCIBIOS_DEVICE_NOT_FOUND;
386 * Note: the caller has already checked that offset is
387 * suitably aligned and that len is 1, 2 or 4.
394 *val = in_le16(addr);
397 *val = in_le32(addr);
400 return PCIBIOS_SUCCESSFUL;
402 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
403 int offset, int len, u32 val)
405 struct pci_controller *hose;
406 volatile void __iomem *addr;
408 hose = pci_bus_to_host(bus);
410 return PCIBIOS_DEVICE_NOT_FOUND;
411 if (offset >= 0x1000)
412 return PCIBIOS_BAD_REGISTER_NUMBER;
413 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
415 return PCIBIOS_DEVICE_NOT_FOUND;
417 * Note: the caller has already checked that offset is
418 * suitably aligned and that len is 1, 2 or 4.
431 return PCIBIOS_SUCCESSFUL;
434 static struct pci_ops u4_pcie_pci_ops =
436 .read = u4_pcie_read_config,
437 .write = u4_pcie_write_config,
440 static void __init setup_u3_agp(struct pci_controller* hose)
442 /* On G5, we move AGP up to high bus number so we don't need
443 * to reassign bus numbers for HT. If we ever have P2P bridges
444 * on AGP, we'll have to move pci_assign_all_buses to the
445 * pci_controller structure so we enable it for AGP and not for
447 * We hard code the address because of the different size of
448 * the reg address cell, we shall fix that by killing struct
449 * reg_property and using some accessor functions instead
451 hose->first_busno = 0xf0;
452 hose->last_busno = 0xff;
453 hose->ops = &u3_agp_pci_ops;
454 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
455 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
460 static void __init setup_u4_pcie(struct pci_controller* hose)
462 /* We currently only implement the "non-atomic" config space, to
463 * be optimised later.
465 hose->ops = &u4_pcie_pci_ops;
466 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
467 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
472 static void __init setup_u3_ht(struct pci_controller* hose)
474 hose->ops = &u3_ht_pci_ops;
476 /* We hard code the address because of the different size of
477 * the reg address cell, we shall fix that by killing struct
478 * reg_property and using some accessor functions instead
480 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
481 hose->cfg_addr = ioremap(0xf8070000, 0x1000);
483 hose->first_busno = 0;
484 hose->last_busno = 0xef;
489 static int __init maple_add_bridge(struct device_node *dev)
492 struct pci_controller *hose;
494 const int *bus_range;
497 DBG("Adding PCI host bridge %pOF\n", dev);
499 bus_range = of_get_property(dev, "bus-range", &len);
500 if (bus_range == NULL || len < 2 * sizeof(int)) {
501 printk(KERN_WARNING "Can't get bus-range for %pOF, assume bus 0\n",
505 hose = pcibios_alloc_controller(dev);
508 hose->first_busno = bus_range ? bus_range[0] : 0;
509 hose->last_busno = bus_range ? bus_range[1] : 0xff;
510 hose->controller_ops = maple_pci_controller_ops;
513 if (of_device_is_compatible(dev, "u3-agp")) {
515 disp_name = "U3-AGP";
517 } else if (of_device_is_compatible(dev, "u3-ht")) {
521 } else if (of_device_is_compatible(dev, "u4-pcie")) {
523 disp_name = "U4-PCIE";
526 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
527 disp_name, hose->first_busno, hose->last_busno);
529 /* Interpret the "ranges" property */
530 /* This also maps the I/O region and sets isa_io/mem_base */
531 pci_process_bridge_OF_ranges(hose, dev, primary);
533 /* Fixup "bus-range" OF property */
534 fixup_bus_range(dev);
536 /* Check for legacy IOs */
537 isa_bridge_find_early(hose);
539 /* create pci_dn's for DT nodes under this PHB */
540 pci_devs_phb_init_dynamic(hose);
546 void maple_pci_irq_fixup(struct pci_dev *dev)
548 DBG(" -> maple_pci_irq_fixup\n");
550 /* Fixup IRQ for PCIe host */
551 if (u4_pcie != NULL && dev->bus->number == 0 &&
552 pci_bus_to_host(dev->bus) == u4_pcie) {
553 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
554 dev->irq = irq_create_mapping(NULL, 1);
556 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
559 /* Hide AMD8111 IDE interrupt when in legacy mode so
560 * the driver calls pci_get_legacy_ide_irq()
562 if (dev->vendor == PCI_VENDOR_ID_AMD &&
563 dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
564 (dev->class & 5) != 5) {
568 DBG(" <- maple_pci_irq_fixup\n");
571 static int maple_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
573 struct pci_controller *hose = pci_bus_to_host(bridge->bus);
574 struct device_node *np, *child;
579 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
580 * assume there is no P2P bridge on the AGP bus, which should be a
581 * safe assumptions hopefully.
584 PCI_DN(np)->busno = 0xf0;
585 for_each_child_of_node(np, child)
586 PCI_DN(child)->busno = 0xf0;
591 void __init maple_pci_init(void)
593 struct device_node *np, *root;
594 struct device_node *ht = NULL;
596 /* Probe root PCI hosts, that is on U3 the AGP host and the
597 * HyperTransport host. That one is actually "kept" around
598 * and actually added last as it's resource management relies
599 * on the AGP resources to have been setup first
601 root = of_find_node_by_path("/");
603 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
606 for_each_child_of_node(root, np) {
607 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "ht"))
609 if ((of_device_is_compatible(np, "u4-pcie") ||
610 of_device_is_compatible(np, "u3-agp")) &&
611 maple_add_bridge(np) == 0)
614 if (of_device_is_compatible(np, "u3-ht")) {
621 /* Now setup the HyperTransport host if we found any
623 if (ht && maple_add_bridge(ht) != 0)
626 ppc_md.pcibios_root_bridge_prepare = maple_pci_root_bridge_prepare;
628 /* Tell pci.c to not change any resource allocations. */
629 pci_add_flags(PCI_PROBE_ONLY);
632 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
634 struct device_node *np;
635 unsigned int defirq = channel ? 15 : 14;
638 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
639 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
642 np = pci_device_to_OF_node(pdev);
644 printk("Failed to locate OF node for IDE %s\n",
648 irq = irq_of_parse_and_map(np, channel & 0x1);
650 printk("Failed to map onboard IDE interrupt for channel %d\n",
657 static void quirk_ipr_msi(struct pci_dev *dev)
659 /* Something prevents MSIs from the IPR from working on Bimini,
660 * and the driver has no smarts to recover. So disable MSI
663 if (machine_is(maple)) {
665 dev_info(&dev->dev, "Quirk disabled MSI\n");
668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
671 struct pci_controller_ops maple_pci_controller_ops = {