2 * CBE Pervasive Monitor and Debug
4 * (C) Copyright IBM Corporation 2005
6 * Authors: Maximino Aguilar (maguilar@us.ibm.com)
7 * Michael N. Day (mnday@us.ibm.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/percpu.h>
29 #include <linux/types.h>
30 #include <linux/kallsyms.h>
33 #include <asm/machdep.h>
35 #include <asm/pgtable.h>
37 #include <asm/cell-regs.h>
38 #include <asm/cpu_has_feature.h>
40 #include "pervasive.h"
42 static void cbe_power_save(void)
44 unsigned long ctrl, thread_switch_control;
46 /* Ensure our interrupt state is properly tracked */
47 if (!prep_irq_for_idle())
50 ctrl = mfspr(SPRN_CTRLF);
52 /* Enable DEC and EE interrupt request */
53 thread_switch_control = mfspr(SPRN_TSC_CELL);
54 thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
56 switch (ctrl & CTRL_CT) {
58 thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
61 thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
64 printk(KERN_WARNING "%s: unknown configuration\n",
68 mtspr(SPRN_TSC_CELL, thread_switch_control);
71 * go into low thread priority, medium priority will be
72 * restored for us after wake-up.
77 * atomically disable thread execution and runlatch.
78 * External and Decrementer exceptions are still handled when the
79 * thread is disabled but now enter in cbe_system_reset_exception()
81 ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
82 mtspr(SPRN_CTRLT, ctrl);
84 /* Re-enable interrupts in MSR */
88 static int cbe_system_reset_exception(struct pt_regs *regs)
90 switch (regs->msr & SRR1_WAKEMASK) {
96 * Handle these when interrupts get re-enabled and we take
97 * them as regular exceptions. We are in an NMI context
98 * and can't handle these here.
102 return cbe_sysreset_hack();
103 #ifdef CONFIG_CBE_RAS
104 case SRR1_WAKESYSERR:
105 cbe_system_error_exception(regs);
108 cbe_thermal_exception(regs);
110 #endif /* CONFIG_CBE_RAS */
112 /* do system reset */
115 /* everything handled */
119 void __init cbe_pervasive_init(void)
123 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
126 for_each_possible_cpu(cpu) {
127 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
131 /* Enable Pause(0) control bit */
132 out_be64(®s->pmcr, in_be64(®s->pmcr) |
133 CBE_PMD_PAUSE_ZERO_CONTROL);
136 ppc_md.power_save = cbe_power_save;
137 ppc_md.system_reset_exception = cbe_system_reset_exception;