1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * CBE Pervasive Monitor and Debug
5 * (C) Copyright IBM Corporation 2005
7 * Authors: Maximino Aguilar (maguilar@us.ibm.com)
8 * Michael N. Day (mnday@us.ibm.com)
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/percpu.h>
16 #include <linux/types.h>
17 #include <linux/kallsyms.h>
18 #include <linux/pgtable.h>
21 #include <asm/machdep.h>
24 #include <asm/cell-regs.h>
25 #include <asm/cpu_has_feature.h>
27 #include "pervasive.h"
29 static void cbe_power_save(void)
31 unsigned long ctrl, thread_switch_control;
33 /* Ensure our interrupt state is properly tracked */
34 if (!prep_irq_for_idle())
37 ctrl = mfspr(SPRN_CTRLF);
39 /* Enable DEC and EE interrupt request */
40 thread_switch_control = mfspr(SPRN_TSC_CELL);
41 thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
43 switch (ctrl & CTRL_CT) {
45 thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
48 thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
51 printk(KERN_WARNING "%s: unknown configuration\n",
55 mtspr(SPRN_TSC_CELL, thread_switch_control);
58 * go into low thread priority, medium priority will be
59 * restored for us after wake-up.
64 * atomically disable thread execution and runlatch.
65 * External and Decrementer exceptions are still handled when the
66 * thread is disabled but now enter in cbe_system_reset_exception()
68 ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
69 mtspr(SPRN_CTRLT, ctrl);
71 /* Re-enable interrupts in MSR */
75 static int cbe_system_reset_exception(struct pt_regs *regs)
77 switch (regs->msr & SRR1_WAKEMASK) {
83 * Handle these when interrupts get re-enabled and we take
84 * them as regular exceptions. We are in an NMI context
85 * and can't handle these here.
89 return cbe_sysreset_hack();
92 cbe_system_error_exception(regs);
95 cbe_thermal_exception(regs);
97 #endif /* CONFIG_CBE_RAS */
102 /* everything handled */
106 void __init cbe_pervasive_init(void)
110 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
113 for_each_possible_cpu(cpu) {
114 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
118 /* Enable Pause(0) control bit */
119 out_be64(®s->pmcr, in_be64(®s->pmcr) |
120 CBE_PMD_PAUSE_ZERO_CONTROL);
123 ppc_md.power_save = cbe_power_save;
124 ppc_md.system_reset_exception = cbe_system_reset_exception;