2 * Copyright 2007, Michael Ellerman, IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/msi.h>
16 #include <linux/export.h>
17 #include <linux/of_platform.h>
18 #include <linux/slab.h>
20 #include <asm/debugfs.h>
22 #include <asm/machdep.h>
28 * MSIC registers, specified as offsets from dcr_base
30 #define MSIC_CTRL_REG 0x0
32 /* Base Address registers specify FIFO location in BE memory */
33 #define MSIC_BASE_ADDR_HI_REG 0x3
34 #define MSIC_BASE_ADDR_LO_REG 0x4
36 /* Hold the read/write offsets into the FIFO */
37 #define MSIC_READ_OFFSET_REG 0x5
38 #define MSIC_WRITE_OFFSET_REG 0x6
41 /* MSIC control register flags */
42 #define MSIC_CTRL_ENABLE 0x0001
43 #define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
44 #define MSIC_CTRL_IRQ_ENABLE 0x0008
45 #define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
48 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
49 * Currently we're using a 64KB FIFO size.
51 #define MSIC_FIFO_SIZE_SHIFT 16
52 #define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
55 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
56 * 8-9 of the MSIC control reg.
58 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
61 * We need to mask the read/write offsets to make sure they stay within
62 * the bounds of the FIFO. Also they should always be 16-byte aligned.
64 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
66 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
67 #define MSIC_FIFO_ENTRY_SIZE 0x10
71 struct irq_domain *irq_domain;
82 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
84 static inline void axon_msi_debug_setup(struct device_node *dn,
85 struct axon_msic *msic) { }
89 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
91 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
93 dcr_write(msic->dcr_host, dcr_n, val);
96 static void axon_msi_cascade(struct irq_desc *desc)
98 struct irq_chip *chip = irq_desc_get_chip(desc);
99 struct axon_msic *msic = irq_desc_get_handler_data(desc);
100 u32 write_offset, msi;
104 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
105 pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
107 /* write_offset doesn't wrap properly, so we have to mask it */
108 write_offset &= MSIC_FIFO_SIZE_MASK;
110 while (msic->read_offset != write_offset && retry < 100) {
111 idx = msic->read_offset / sizeof(__le32);
112 msi = le32_to_cpu(msic->fifo_virt[idx]);
115 pr_devel("axon_msi: woff %x roff %x msi %x\n",
116 write_offset, msic->read_offset, msi);
118 if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
119 generic_handle_irq(msi);
120 msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
123 * Reading the MSIC_WRITE_OFFSET_REG does not
124 * reliably flush the outstanding DMA to the
125 * FIFO buffer. Here we were reading stale
126 * data, so we need to retry.
130 pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
135 pr_devel("axon_msi: late irq 0x%x, retry %d\n",
140 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
141 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
145 printk(KERN_WARNING "axon_msi: irq timed out\n");
147 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
148 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
151 chip->irq_eoi(&desc->irq_data);
154 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
156 struct irq_domain *irq_domain;
157 struct device_node *dn, *tmp;
159 struct axon_msic *msic = NULL;
161 dn = of_node_get(pci_device_to_OF_node(dev));
163 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
167 for (; dn; dn = of_get_next_parent(dn)) {
168 ph = of_get_property(dn, "msi-translator", NULL);
175 "axon_msi: no msi-translator property found\n");
180 dn = of_find_node_by_phandle(*ph);
184 "axon_msi: msi-translator doesn't point to a node\n");
188 irq_domain = irq_find_host(dn);
190 dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %pOF\n",
195 msic = irq_domain->host_data;
203 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
205 struct device_node *dn;
206 struct msi_desc *entry;
210 dn = of_node_get(pci_device_to_OF_node(dev));
212 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
216 entry = first_pci_msi_entry(dev);
218 for (; dn; dn = of_get_next_parent(dn)) {
219 if (entry->msi_attrib.is_64) {
220 prop = of_get_property(dn, "msi-address-64", &len);
225 prop = of_get_property(dn, "msi-address-32", &len);
232 "axon_msi: no msi-address-(32|64) properties found\n");
239 msg->address_hi = prop[0];
240 msg->address_lo = prop[1];
244 msg->address_lo = prop[0];
248 "axon_msi: malformed msi-address-(32|64) property\n");
258 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
260 unsigned int virq, rc;
261 struct msi_desc *entry;
263 struct axon_msic *msic;
265 msic = find_msi_translator(dev);
269 rc = setup_msi_msg_address(dev, &msg);
273 for_each_pci_msi_entry(entry, dev) {
274 virq = irq_create_direct_mapping(msic->irq_domain);
277 "axon_msi: virq allocation failed!\n");
280 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
282 irq_set_msi_desc(virq, entry);
284 pci_write_msi_msg(virq, &msg);
290 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
292 struct msi_desc *entry;
294 dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
296 for_each_pci_msi_entry(entry, dev) {
300 irq_set_msi_desc(entry->irq, NULL);
301 irq_dispose_mapping(entry->irq);
305 static struct irq_chip msic_irq_chip = {
306 .irq_mask = pci_msi_mask_irq,
307 .irq_unmask = pci_msi_unmask_irq,
308 .irq_shutdown = pci_msi_mask_irq,
312 static int msic_host_map(struct irq_domain *h, unsigned int virq,
315 irq_set_chip_data(virq, h->host_data);
316 irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
321 static const struct irq_domain_ops msic_host_ops = {
322 .map = msic_host_map,
325 static void axon_msi_shutdown(struct platform_device *device)
327 struct axon_msic *msic = dev_get_drvdata(&device->dev);
330 pr_devel("axon_msi: disabling %pOF\n",
331 irq_domain_get_of_node(msic->irq_domain));
332 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
333 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
334 msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
337 static int axon_msi_probe(struct platform_device *device)
339 struct device_node *dn = device->dev.of_node;
340 struct axon_msic *msic;
342 int dcr_base, dcr_len;
344 pr_devel("axon_msi: setting up dn %pOF\n", dn);
346 msic = kzalloc(sizeof(*msic), GFP_KERNEL);
348 printk(KERN_ERR "axon_msi: couldn't allocate msic for %pOF\n",
353 dcr_base = dcr_resource_start(dn, 0);
354 dcr_len = dcr_resource_len(dn, 0);
356 if (dcr_base == 0 || dcr_len == 0) {
358 "axon_msi: couldn't parse dcr properties on %pOF\n",
363 msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
364 if (!DCR_MAP_OK(msic->dcr_host)) {
365 printk(KERN_ERR "axon_msi: dcr_map failed for %pOF\n",
370 msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
371 &msic->fifo_phys, GFP_KERNEL);
372 if (!msic->fifo_virt) {
373 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %pOF\n",
378 virq = irq_of_parse_and_map(dn, 0);
380 printk(KERN_ERR "axon_msi: irq parse and map failed for %pOF\n",
384 memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
386 /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
387 msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
388 if (!msic->irq_domain) {
389 printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %pOF\n",
394 irq_set_handler_data(virq, msic);
395 irq_set_chained_handler(virq, axon_msi_cascade);
396 pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
398 /* Enable the MSIC hardware */
399 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
400 msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
401 msic->fifo_phys & 0xFFFFFFFF);
402 msic_dcr_write(msic, MSIC_CTRL_REG,
403 MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
404 MSIC_CTRL_FIFO_SIZE);
406 msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
407 & MSIC_FIFO_SIZE_MASK;
409 dev_set_drvdata(&device->dev, msic);
411 cell_pci_controller_ops.setup_msi_irqs = axon_msi_setup_msi_irqs;
412 cell_pci_controller_ops.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
414 axon_msi_debug_setup(dn, msic);
416 printk(KERN_DEBUG "axon_msi: setup MSIC on %pOF\n", dn);
421 dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
430 static const struct of_device_id axon_msi_device_id[] = {
432 .compatible = "ibm,axon-msic"
437 static struct platform_driver axon_msi_driver = {
438 .probe = axon_msi_probe,
439 .shutdown = axon_msi_shutdown,
442 .of_match_table = axon_msi_device_id,
446 static int __init axon_msi_init(void)
448 return platform_driver_register(&axon_msi_driver);
450 subsys_initcall(axon_msi_init);
454 static int msic_set(void *data, u64 val)
456 struct axon_msic *msic = data;
457 out_le32(msic->trigger, val);
461 static int msic_get(void *data, u64 *val)
467 DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
469 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
474 addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
475 if (addr == OF_BAD_ADDR) {
476 pr_devel("axon_msi: couldn't translate reg property\n");
480 msic->trigger = ioremap(addr, 0x4);
481 if (!msic->trigger) {
482 pr_devel("axon_msi: ioremap failed\n");
486 snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
488 if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
490 pr_devel("axon_msi: debugfs_create_file failed!\n");