1 # SPDX-License-Identifier: GPL-2.0
2 menu "Platform support"
4 source "arch/powerpc/platforms/powernv/Kconfig"
5 source "arch/powerpc/platforms/pseries/Kconfig"
6 source "arch/powerpc/platforms/chrp/Kconfig"
7 source "arch/powerpc/platforms/512x/Kconfig"
8 source "arch/powerpc/platforms/52xx/Kconfig"
9 source "arch/powerpc/platforms/powermac/Kconfig"
10 source "arch/powerpc/platforms/maple/Kconfig"
11 source "arch/powerpc/platforms/pasemi/Kconfig"
12 source "arch/powerpc/platforms/ps3/Kconfig"
13 source "arch/powerpc/platforms/cell/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
19 source "arch/powerpc/platforms/embedded6xx/Kconfig"
20 source "arch/powerpc/platforms/44x/Kconfig"
21 source "arch/powerpc/platforms/40x/Kconfig"
22 source "arch/powerpc/platforms/amigaone/Kconfig"
25 bool "KVM Guest support"
28 This option enables various optimizations for running under the KVM
29 hypervisor. Overhead for the kernel when not running inside KVM should
32 In case of doubt, say Y
35 bool "ePAPR para-virtualization support"
37 Enables ePAPR para-virtualization support for guests.
39 In case of doubt, say Y
43 depends on PPC_BOOK3S_32 || PPC64
45 Support for running natively on the hardware, i.e. without
46 a hypervisor. This option is not user-selectable but should
47 be selected by all platforms that need it.
49 config PPC_OF_BOOT_TRAMPOLINE
50 bool "Support booting from Open Firmware or yaboot"
51 depends on PPC_BOOK3S_32 || PPC64
54 Support from booting from Open Firmware or yaboot using an
55 Open Firmware client interface. This enables the kernel to
56 communicate with open firmware to retrieve system information
57 such as the device tree.
59 In case of doubt, say Y
61 config PPC_DT_CPU_FTRS
62 bool "Device-tree based CPU feature discovery & setup"
63 depends on PPC_BOOK3S_64
66 This enables code to use a new device tree binding for describing CPU
67 compatibility and features. Saying Y here will attempt to use the new
68 binding if the firmware provides it. Currently only the skiboot
69 firmware provides this binding.
70 If you're not sure say Y.
72 config UDBG_RTAS_CONSOLE
73 bool "RTAS based debug console"
76 config PPC_SMP_MUXED_IPI
79 Select this option if your platform supports SMP and your
80 interrupt controller provides less than 4 interrupts to each
81 cpu. This will enable the generic code to multiplex the 4
82 messages on to one ipi.
91 bool "MPIC Global Timer"
92 depends on MPIC && FSL_SOC
94 The MPIC global timer is a hardware timer inside the
95 Freescale PIC complying with OpenPIC standard. When the
96 specified interval times out, the hardware timer generates
97 an interrupt. The driver currently is only tested on fsl
98 chip, but it can potentially support other global timers
99 complying with the OpenPIC standard.
101 config FSL_MPIC_TIMER_WAKEUP
102 tristate "Freescale MPIC global timer wakeup driver"
103 depends on FSL_SOC && MPIC_TIMER && PM
105 The driver provides a way to wake up the system by MPIC
107 e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
109 config PPC_EPAPR_HV_PIC
111 select EPAPR_PARAVIRT
117 bool "MPIC message register support"
120 Enables support for the MPIC message registers. These
121 registers are used for inter-processor communication.
133 config RTAS_ERROR_LOGGING
137 config PPC_RTAS_DAEMON
142 bool "Proc interface to RTAS"
143 depends on PPC_RTAS && PROC_FS
147 tristate "Firmware flash interface"
148 depends on PPC64 && RTAS_PROC
153 config MPIC_U3_HT_IRQS
156 config MPIC_BROKEN_REGREAD
160 This option enables a MPIC driver workaround for some chips
161 that have a bug that causes some interrupt source information
162 to not read back properly. It is safe to use on other chips as
163 well, but enabling it uses about 8KB of memory to keep copies
164 of the register contents in software.
168 depends on (PPC_POWERNV || PPC_PSERIES) && PCI
180 config PPC_INDIRECT_PIO
184 config PPC_INDIRECT_MMIO
187 config PPC_IO_WORKAROUNDS
190 source "drivers/cpufreq/Kconfig"
192 menu "CPUIdle driver"
194 source "drivers/cpuidle/Kconfig"
198 config PPC601_SYNC_FIX
199 bool "Workarounds for PPC601 bugs"
200 depends on PPC_BOOK3S_601 && PPC_PMAC
203 Some versions of the PPC601 (the first PowerPC chip) have bugs which
204 mean that extra synchronization instructions are required near
205 certain instructions, typically those that make major changes to the
206 CPU state. These extra instructions reduce performance slightly.
207 If you say N here, these extra instructions will not be included,
208 resulting in a kernel which will run faster but may not run at all
209 on some systems with the PPC601 chip.
211 If in doubt, say Y here.
214 bool "On-chip CPU temperature sensor support"
215 depends on PPC_BOOK3S_32
217 G3 and G4 processors have an on-chip temperature sensor called the
218 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
219 temperature within 2-4 degrees Celsius. This option shows the current
220 on-die temperature in /proc/cpuinfo if the cpu supports it.
222 Unfortunately, this sensor is very inaccurate when uncalibrated, so
223 don't assume the cpu temp is actually what /proc/cpuinfo says it is.
226 bool "Interrupt driven TAU driver (EXPERIMENTAL)"
229 The TAU supports an interrupt driven mode which causes an interrupt
230 whenever the temperature goes out of range. This is the fastest way
231 to get notified the temp has exceeded a range. With this option off,
232 a timer is used to re-check the temperature periodically.
234 If in doubt, say N here.
237 bool "Average high and low temp"
240 The TAU hardware can compare the temperature to an upper and lower
241 bound. The default behavior is to show both the upper and lower
242 bound in /proc/cpuinfo. If the range is large, the temperature is
243 either changing a lot, or the TAU hardware is broken (likely on some
244 G4's). If the range is small (around 4 degrees), the temperature is
245 relatively stable. If you say Y here, a single temperature value,
246 halfway between the upper and lower bounds, will be reported in
249 If in doubt, say N here.
252 bool "QE GPIO support"
253 depends on QUICC_ENGINE
256 Say Y here if you're going to use hardware that connects to the
260 bool "Enable support for the CPM2 (Communications Processor Module)"
261 depends on (FSL_SOC_BOOKE && PPC32) || 8260
266 The CPM2 (Communications Processor Module) is a coprocessor on
267 embedded CPUs made by Freescale. Selecting this option means that
268 you wish to build a kernel for a machine with a CPM2 coprocessor
269 on it (826x, 827x, 8560).
273 select GENERIC_ISA_DMA
275 Supports for the ULI1575 PCIe south bridge that exists on some
276 Freescale reference boards. The boards all use the ULI in pretty
281 select GENERIC_ALLOCATOR
286 Uses information from the OF or flattened device tree to instantiate
287 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
290 bool "Use the platform RTC operations from user space"
292 select RTC_DRV_GENERIC
294 This option provides backwards compatibility with the old gen_rtc.ko
295 module that was traditionally used for old PowerPC machines.
296 Platforms should migrate to enabling the RTC_DRV_GENERIC by hand
297 replacing their get_rtc_time/set_rtc_time callbacks with
298 a proper RTC device driver.
301 bool "Support for simple, memory-mapped GPIO controllers"
305 Say Y here to support simple, memory-mapped GPIO controllers.
306 These are usually BCSRs used to control board's switches, LEDs,
307 chip-selects, Ethernet/USB PHY's power and various other small
308 on-board peripherals.
310 config MCU_MPC8349EMITX
311 bool "MPC8349E-mITX MCU driver"
312 depends on I2C=y && PPC_83xx
315 Say Y here to enable soft power-off functionality on the Freescale
316 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
317 also register MCU GPIOs with the generic GPIO API, so you'll able
318 to use MCU pins as GPIOs.
321 bool "Xilinx PCI host bridge support"
322 depends on PCI && XILINX_VIRTEX