1 // SPDX-License-Identifier: GPL-2.0
3 * General Purpose functions for the global management of the
4 * Communication Processor Module.
5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
7 * In addition to the individual control of the communication
8 * channels, there are a few functions that globally affect the
9 * communication processor.
11 * Buffer descriptors must be allocated from the dual ported memory
12 * space. The allocator for that is here. When the communication
13 * process is reset, we reclaim the memory available. There is
14 * currently no deallocator for this memory.
15 * The amount of space available is platform dependent. On the
16 * MBX, the EPPC software loads additional microcode into the
17 * communication processor, and uses some of the DP ram for this
18 * purpose. Current, the first 512 bytes and the last 256 bytes of
19 * memory are used. Right now I am conservative and only use the
20 * memory that can never be used for microcode. If there are
21 * applications that require more DP ram, we can expand the boundaries
22 * but then we have to be careful of any downloaded microcode.
24 #include <linux/errno.h>
25 #include <linux/sched.h>
26 #include <linux/kernel.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/param.h>
29 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/module.h>
34 #include <linux/spinlock.h>
35 #include <linux/slab.h>
37 #include <asm/pgtable.h>
38 #include <asm/8xx_immap.h>
41 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
47 #ifdef CONFIG_8xx_GPIO
48 #include <linux/of_gpio.h>
51 #define CPM_MAP_SIZE (0x4000)
53 cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
54 immap_t __iomem *mpc8xx_immr;
55 static cpic8xx_t __iomem *cpic_reg;
57 static struct irq_domain *cpm_pic_host;
59 static void cpm_mask_irq(struct irq_data *d)
61 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
63 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
66 static void cpm_unmask_irq(struct irq_data *d)
68 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
70 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
73 static void cpm_end_irq(struct irq_data *d)
75 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
77 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
80 static struct irq_chip cpm_pic = {
82 .irq_mask = cpm_mask_irq,
83 .irq_unmask = cpm_unmask_irq,
84 .irq_eoi = cpm_end_irq,
92 * Get the vector by setting the ACK bit and then reading
95 out_be16(&cpic_reg->cpic_civr, 1);
96 cpm_vec = in_be16(&cpic_reg->cpic_civr);
99 return irq_linear_revmap(cpm_pic_host, cpm_vec);
102 static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
105 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
107 irq_set_status_flags(virq, IRQ_LEVEL);
108 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
113 * The CPM can generate the error interrupt when there is a race condition
114 * between generating and masking interrupts. All we have to do is ACK it
115 * and return. This is a no-op function so we don't need any special
116 * tests in the interrupt handler.
118 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
123 static struct irqaction cpm_error_irqaction = {
124 .handler = cpm_error_interrupt,
125 .flags = IRQF_NO_THREAD,
129 static const struct irq_domain_ops cpm_pic_host_ops = {
130 .map = cpm_pic_host_map,
133 unsigned int cpm_pic_init(void)
135 struct device_node *np = NULL;
137 unsigned int sirq = 0, hwirq, eirq;
140 pr_debug("cpm_pic_init\n");
142 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
144 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
146 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
150 ret = of_address_to_resource(np, 0, &res);
154 cpic_reg = ioremap(res.start, resource_size(&res));
155 if (cpic_reg == NULL)
158 sirq = irq_of_parse_and_map(np, 0);
162 /* Initialize the CPM interrupt controller. */
163 hwirq = (unsigned int)virq_to_hw(sirq);
164 out_be32(&cpic_reg->cpic_cicr,
165 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
166 ((hwirq/2) << 13) | CICR_HP_MASK);
168 out_be32(&cpic_reg->cpic_cimr, 0);
170 cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
171 if (cpm_pic_host == NULL) {
172 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
177 /* Install our own error handler. */
178 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
180 np = of_find_node_by_type(NULL, "cpm");
182 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
186 eirq = irq_of_parse_and_map(np, 0);
190 if (setup_irq(eirq, &cpm_error_irqaction))
191 printk(KERN_ERR "Could not allocate CPM error IRQ!");
193 setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
200 void __init cpm_reset(void)
202 sysconf8xx_t __iomem *siu_conf;
204 mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
206 printk(KERN_CRIT "Could not map IMMR\n");
210 cpmp = &mpc8xx_immr->im_cpm;
212 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
213 /* Perform a reset. */
214 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
217 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
220 #ifdef CONFIG_UCODE_PATCH
221 cpm_load_patch(cpmp);
225 * Set SDMA Bus Request priority 5.
226 * On 860T, this also enables FEC priority 6. I am not sure
227 * this is what we really want for some applications, but the
228 * manual recommends it.
229 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
231 siu_conf = immr_map(im_siu_conf);
232 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
233 out_be32(&siu_conf->sc_sdcr, 0x40);
235 out_be32(&siu_conf->sc_sdcr, 1);
236 immr_unmap(siu_conf);
239 static DEFINE_SPINLOCK(cmd_lock);
241 #define MAX_CR_CMD_LOOPS 10000
243 int cpm_command(u32 command, u8 opcode)
248 if (command & 0xffffff0f)
251 spin_lock_irqsave(&cmd_lock, flags);
254 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
255 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
256 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
259 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
262 spin_unlock_irqrestore(&cmd_lock, flags);
265 EXPORT_SYMBOL(cpm_command);
268 * Set a baud rate generator. This needs lots of work. There are
269 * four BRGs, any of which can be wired to any channel.
270 * The internal baud rate clock is the system clock divided by 16.
271 * This assumes the baudrate is 16x oversampled by the uart.
273 #define BRG_INT_CLK (get_brgfreq())
274 #define BRG_UART_CLK (BRG_INT_CLK/16)
275 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
278 cpm_setbrg(uint brg, uint rate)
282 /* This is good enough to get SMCs running..... */
283 bp = &cpmp->cp_brgc1;
286 * The BRG has a 12-bit counter. For really slow baud rates (or
287 * really fast processors), we may have to further divide by 16.
289 if (((BRG_UART_CLK / rate) - 1) < 4096)
290 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
292 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
293 CPM_BRG_EN | CPM_BRG_DIV16);
295 EXPORT_SYMBOL(cpm_setbrg);
297 struct cpm_ioport16 {
298 __be16 dir, par, odr_sor, dat, intr;
302 struct cpm_ioport32b {
303 __be32 dir, par, odr, dat;
306 struct cpm_ioport32e {
307 __be32 dir, par, sor, odr, dat;
310 static void cpm1_set_pin32(int port, int pin, int flags)
312 struct cpm_ioport32e __iomem *iop;
313 pin = 1 << (31 - pin);
315 if (port == CPM_PORTB)
316 iop = (struct cpm_ioport32e __iomem *)
317 &mpc8xx_immr->im_cpm.cp_pbdir;
319 iop = (struct cpm_ioport32e __iomem *)
320 &mpc8xx_immr->im_cpm.cp_pedir;
322 if (flags & CPM_PIN_OUTPUT)
323 setbits32(&iop->dir, pin);
325 clrbits32(&iop->dir, pin);
327 if (!(flags & CPM_PIN_GPIO))
328 setbits32(&iop->par, pin);
330 clrbits32(&iop->par, pin);
332 if (port == CPM_PORTB) {
333 if (flags & CPM_PIN_OPENDRAIN)
334 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
336 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
339 if (port == CPM_PORTE) {
340 if (flags & CPM_PIN_SECONDARY)
341 setbits32(&iop->sor, pin);
343 clrbits32(&iop->sor, pin);
345 if (flags & CPM_PIN_OPENDRAIN)
346 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
348 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
352 static void cpm1_set_pin16(int port, int pin, int flags)
354 struct cpm_ioport16 __iomem *iop =
355 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
357 pin = 1 << (15 - pin);
362 if (flags & CPM_PIN_OUTPUT)
363 setbits16(&iop->dir, pin);
365 clrbits16(&iop->dir, pin);
367 if (!(flags & CPM_PIN_GPIO))
368 setbits16(&iop->par, pin);
370 clrbits16(&iop->par, pin);
372 if (port == CPM_PORTA) {
373 if (flags & CPM_PIN_OPENDRAIN)
374 setbits16(&iop->odr_sor, pin);
376 clrbits16(&iop->odr_sor, pin);
378 if (port == CPM_PORTC) {
379 if (flags & CPM_PIN_SECONDARY)
380 setbits16(&iop->odr_sor, pin);
382 clrbits16(&iop->odr_sor, pin);
383 if (flags & CPM_PIN_FALLEDGE)
384 setbits16(&iop->intr, pin);
386 clrbits16(&iop->intr, pin);
390 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
392 if (port == CPM_PORTB || port == CPM_PORTE)
393 cpm1_set_pin32(port, pin, flags);
395 cpm1_set_pin16(port, pin, flags);
398 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
406 {CPM_CLK_SCC1, CPM_BRG1, 0},
407 {CPM_CLK_SCC1, CPM_BRG2, 1},
408 {CPM_CLK_SCC1, CPM_BRG3, 2},
409 {CPM_CLK_SCC1, CPM_BRG4, 3},
410 {CPM_CLK_SCC1, CPM_CLK1, 4},
411 {CPM_CLK_SCC1, CPM_CLK2, 5},
412 {CPM_CLK_SCC1, CPM_CLK3, 6},
413 {CPM_CLK_SCC1, CPM_CLK4, 7},
415 {CPM_CLK_SCC2, CPM_BRG1, 0},
416 {CPM_CLK_SCC2, CPM_BRG2, 1},
417 {CPM_CLK_SCC2, CPM_BRG3, 2},
418 {CPM_CLK_SCC2, CPM_BRG4, 3},
419 {CPM_CLK_SCC2, CPM_CLK1, 4},
420 {CPM_CLK_SCC2, CPM_CLK2, 5},
421 {CPM_CLK_SCC2, CPM_CLK3, 6},
422 {CPM_CLK_SCC2, CPM_CLK4, 7},
424 {CPM_CLK_SCC3, CPM_BRG1, 0},
425 {CPM_CLK_SCC3, CPM_BRG2, 1},
426 {CPM_CLK_SCC3, CPM_BRG3, 2},
427 {CPM_CLK_SCC3, CPM_BRG4, 3},
428 {CPM_CLK_SCC3, CPM_CLK5, 4},
429 {CPM_CLK_SCC3, CPM_CLK6, 5},
430 {CPM_CLK_SCC3, CPM_CLK7, 6},
431 {CPM_CLK_SCC3, CPM_CLK8, 7},
433 {CPM_CLK_SCC4, CPM_BRG1, 0},
434 {CPM_CLK_SCC4, CPM_BRG2, 1},
435 {CPM_CLK_SCC4, CPM_BRG3, 2},
436 {CPM_CLK_SCC4, CPM_BRG4, 3},
437 {CPM_CLK_SCC4, CPM_CLK5, 4},
438 {CPM_CLK_SCC4, CPM_CLK6, 5},
439 {CPM_CLK_SCC4, CPM_CLK7, 6},
440 {CPM_CLK_SCC4, CPM_CLK8, 7},
442 {CPM_CLK_SMC1, CPM_BRG1, 0},
443 {CPM_CLK_SMC1, CPM_BRG2, 1},
444 {CPM_CLK_SMC1, CPM_BRG3, 2},
445 {CPM_CLK_SMC1, CPM_BRG4, 3},
446 {CPM_CLK_SMC1, CPM_CLK1, 4},
447 {CPM_CLK_SMC1, CPM_CLK2, 5},
448 {CPM_CLK_SMC1, CPM_CLK3, 6},
449 {CPM_CLK_SMC1, CPM_CLK4, 7},
451 {CPM_CLK_SMC2, CPM_BRG1, 0},
452 {CPM_CLK_SMC2, CPM_BRG2, 1},
453 {CPM_CLK_SMC2, CPM_BRG3, 2},
454 {CPM_CLK_SMC2, CPM_BRG4, 3},
455 {CPM_CLK_SMC2, CPM_CLK5, 4},
456 {CPM_CLK_SMC2, CPM_CLK6, 5},
457 {CPM_CLK_SMC2, CPM_CLK7, 6},
458 {CPM_CLK_SMC2, CPM_CLK8, 7},
463 reg = &mpc8xx_immr->im_cpm.cp_sicr;
468 reg = &mpc8xx_immr->im_cpm.cp_sicr;
473 reg = &mpc8xx_immr->im_cpm.cp_sicr;
478 reg = &mpc8xx_immr->im_cpm.cp_sicr;
483 reg = &mpc8xx_immr->im_cpm.cp_simode;
488 reg = &mpc8xx_immr->im_cpm.cp_simode;
493 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
497 for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
498 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
499 bits = clk_map[i][2];
504 if (i == ARRAY_SIZE(clk_map)) {
505 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
512 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
513 if (mode == CPM_CLK_RTX) {
516 } else if (mode == CPM_CLK_RX) {
522 out_be32(reg, (in_be32(reg) & ~mask) | bits);
528 * GPIO LIB API implementation
530 #ifdef CONFIG_8xx_GPIO
532 struct cpm1_gpio16_chip {
533 struct of_mm_gpio_chip mm_gc;
536 /* shadowed data register to clear/set bits safely */
539 /* IRQ associated with Pins when relevant */
543 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
545 struct cpm1_gpio16_chip *cpm1_gc =
546 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
547 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
549 cpm1_gc->cpdata = in_be16(&iop->dat);
552 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
554 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
555 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
558 pin_mask = 1 << (15 - gpio);
560 return !!(in_be16(&iop->dat) & pin_mask);
563 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
566 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
567 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
570 cpm1_gc->cpdata |= pin_mask;
572 cpm1_gc->cpdata &= ~pin_mask;
574 out_be16(&iop->dat, cpm1_gc->cpdata);
577 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
579 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
580 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
582 u16 pin_mask = 1 << (15 - gpio);
584 spin_lock_irqsave(&cpm1_gc->lock, flags);
586 __cpm1_gpio16_set(mm_gc, pin_mask, value);
588 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
591 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
593 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
594 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
596 return cpm1_gc->irq[gpio] ? : -ENXIO;
599 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
601 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
602 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
603 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
605 u16 pin_mask = 1 << (15 - gpio);
607 spin_lock_irqsave(&cpm1_gc->lock, flags);
609 setbits16(&iop->dir, pin_mask);
610 __cpm1_gpio16_set(mm_gc, pin_mask, val);
612 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
617 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
619 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
620 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
621 struct cpm_ioport16 __iomem *iop = mm_gc->regs;
623 u16 pin_mask = 1 << (15 - gpio);
625 spin_lock_irqsave(&cpm1_gc->lock, flags);
627 clrbits16(&iop->dir, pin_mask);
629 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
634 int cpm1_gpiochip_add16(struct device *dev)
636 struct device_node *np = dev->of_node;
637 struct cpm1_gpio16_chip *cpm1_gc;
638 struct of_mm_gpio_chip *mm_gc;
639 struct gpio_chip *gc;
642 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
646 spin_lock_init(&cpm1_gc->lock);
648 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
651 for (i = 0, j = 0; i < 16; i++)
652 if (mask & (1 << (15 - i)))
653 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
656 mm_gc = &cpm1_gc->mm_gc;
659 mm_gc->save_regs = cpm1_gpio16_save_regs;
661 gc->direction_input = cpm1_gpio16_dir_in;
662 gc->direction_output = cpm1_gpio16_dir_out;
663 gc->get = cpm1_gpio16_get;
664 gc->set = cpm1_gpio16_set;
665 gc->to_irq = cpm1_gpio16_to_irq;
667 gc->owner = THIS_MODULE;
669 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
672 struct cpm1_gpio32_chip {
673 struct of_mm_gpio_chip mm_gc;
676 /* shadowed data register to clear/set bits safely */
680 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
682 struct cpm1_gpio32_chip *cpm1_gc =
683 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
684 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
686 cpm1_gc->cpdata = in_be32(&iop->dat);
689 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
691 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
692 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
695 pin_mask = 1 << (31 - gpio);
697 return !!(in_be32(&iop->dat) & pin_mask);
700 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
703 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
704 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
707 cpm1_gc->cpdata |= pin_mask;
709 cpm1_gc->cpdata &= ~pin_mask;
711 out_be32(&iop->dat, cpm1_gc->cpdata);
714 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
716 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
717 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
719 u32 pin_mask = 1 << (31 - gpio);
721 spin_lock_irqsave(&cpm1_gc->lock, flags);
723 __cpm1_gpio32_set(mm_gc, pin_mask, value);
725 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
728 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
730 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
731 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
732 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
734 u32 pin_mask = 1 << (31 - gpio);
736 spin_lock_irqsave(&cpm1_gc->lock, flags);
738 setbits32(&iop->dir, pin_mask);
739 __cpm1_gpio32_set(mm_gc, pin_mask, val);
741 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
746 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
748 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
749 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
750 struct cpm_ioport32b __iomem *iop = mm_gc->regs;
752 u32 pin_mask = 1 << (31 - gpio);
754 spin_lock_irqsave(&cpm1_gc->lock, flags);
756 clrbits32(&iop->dir, pin_mask);
758 spin_unlock_irqrestore(&cpm1_gc->lock, flags);
763 int cpm1_gpiochip_add32(struct device *dev)
765 struct device_node *np = dev->of_node;
766 struct cpm1_gpio32_chip *cpm1_gc;
767 struct of_mm_gpio_chip *mm_gc;
768 struct gpio_chip *gc;
770 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
774 spin_lock_init(&cpm1_gc->lock);
776 mm_gc = &cpm1_gc->mm_gc;
779 mm_gc->save_regs = cpm1_gpio32_save_regs;
781 gc->direction_input = cpm1_gpio32_dir_in;
782 gc->direction_output = cpm1_gpio32_dir_out;
783 gc->get = cpm1_gpio32_get;
784 gc->set = cpm1_gpio32_set;
786 gc->owner = THIS_MODULE;
788 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
791 #endif /* CONFIG_8xx_GPIO */