arch/powerpc/platforms/8xx/cpm1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * General Purpose functions for the global management of the
   4  * Communication Processor Module.
   5  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   6  *
   7  * In addition to the individual control of the communication
   8  * channels, there are a few functions that globally affect the
   9  * communication processor.
  10  *
  11  * Buffer descriptors must be allocated from the dual ported memory
  12  * space.  The allocator for that is here.  When the communication
  13  * process is reset, we reclaim the memory available.  There is
  14  * currently no deallocator for this memory.
  15  * The amount of space available is platform dependent.  On the
  16  * MBX, the EPPC software loads additional microcode into the
  17  * communication processor, and uses some of the DP ram for this
  18  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  19  * memory are used.  Right now I am conservative and only use the
  20  * memory that can never be used for microcode.  If there are
  21  * applications that require more DP ram, we can expand the boundaries
  22  * but then we have to be careful of any downloaded microcode.
  23  */
  24 #include <linux/errno.h>
  25 #include <linux/sched.h>
  26 #include <linux/kernel.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/param.h>
  29 #include <linux/string.h>
  30 #include <linux/mm.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/irq.h>
  33 #include <linux/module.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/slab.h>
  36 #include <asm/page.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/8xx_immap.h>
  39 #include <asm/cpm1.h>
  40 #include <asm/io.h>
  41 #include <asm/rheap.h>
  42 #include <asm/prom.h>
  43 #include <asm/cpm.h>
  44
  45 #include <asm/fs_pd.h>
  46
  47 #ifdef CONFIG_8xx_GPIO
  48 #include <linux/of_gpio.h>
  49 #endif
  50
  51 #define CPM_MAP_SIZE    (0x4000)
  52
  53 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  54 immap_t __iomem *mpc8xx_immr;
  55 static cpic8xx_t __iomem *cpic_reg;
  56
  57 static struct irq_domain *cpm_pic_host;
  58
  59 static void cpm_mask_irq(struct irq_data *d)
  60 {
  61         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  62
  63         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  64 }
  65
  66 static void cpm_unmask_irq(struct irq_data *d)
  67 {
  68         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  69
  70         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  71 }
  72
  73 static void cpm_end_irq(struct irq_data *d)
  74 {
  75         unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
  76
  77         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  78 }
  79
  80 static struct irq_chip cpm_pic = {
  81         .name = "CPM PIC",
  82         .irq_mask = cpm_mask_irq,
  83         .irq_unmask = cpm_unmask_irq,
  84         .irq_eoi = cpm_end_irq,
  85 };
  86
  87 int cpm_get_irq(void)
  88 {
  89         int cpm_vec;
  90
  91         /*
  92          * Get the vector by setting the ACK bit and then reading
  93          * the register.
  94          */
  95         out_be16(&cpic_reg->cpic_civr, 1);
  96         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  97         cpm_vec >>= 11;
  98
  99         return irq_linear_revmap(cpm_pic_host, cpm_vec);
 100 }
 101
 102 static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
 103                           irq_hw_number_t hw)
 104 {
 105         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 106
 107         irq_set_status_flags(virq, IRQ_LEVEL);
 108         irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 109         return 0;
 110 }
 111
 112 /*
 113  * The CPM can generate the error interrupt when there is a race condition
 114  * between generating and masking interrupts.  All we have to do is ACK it
 115  * and return.  This is a no-op function so we don't need any special
 116  * tests in the interrupt handler.
 117  */
 118 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 119 {
 120         return IRQ_HANDLED;
 121 }
 122
 123 static struct irqaction cpm_error_irqaction = {
 124         .handler = cpm_error_interrupt,
 125         .flags = IRQF_NO_THREAD,
 126         .name = "error",
 127 };
 128
 129 static const struct irq_domain_ops cpm_pic_host_ops = {
 130         .map = cpm_pic_host_map,
 131 };
 132
 133 unsigned int cpm_pic_init(void)
 134 {
 135         struct device_node *np = NULL;
 136         struct resource res;
 137         unsigned int sirq = 0, hwirq, eirq;
 138         int ret;
 139
 140         pr_debug("cpm_pic_init\n");
 141
 142         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 143         if (np == NULL)
 144                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 145         if (np == NULL) {
 146                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 147                 return sirq;
 148         }
 149
 150         ret = of_address_to_resource(np, 0, &res);
 151         if (ret)
 152                 goto end;
 153
 154         cpic_reg = ioremap(res.start, resource_size(&res));
 155         if (cpic_reg == NULL)
 156                 goto end;
 157
 158         sirq = irq_of_parse_and_map(np, 0);
 159         if (!sirq)
 160                 goto end;
 161
 162         /* Initialize the CPM interrupt controller. */
 163         hwirq = (unsigned int)virq_to_hw(sirq);
 164         out_be32(&cpic_reg->cpic_cicr,
 165             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 166                 ((hwirq/2) << 13) | CICR_HP_MASK);
 167
 168         out_be32(&cpic_reg->cpic_cimr, 0);
 169
 170         cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
 171         if (cpm_pic_host == NULL) {
 172                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 173                 sirq = 0;
 174                 goto end;
 175         }
 176
 177         /* Install our own error handler. */
 178         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 179         if (np == NULL)
 180                 np = of_find_node_by_type(NULL, "cpm");
 181         if (np == NULL) {
 182                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 183                 goto end;
 184         }
 185
 186         eirq = irq_of_parse_and_map(np, 0);
 187         if (!eirq)
 188                 goto end;
 189
 190         if (setup_irq(eirq, &cpm_error_irqaction))
 191                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 192
 193         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 194
 195 end:
 196         of_node_put(np);
 197         return sirq;
 198 }
 199
 200 void __init cpm_reset(void)
 201 {
 202         sysconf8xx_t __iomem *siu_conf;
 203
 204         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 205         if (!mpc8xx_immr) {
 206                 printk(KERN_CRIT "Could not map IMMR\n");
 207                 return;
 208         }
 209
 210         cpmp = &mpc8xx_immr->im_cpm;
 211
 212 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 213         /* Perform a reset. */
 214         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 215
 216         /* Wait for it. */
 217         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 218 #endif
 219
 220 #ifdef CONFIG_UCODE_PATCH
 221         cpm_load_patch(cpmp);
 222 #endif
 223
 224         /*
 225          * Set SDMA Bus Request priority 5.
 226          * On 860T, this also enables FEC priority 6.  I am not sure
 227          * this is what we really want for some applications, but the
 228          * manual recommends it.
 229          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 230          */
 231         siu_conf = immr_map(im_siu_conf);
 232         if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
 233                 out_be32(&siu_conf->sc_sdcr, 0x40);
 234         else
 235                 out_be32(&siu_conf->sc_sdcr, 1);
 236         immr_unmap(siu_conf);
 237 }
 238
 239 static DEFINE_SPINLOCK(cmd_lock);
 240
 241 #define MAX_CR_CMD_LOOPS        10000
 242
 243 int cpm_command(u32 command, u8 opcode)
 244 {
 245         int i, ret;
 246         unsigned long flags;
 247
 248         if (command & 0xffffff0f)
 249                 return -EINVAL;
 250
 251         spin_lock_irqsave(&cmd_lock, flags);
 252
 253         ret = 0;
 254         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 255         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 256                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 257                         goto out;
 258
 259         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 260         ret = -EIO;
 261 out:
 262         spin_unlock_irqrestore(&cmd_lock, flags);
 263         return ret;
 264 }
 265 EXPORT_SYMBOL(cpm_command);
 266
 267 /*
 268  * Set a baud rate generator.  This needs lots of work.  There are
 269  * four BRGs, any of which can be wired to any channel.
 270  * The internal baud rate clock is the system clock divided by 16.
 271  * This assumes the baudrate is 16x oversampled by the uart.
 272  */
 273 #define BRG_INT_CLK             (get_brgfreq())
 274 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 275 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 276
 277 void
 278 cpm_setbrg(uint brg, uint rate)
 279 {
 280         u32 __iomem *bp;
 281
 282         /* This is good enough to get SMCs running..... */
 283         bp = &cpmp->cp_brgc1;
 284         bp += brg;
 285         /*
 286          * The BRG has a 12-bit counter.  For really slow baud rates (or
 287          * really fast processors), we may have to further divide by 16.
 288          */
 289         if (((BRG_UART_CLK / rate) - 1) < 4096)
 290                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 291         else
 292                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 293                               CPM_BRG_EN | CPM_BRG_DIV16);
 294 }
 295 EXPORT_SYMBOL(cpm_setbrg);
 296
 297 struct cpm_ioport16 {
 298         __be16 dir, par, odr_sor, dat, intr;
 299         __be16 res[3];
 300 };
 301
 302 struct cpm_ioport32b {
 303         __be32 dir, par, odr, dat;
 304 };
 305
 306 struct cpm_ioport32e {
 307         __be32 dir, par, sor, odr, dat;
 308 };
 309
 310 static void cpm1_set_pin32(int port, int pin, int flags)
 311 {
 312         struct cpm_ioport32e __iomem *iop;
 313         pin = 1 << (31 - pin);
 314
 315         if (port == CPM_PORTB)
 316                 iop = (struct cpm_ioport32e __iomem *)
 317                       &mpc8xx_immr->im_cpm.cp_pbdir;
 318         else
 319                 iop = (struct cpm_ioport32e __iomem *)
 320                       &mpc8xx_immr->im_cpm.cp_pedir;
 321
 322         if (flags & CPM_PIN_OUTPUT)
 323                 setbits32(&iop->dir, pin);
 324         else
 325                 clrbits32(&iop->dir, pin);
 326
 327         if (!(flags & CPM_PIN_GPIO))
 328                 setbits32(&iop->par, pin);
 329         else
 330                 clrbits32(&iop->par, pin);
 331
 332         if (port == CPM_PORTB) {
 333                 if (flags & CPM_PIN_OPENDRAIN)
 334                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 335                 else
 336                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 337         }
 338
 339         if (port == CPM_PORTE) {
 340                 if (flags & CPM_PIN_SECONDARY)
 341                         setbits32(&iop->sor, pin);
 342                 else
 343                         clrbits32(&iop->sor, pin);
 344
 345                 if (flags & CPM_PIN_OPENDRAIN)
 346                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 347                 else
 348                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 349         }
 350 }
 351
 352 static void cpm1_set_pin16(int port, int pin, int flags)
 353 {
 354         struct cpm_ioport16 __iomem *iop =
 355                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 356
 357         pin = 1 << (15 - pin);
 358
 359         if (port != 0)
 360                 iop += port - 1;
 361
 362         if (flags & CPM_PIN_OUTPUT)
 363                 setbits16(&iop->dir, pin);
 364         else
 365                 clrbits16(&iop->dir, pin);
 366
 367         if (!(flags & CPM_PIN_GPIO))
 368                 setbits16(&iop->par, pin);
 369         else
 370                 clrbits16(&iop->par, pin);
 371
 372         if (port == CPM_PORTA) {
 373                 if (flags & CPM_PIN_OPENDRAIN)
 374                         setbits16(&iop->odr_sor, pin);
 375                 else
 376                         clrbits16(&iop->odr_sor, pin);
 377         }
 378         if (port == CPM_PORTC) {
 379                 if (flags & CPM_PIN_SECONDARY)
 380                         setbits16(&iop->odr_sor, pin);
 381                 else
 382                         clrbits16(&iop->odr_sor, pin);
 383                 if (flags & CPM_PIN_FALLEDGE)
 384                         setbits16(&iop->intr, pin);
 385                 else
 386                         clrbits16(&iop->intr, pin);
 387         }
 388 }
 389
 390 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 391 {
 392         if (port == CPM_PORTB || port == CPM_PORTE)
 393                 cpm1_set_pin32(port, pin, flags);
 394         else
 395                 cpm1_set_pin16(port, pin, flags);
 396 }
 397
 398 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 399 {
 400         int shift;
 401         int i, bits = 0;
 402         u32 __iomem *reg;
 403         u32 mask = 7;
 404
 405         u8 clk_map[][3] = {
 406                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 407                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 408                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 409                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 410                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 411                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 412                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 413                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 414
 415                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 416                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 417                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 418                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 419                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 420                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 421                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 422                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 423
 424                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 425                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 426                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 427                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 428                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 429                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 430                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 431                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 432
 433                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 434                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 435                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 436                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 437                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 438                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 439                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 440                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 441
 442                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 443                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 444                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 445                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 446                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 447                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 448                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 449                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 450
 451                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 452                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 453                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 454                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 455                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 456                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 457                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 458                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 459         };
 460
 461         switch (target) {
 462         case CPM_CLK_SCC1:
 463                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 464                 shift = 0;
 465                 break;
 466
 467         case CPM_CLK_SCC2:
 468                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 469                 shift = 8;
 470                 break;
 471
 472         case CPM_CLK_SCC3:
 473                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 474                 shift = 16;
 475                 break;
 476
 477         case CPM_CLK_SCC4:
 478                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 479                 shift = 24;
 480                 break;
 481
 482         case CPM_CLK_SMC1:
 483                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 484                 shift = 12;
 485                 break;
 486
 487         case CPM_CLK_SMC2:
 488                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 489                 shift = 28;
 490                 break;
 491
 492         default:
 493                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 494                 return -EINVAL;
 495         }
 496
 497         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 498                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 499                         bits = clk_map[i][2];
 500                         break;
 501                 }
 502         }
 503
 504         if (i == ARRAY_SIZE(clk_map)) {
 505                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 506                 return -EINVAL;
 507         }
 508
 509         bits <<= shift;
 510         mask <<= shift;
 511
 512         if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
 513                 if (mode == CPM_CLK_RTX) {
 514                         bits |= bits << 3;
 515                         mask |= mask << 3;
 516                 } else if (mode == CPM_CLK_RX) {
 517                         bits <<= 3;
 518                         mask <<= 3;
 519                 }
 520         }
 521
 522         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 523
 524         return 0;
 525 }
 526
 527 /*
 528  * GPIO LIB API implementation
 529  */
 530 #ifdef CONFIG_8xx_GPIO
 531
 532 struct cpm1_gpio16_chip {
 533         struct of_mm_gpio_chip mm_gc;
 534         spinlock_t lock;
 535
 536         /* shadowed data register to clear/set bits safely */
 537         u16 cpdata;
 538
 539         /* IRQ associated with Pins when relevant */
 540         int irq[16];
 541 };
 542
 543 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
 544 {
 545         struct cpm1_gpio16_chip *cpm1_gc =
 546                 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
 547         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 548
 549         cpm1_gc->cpdata = in_be16(&iop->dat);
 550 }
 551
 552 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
 553 {
 554         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 555         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 556         u16 pin_mask;
 557
 558         pin_mask = 1 << (15 - gpio);
 559
 560         return !!(in_be16(&iop->dat) & pin_mask);
 561 }
 562
 563 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
 564         int value)
 565 {
 566         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 567         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 568
 569         if (value)
 570                 cpm1_gc->cpdata |= pin_mask;
 571         else
 572                 cpm1_gc->cpdata &= ~pin_mask;
 573
 574         out_be16(&iop->dat, cpm1_gc->cpdata);
 575 }
 576
 577 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
 578 {
 579         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 580         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 581         unsigned long flags;
 582         u16 pin_mask = 1 << (15 - gpio);
 583
 584         spin_lock_irqsave(&cpm1_gc->lock, flags);
 585
 586         __cpm1_gpio16_set(mm_gc, pin_mask, value);
 587
 588         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 589 }
 590
 591 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
 592 {
 593         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 594         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 595
 596         return cpm1_gc->irq[gpio] ? : -ENXIO;
 597 }
 598
 599 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 600 {
 601         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 602         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 603         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 604         unsigned long flags;
 605         u16 pin_mask = 1 << (15 - gpio);
 606
 607         spin_lock_irqsave(&cpm1_gc->lock, flags);
 608
 609         setbits16(&iop->dir, pin_mask);
 610         __cpm1_gpio16_set(mm_gc, pin_mask, val);
 611
 612         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 613
 614         return 0;
 615 }
 616
 617 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
 618 {
 619         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 620         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 621         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 622         unsigned long flags;
 623         u16 pin_mask = 1 << (15 - gpio);
 624
 625         spin_lock_irqsave(&cpm1_gc->lock, flags);
 626
 627         clrbits16(&iop->dir, pin_mask);
 628
 629         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 630
 631         return 0;
 632 }
 633
 634 int cpm1_gpiochip_add16(struct device *dev)
 635 {
 636         struct device_node *np = dev->of_node;
 637         struct cpm1_gpio16_chip *cpm1_gc;
 638         struct of_mm_gpio_chip *mm_gc;
 639         struct gpio_chip *gc;
 640         u16 mask;
 641
 642         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 643         if (!cpm1_gc)
 644                 return -ENOMEM;
 645
 646         spin_lock_init(&cpm1_gc->lock);
 647
 648         if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
 649                 int i, j;
 650
 651                 for (i = 0, j = 0; i < 16; i++)
 652                         if (mask & (1 << (15 - i)))
 653                                 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
 654         }
 655
 656         mm_gc = &cpm1_gc->mm_gc;
 657         gc = &mm_gc->gc;
 658
 659         mm_gc->save_regs = cpm1_gpio16_save_regs;
 660         gc->ngpio = 16;
 661         gc->direction_input = cpm1_gpio16_dir_in;
 662         gc->direction_output = cpm1_gpio16_dir_out;
 663         gc->get = cpm1_gpio16_get;
 664         gc->set = cpm1_gpio16_set;
 665         gc->to_irq = cpm1_gpio16_to_irq;
 666         gc->parent = dev;
 667         gc->owner = THIS_MODULE;
 668
 669         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 670 }
 671
 672 struct cpm1_gpio32_chip {
 673         struct of_mm_gpio_chip mm_gc;
 674         spinlock_t lock;
 675
 676         /* shadowed data register to clear/set bits safely */
 677         u32 cpdata;
 678 };
 679
 680 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
 681 {
 682         struct cpm1_gpio32_chip *cpm1_gc =
 683                 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
 684         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 685
 686         cpm1_gc->cpdata = in_be32(&iop->dat);
 687 }
 688
 689 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
 690 {
 691         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 692         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 693         u32 pin_mask;
 694
 695         pin_mask = 1 << (31 - gpio);
 696
 697         return !!(in_be32(&iop->dat) & pin_mask);
 698 }
 699
 700 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
 701         int value)
 702 {
 703         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 704         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 705
 706         if (value)
 707                 cpm1_gc->cpdata |= pin_mask;
 708         else
 709                 cpm1_gc->cpdata &= ~pin_mask;
 710
 711         out_be32(&iop->dat, cpm1_gc->cpdata);
 712 }
 713
 714 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 715 {
 716         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 717         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 718         unsigned long flags;
 719         u32 pin_mask = 1 << (31 - gpio);
 720
 721         spin_lock_irqsave(&cpm1_gc->lock, flags);
 722
 723         __cpm1_gpio32_set(mm_gc, pin_mask, value);
 724
 725         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 726 }
 727
 728 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 729 {
 730         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 731         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 732         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 733         unsigned long flags;
 734         u32 pin_mask = 1 << (31 - gpio);
 735
 736         spin_lock_irqsave(&cpm1_gc->lock, flags);
 737
 738         setbits32(&iop->dir, pin_mask);
 739         __cpm1_gpio32_set(mm_gc, pin_mask, val);
 740
 741         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 742
 743         return 0;
 744 }
 745
 746 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 747 {
 748         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 749         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 750         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 751         unsigned long flags;
 752         u32 pin_mask = 1 << (31 - gpio);
 753
 754         spin_lock_irqsave(&cpm1_gc->lock, flags);
 755
 756         clrbits32(&iop->dir, pin_mask);
 757
 758         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 759
 760         return 0;
 761 }
 762
 763 int cpm1_gpiochip_add32(struct device *dev)
 764 {
 765         struct device_node *np = dev->of_node;
 766         struct cpm1_gpio32_chip *cpm1_gc;
 767         struct of_mm_gpio_chip *mm_gc;
 768         struct gpio_chip *gc;
 769
 770         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 771         if (!cpm1_gc)
 772                 return -ENOMEM;
 773
 774         spin_lock_init(&cpm1_gc->lock);
 775
 776         mm_gc = &cpm1_gc->mm_gc;
 777         gc = &mm_gc->gc;
 778
 779         mm_gc->save_regs = cpm1_gpio32_save_regs;
 780         gc->ngpio = 32;
 781         gc->direction_input = cpm1_gpio32_dir_in;
 782         gc->direction_output = cpm1_gpio32_dir_out;
 783         gc->get = cpm1_gpio32_get;
 784         gc->set = cpm1_gpio32_set;
 785         gc->parent = dev;
 786         gc->owner = THIS_MODULE;
 787
 788         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 789 }
 790
 791 #endif /* CONFIG_8xx_GPIO */