arch/powerpc/platforms/8xx/cpm1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * General Purpose functions for the global management of the
   4  * Communication Processor Module.
   5  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   6  *
   7  * In addition to the individual control of the communication
   8  * channels, there are a few functions that globally affect the
   9  * communication processor.
  10  *
  11  * Buffer descriptors must be allocated from the dual ported memory
  12  * space.  The allocator for that is here.  When the communication
  13  * process is reset, we reclaim the memory available.  There is
  14  * currently no deallocator for this memory.
  15  * The amount of space available is platform dependent.  On the
  16  * MBX, the EPPC software loads additional microcode into the
  17  * communication processor, and uses some of the DP ram for this
  18  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  19  * memory are used.  Right now I am conservative and only use the
  20  * memory that can never be used for microcode.  If there are
  21  * applications that require more DP ram, we can expand the boundaries
  22  * but then we have to be careful of any downloaded microcode.
  23  */
  24 #include <linux/errno.h>
  25 #include <linux/sched.h>
  26 #include <linux/kernel.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/param.h>
  29 #include <linux/string.h>
  30 #include <linux/mm.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/irq.h>
  33 #include <linux/module.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/slab.h>
  36 #include <linux/of_irq.h>
  37 #include <asm/page.h>
  38 #include <asm/8xx_immap.h>
  39 #include <asm/cpm1.h>
  40 #include <asm/io.h>
  41 #include <asm/rheap.h>
  42 #include <asm/cpm.h>
  43 #include <asm/fixmap.h>
  44
  45 #include <sysdev/fsl_soc.h>
  46
  47 #ifdef CONFIG_8xx_GPIO
  48 #include <linux/gpio/legacy-of-mm-gpiochip.h>
  49 #endif
  50
  51 #define CPM_MAP_SIZE    (0x4000)
  52
  53 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  54 immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE;
  55
  56 void __init cpm_reset(void)
  57 {
  58         cpmp = &mpc8xx_immr->im_cpm;
  59
  60 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
  61         /* Perform a reset. */
  62         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
  63
  64         /* Wait for it. */
  65         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
  66 #endif
  67
  68 #ifdef CONFIG_UCODE_PATCH
  69         cpm_load_patch(cpmp);
  70 #endif
  71
  72         /*
  73          * Set SDMA Bus Request priority 5.
  74          * On 860T, this also enables FEC priority 6.  I am not sure
  75          * this is what we really want for some applications, but the
  76          * manual recommends it.
  77          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
  78          */
  79         if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
  80                 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 0x40);
  81         else
  82                 out_be32(&mpc8xx_immr->im_siu_conf.sc_sdcr, 1);
  83 }
  84
  85 static DEFINE_SPINLOCK(cmd_lock);
  86
  87 #define MAX_CR_CMD_LOOPS        10000
  88
  89 int cpm_command(u32 command, u8 opcode)
  90 {
  91         int i, ret;
  92         unsigned long flags;
  93
  94         if (command & 0xffffff03)
  95                 return -EINVAL;
  96
  97         spin_lock_irqsave(&cmd_lock, flags);
  98
  99         ret = 0;
 100         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 101         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 102                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 103                         goto out;
 104
 105         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 106         ret = -EIO;
 107 out:
 108         spin_unlock_irqrestore(&cmd_lock, flags);
 109         return ret;
 110 }
 111 EXPORT_SYMBOL(cpm_command);
 112
 113 /*
 114  * Set a baud rate generator.  This needs lots of work.  There are
 115  * four BRGs, any of which can be wired to any channel.
 116  * The internal baud rate clock is the system clock divided by 16.
 117  * This assumes the baudrate is 16x oversampled by the uart.
 118  */
 119 #define BRG_INT_CLK             (get_brgfreq())
 120 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 121 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 122
 123 void
 124 cpm_setbrg(uint brg, uint rate)
 125 {
 126         u32 __iomem *bp;
 127
 128         /* This is good enough to get SMCs running..... */
 129         bp = &cpmp->cp_brgc1;
 130         bp += brg;
 131         /*
 132          * The BRG has a 12-bit counter.  For really slow baud rates (or
 133          * really fast processors), we may have to further divide by 16.
 134          */
 135         if (((BRG_UART_CLK / rate) - 1) < 4096)
 136                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 137         else
 138                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 139                               CPM_BRG_EN | CPM_BRG_DIV16);
 140 }
 141 EXPORT_SYMBOL(cpm_setbrg);
 142
 143 struct cpm_ioport16 {
 144         __be16 dir, par, odr_sor, dat, intr;
 145         __be16 res[3];
 146 };
 147
 148 struct cpm_ioport32b {
 149         __be32 dir, par, odr, dat;
 150 };
 151
 152 struct cpm_ioport32e {
 153         __be32 dir, par, sor, odr, dat;
 154 };
 155
 156 static void __init cpm1_set_pin32(int port, int pin, int flags)
 157 {
 158         struct cpm_ioport32e __iomem *iop;
 159         pin = 1 << (31 - pin);
 160
 161         if (port == CPM_PORTB)
 162                 iop = (struct cpm_ioport32e __iomem *)
 163                       &mpc8xx_immr->im_cpm.cp_pbdir;
 164         else
 165                 iop = (struct cpm_ioport32e __iomem *)
 166                       &mpc8xx_immr->im_cpm.cp_pedir;
 167
 168         if (flags & CPM_PIN_OUTPUT)
 169                 setbits32(&iop->dir, pin);
 170         else
 171                 clrbits32(&iop->dir, pin);
 172
 173         if (!(flags & CPM_PIN_GPIO))
 174                 setbits32(&iop->par, pin);
 175         else
 176                 clrbits32(&iop->par, pin);
 177
 178         if (port == CPM_PORTB) {
 179                 if (flags & CPM_PIN_OPENDRAIN)
 180                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 181                 else
 182                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 183         }
 184
 185         if (port == CPM_PORTE) {
 186                 if (flags & CPM_PIN_SECONDARY)
 187                         setbits32(&iop->sor, pin);
 188                 else
 189                         clrbits32(&iop->sor, pin);
 190
 191                 if (flags & CPM_PIN_OPENDRAIN)
 192                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 193                 else
 194                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 195         }
 196 }
 197
 198 static void __init cpm1_set_pin16(int port, int pin, int flags)
 199 {
 200         struct cpm_ioport16 __iomem *iop =
 201                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 202
 203         pin = 1 << (15 - pin);
 204
 205         if (port != 0)
 206                 iop += port - 1;
 207
 208         if (flags & CPM_PIN_OUTPUT)
 209                 setbits16(&iop->dir, pin);
 210         else
 211                 clrbits16(&iop->dir, pin);
 212
 213         if (!(flags & CPM_PIN_GPIO))
 214                 setbits16(&iop->par, pin);
 215         else
 216                 clrbits16(&iop->par, pin);
 217
 218         if (port == CPM_PORTA) {
 219                 if (flags & CPM_PIN_OPENDRAIN)
 220                         setbits16(&iop->odr_sor, pin);
 221                 else
 222                         clrbits16(&iop->odr_sor, pin);
 223         }
 224         if (port == CPM_PORTC) {
 225                 if (flags & CPM_PIN_SECONDARY)
 226                         setbits16(&iop->odr_sor, pin);
 227                 else
 228                         clrbits16(&iop->odr_sor, pin);
 229                 if (flags & CPM_PIN_FALLEDGE)
 230                         setbits16(&iop->intr, pin);
 231                 else
 232                         clrbits16(&iop->intr, pin);
 233         }
 234 }
 235
 236 void __init cpm1_set_pin(enum cpm_port port, int pin, int flags)
 237 {
 238         if (port == CPM_PORTB || port == CPM_PORTE)
 239                 cpm1_set_pin32(port, pin, flags);
 240         else
 241                 cpm1_set_pin16(port, pin, flags);
 242 }
 243
 244 int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 245 {
 246         int shift;
 247         int i, bits = 0;
 248         u32 __iomem *reg;
 249         u32 mask = 7;
 250
 251         u8 clk_map[][3] = {
 252                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 253                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 254                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 255                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 256                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 257                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 258                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 259                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 260
 261                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 262                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 263                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 264                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 265                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 266                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 267                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 268                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 269
 270                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 271                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 272                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 273                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 274                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 275                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 276                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 277                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 278
 279                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 280                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 281                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 282                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 283                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 284                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 285                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 286                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 287
 288                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 289                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 290                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 291                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 292                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 293                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 294                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 295                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 296
 297                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 298                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 299                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 300                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 301                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 302                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 303                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 304                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 305         };
 306
 307         switch (target) {
 308         case CPM_CLK_SCC1:
 309                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 310                 shift = 0;
 311                 break;
 312
 313         case CPM_CLK_SCC2:
 314                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 315                 shift = 8;
 316                 break;
 317
 318         case CPM_CLK_SCC3:
 319                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 320                 shift = 16;
 321                 break;
 322
 323         case CPM_CLK_SCC4:
 324                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 325                 shift = 24;
 326                 break;
 327
 328         case CPM_CLK_SMC1:
 329                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 330                 shift = 12;
 331                 break;
 332
 333         case CPM_CLK_SMC2:
 334                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 335                 shift = 28;
 336                 break;
 337
 338         default:
 339                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 340                 return -EINVAL;
 341         }
 342
 343         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 344                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 345                         bits = clk_map[i][2];
 346                         break;
 347                 }
 348         }
 349
 350         if (i == ARRAY_SIZE(clk_map)) {
 351                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 352                 return -EINVAL;
 353         }
 354
 355         bits <<= shift;
 356         mask <<= shift;
 357
 358         if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
 359                 if (mode == CPM_CLK_RTX) {
 360                         bits |= bits << 3;
 361                         mask |= mask << 3;
 362                 } else if (mode == CPM_CLK_RX) {
 363                         bits <<= 3;
 364                         mask <<= 3;
 365                 }
 366         }
 367
 368         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 369
 370         return 0;
 371 }
 372
 373 /*
 374  * GPIO LIB API implementation
 375  */
 376 #ifdef CONFIG_8xx_GPIO
 377
 378 struct cpm1_gpio16_chip {
 379         struct of_mm_gpio_chip mm_gc;
 380         spinlock_t lock;
 381
 382         /* shadowed data register to clear/set bits safely */
 383         u16 cpdata;
 384
 385         /* IRQ associated with Pins when relevant */
 386         int irq[16];
 387 };
 388
 389 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
 390 {
 391         struct cpm1_gpio16_chip *cpm1_gc =
 392                 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
 393         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 394
 395         cpm1_gc->cpdata = in_be16(&iop->dat);
 396 }
 397
 398 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
 399 {
 400         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 401         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 402         u16 pin_mask;
 403
 404         pin_mask = 1 << (15 - gpio);
 405
 406         return !!(in_be16(&iop->dat) & pin_mask);
 407 }
 408
 409 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
 410         int value)
 411 {
 412         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 413         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 414
 415         if (value)
 416                 cpm1_gc->cpdata |= pin_mask;
 417         else
 418                 cpm1_gc->cpdata &= ~pin_mask;
 419
 420         out_be16(&iop->dat, cpm1_gc->cpdata);
 421 }
 422
 423 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
 424 {
 425         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 426         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 427         unsigned long flags;
 428         u16 pin_mask = 1 << (15 - gpio);
 429
 430         spin_lock_irqsave(&cpm1_gc->lock, flags);
 431
 432         __cpm1_gpio16_set(mm_gc, pin_mask, value);
 433
 434         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 435 }
 436
 437 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
 438 {
 439         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 440         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 441
 442         return cpm1_gc->irq[gpio] ? : -ENXIO;
 443 }
 444
 445 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 446 {
 447         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 448         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 449         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 450         unsigned long flags;
 451         u16 pin_mask = 1 << (15 - gpio);
 452
 453         spin_lock_irqsave(&cpm1_gc->lock, flags);
 454
 455         setbits16(&iop->dir, pin_mask);
 456         __cpm1_gpio16_set(mm_gc, pin_mask, val);
 457
 458         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 459
 460         return 0;
 461 }
 462
 463 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
 464 {
 465         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 466         struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 467         struct cpm_ioport16 __iomem *iop = mm_gc->regs;
 468         unsigned long flags;
 469         u16 pin_mask = 1 << (15 - gpio);
 470
 471         spin_lock_irqsave(&cpm1_gc->lock, flags);
 472
 473         clrbits16(&iop->dir, pin_mask);
 474
 475         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 476
 477         return 0;
 478 }
 479
 480 int cpm1_gpiochip_add16(struct device *dev)
 481 {
 482         struct device_node *np = dev->of_node;
 483         struct cpm1_gpio16_chip *cpm1_gc;
 484         struct of_mm_gpio_chip *mm_gc;
 485         struct gpio_chip *gc;
 486         u16 mask;
 487
 488         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 489         if (!cpm1_gc)
 490                 return -ENOMEM;
 491
 492         spin_lock_init(&cpm1_gc->lock);
 493
 494         if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
 495                 int i, j;
 496
 497                 for (i = 0, j = 0; i < 16; i++)
 498                         if (mask & (1 << (15 - i)))
 499                                 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
 500         }
 501
 502         mm_gc = &cpm1_gc->mm_gc;
 503         gc = &mm_gc->gc;
 504
 505         mm_gc->save_regs = cpm1_gpio16_save_regs;
 506         gc->ngpio = 16;
 507         gc->direction_input = cpm1_gpio16_dir_in;
 508         gc->direction_output = cpm1_gpio16_dir_out;
 509         gc->get = cpm1_gpio16_get;
 510         gc->set = cpm1_gpio16_set;
 511         gc->to_irq = cpm1_gpio16_to_irq;
 512         gc->parent = dev;
 513         gc->owner = THIS_MODULE;
 514
 515         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 516 }
 517
 518 struct cpm1_gpio32_chip {
 519         struct of_mm_gpio_chip mm_gc;
 520         spinlock_t lock;
 521
 522         /* shadowed data register to clear/set bits safely */
 523         u32 cpdata;
 524 };
 525
 526 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
 527 {
 528         struct cpm1_gpio32_chip *cpm1_gc =
 529                 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
 530         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 531
 532         cpm1_gc->cpdata = in_be32(&iop->dat);
 533 }
 534
 535 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
 536 {
 537         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 538         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 539         u32 pin_mask;
 540
 541         pin_mask = 1 << (31 - gpio);
 542
 543         return !!(in_be32(&iop->dat) & pin_mask);
 544 }
 545
 546 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
 547         int value)
 548 {
 549         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 550         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 551
 552         if (value)
 553                 cpm1_gc->cpdata |= pin_mask;
 554         else
 555                 cpm1_gc->cpdata &= ~pin_mask;
 556
 557         out_be32(&iop->dat, cpm1_gc->cpdata);
 558 }
 559
 560 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 561 {
 562         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 563         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 564         unsigned long flags;
 565         u32 pin_mask = 1 << (31 - gpio);
 566
 567         spin_lock_irqsave(&cpm1_gc->lock, flags);
 568
 569         __cpm1_gpio32_set(mm_gc, pin_mask, value);
 570
 571         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 572 }
 573
 574 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 575 {
 576         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 577         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 578         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 579         unsigned long flags;
 580         u32 pin_mask = 1 << (31 - gpio);
 581
 582         spin_lock_irqsave(&cpm1_gc->lock, flags);
 583
 584         setbits32(&iop->dir, pin_mask);
 585         __cpm1_gpio32_set(mm_gc, pin_mask, val);
 586
 587         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 588
 589         return 0;
 590 }
 591
 592 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 593 {
 594         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 595         struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
 596         struct cpm_ioport32b __iomem *iop = mm_gc->regs;
 597         unsigned long flags;
 598         u32 pin_mask = 1 << (31 - gpio);
 599
 600         spin_lock_irqsave(&cpm1_gc->lock, flags);
 601
 602         clrbits32(&iop->dir, pin_mask);
 603
 604         spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 605
 606         return 0;
 607 }
 608
 609 int cpm1_gpiochip_add32(struct device *dev)
 610 {
 611         struct device_node *np = dev->of_node;
 612         struct cpm1_gpio32_chip *cpm1_gc;
 613         struct of_mm_gpio_chip *mm_gc;
 614         struct gpio_chip *gc;
 615
 616         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
 617         if (!cpm1_gc)
 618                 return -ENOMEM;
 619
 620         spin_lock_init(&cpm1_gc->lock);
 621
 622         mm_gc = &cpm1_gc->mm_gc;
 623         gc = &mm_gc->gc;
 624
 625         mm_gc->save_regs = cpm1_gpio32_save_regs;
 626         gc->ngpio = 32;
 627         gc->direction_input = cpm1_gpio32_dir_in;
 628         gc->direction_output = cpm1_gpio32_dir_out;
 629         gc->get = cpm1_gpio32_get;
 630         gc->set = cpm1_gpio32_set;
 631         gc->parent = dev;
 632         gc->owner = THIS_MODULE;
 633
 634         return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 635 }
 636
 637 #endif /* CONFIG_8xx_GPIO */