2 * P1022 RDK board specific routines
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Author: Timur Tabi <timur@freescale.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/fsl/guts.h>
16 #include <linux/pci.h>
18 #include <linux/of_address.h>
19 #include <asm/div64.h>
21 #include <asm/swiotlb.h>
23 #include <sysdev/fsl_soc.h>
24 #include <sysdev/fsl_pci.h>
30 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
32 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
33 #define CLKDVDR_PXCKEN 0x80000000
34 #define CLKDVDR_PXCKINV 0x10000000
35 #define CLKDVDR_PXCKDLY 0x06000000
36 #define CLKDVDR_PXCLK_MASK 0x00FF0000
39 * p1022rdk_set_pixel_clock: program the DIU's clock
41 * @pixclock: the wavelength, in picoseconds, of the clock
43 static void p1022rdk_set_pixel_clock(unsigned int pixclock)
45 struct device_node *guts_np = NULL;
46 struct ccsr_guts __iomem *guts;
51 /* Map the global utilities registers. */
52 guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
54 pr_err("p1022rdk: missing global utilities device node\n");
58 guts = of_iomap(guts_np, 0);
61 pr_err("p1022rdk: could not map global utilities device\n");
65 /* Convert pixclock from a wavelength to a frequency */
66 temp = 1000000000000ULL;
67 do_div(temp, pixclock);
71 * 'pxclk' is the ratio of the platform clock to the pixel clock.
72 * This number is programmed into the CLKDVDR register, and the valid
73 * range of values is 2-255.
75 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
76 pxclk = clamp_t(u32, pxclk, 2, 255);
78 /* Disable the pixel clock, and set it to non-inverted and no delay */
79 clrbits32(&guts->clkdvdr,
80 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
82 /* Enable the clock and set the pxclk */
83 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
89 * p1022rdk_valid_monitor_port: set the monitor port for sysfs
91 static enum fsl_diu_monitor_port
92 p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
94 return FSL_DIU_PORT_DVI;
99 static void __init p1022_rdk_pic_init(void)
101 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
102 MPIC_SINGLE_DEST_CPU,
103 0, 256, " OpenPIC ");
104 BUG_ON(mpic == NULL);
109 * Setup the architecture
111 static void __init p1022_rdk_setup_arch(void)
114 ppc_md.progress("p1022_rdk_setup_arch()", 0);
116 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
117 diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
118 diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
123 fsl_pci_assign_primary();
127 pr_info("Freescale / iVeia P1022 RDK reference board\n");
130 machine_arch_initcall(p1022_rdk, mpc85xx_common_publish_devices);
132 define_machine(p1022_rdk) {
134 .compatible = "fsl,p1022rdk",
135 .setup_arch = p1022_rdk_setup_arch,
136 .init_IRQ = p1022_rdk_pic_init,
138 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
139 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
141 .get_irq = mpic_get_irq,
142 .progress = udbg_progress,