1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
6 * Author: Andy Fleming <afleming@freescale.com>
8 * Based on 83xx/mpc8360e_pb.c by:
9 * Li Yang <LeoLi@freescale.com>
10 * Yin Olivia <Hong-hua.Yin@freescale.com>
13 * MPC85xx MDS board specific routines.
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/initrd.h>
28 #include <linux/fsl_devices.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31 #include <linux/phy.h>
32 #include <linux/memblock.h>
33 #include <linux/fsl/guts.h>
35 #include <linux/atomic.h>
38 #include <asm/machdep.h>
39 #include <asm/pci-bridge.h>
41 #include <mm/mmu_decl.h>
44 #include <sysdev/fsl_soc.h>
45 #include <sysdev/fsl_pci.h>
46 #include <sysdev/simple_gpio.h>
47 #include <soc/fsl/qe/qe.h>
48 #include <soc/fsl/qe/qe_ic.h>
50 #include <asm/swiotlb.h>
57 #define DBG(fmt...) udbg_printf(fmt)
62 #if IS_BUILTIN(CONFIG_PHYLIB)
64 #define MV88E1111_SCR 0x10
65 #define MV88E1111_SCR_125CLK 0x0010
66 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
71 /* Workaround for the 125 CLK Toggle */
72 scr = phy_read(phydev, MV88E1111_SCR);
77 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
82 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
87 scr = phy_read(phydev, MV88E1111_SCR);
92 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
97 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
103 err = phy_write(phydev,29, 0x0006);
108 temp = phy_read(phydev, 30);
113 temp = (temp & (~0x8000)) | 0x4000;
114 err = phy_write(phydev,30, temp);
119 err = phy_write(phydev,29, 0x000a);
124 temp = phy_read(phydev, 30);
129 temp = phy_read(phydev, 30);
136 err = phy_write(phydev,30,temp);
141 /* Disable automatic MDI/MDIX selection */
142 temp = phy_read(phydev, 16);
148 err = phy_write(phydev,16,temp);
155 /* ************************************************************************
157 * Setup the architecture
160 #ifdef CONFIG_QUICC_ENGINE
161 static void __init mpc85xx_mds_reset_ucc_phys(void)
163 struct device_node *np;
164 static u8 __iomem *bcsr_regs;
167 np = of_find_node_by_name(NULL, "bcsr");
171 bcsr_regs = of_iomap(np, 0);
176 if (machine_is(mpc8568_mds)) {
177 #define BCSR_UCC1_GETH_EN (0x1 << 7)
178 #define BCSR_UCC2_GETH_EN (0x1 << 7)
179 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
180 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
182 /* Turn off UCC1 & UCC2 */
183 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
184 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
186 /* Mode is RGMII, all bits clear */
187 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
190 /* Turn UCC1 & UCC2 on */
191 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
192 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
193 } else if (machine_is(mpc8569_mds)) {
194 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
195 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
196 #define BCSR_UCC_RGMII (0x1 << 6)
197 #define BCSR_UCC_RTBI (0x1 << 5)
199 * U-Boot mangles interrupt polarity for Marvell PHYs,
200 * so reset built-in and UEM Marvell PHYs, this puts
201 * the PHYs into their normal state.
203 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
206 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
207 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
209 for_each_compatible_node(np, "network", "ucc_geth") {
210 const unsigned int *prop;
213 prop = of_get_property(np, "cell-index", NULL);
219 prop = of_get_property(np, "phy-connection-type", NULL);
223 if (strcmp("rtbi", (const char *)prop) == 0)
224 clrsetbits_8(&bcsr_regs[7 + ucc_num],
225 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
227 } else if (machine_is(p1021_mds)) {
228 #define BCSR11_ENET_MICRST (0x1 << 5)
229 /* Reset Micrel PHY */
230 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
231 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
237 static void __init mpc85xx_mds_qe_init(void)
239 struct device_node *np;
242 mpc85xx_qe_par_io_init();
243 mpc85xx_mds_reset_ucc_phys();
245 if (machine_is(p1021_mds)) {
247 struct ccsr_guts __iomem *guts;
249 np = of_find_node_by_name(NULL, "global-utilities");
251 guts = of_iomap(np, 0);
253 pr_err("mpc85xx-rdb: could not map global utilities register\n");
255 /* P1021 has pins muxed for QE and other functions. To
256 * enable QE UEC mode, we need to set bit QE0 for UCC1
257 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
258 * and QE12 for QE MII management signals in PMUXCR
261 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
262 MPC85xx_PMUXCR_QE(3) |
263 MPC85xx_PMUXCR_QE(9) |
264 MPC85xx_PMUXCR_QE(12));
273 static void __init mpc85xx_mds_qeic_init(void)
275 struct device_node *np;
277 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
278 if (!of_device_is_available(np)) {
283 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
285 np = of_find_node_by_type(NULL, "qeic");
290 if (machine_is(p1021_mds))
291 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
292 qe_ic_cascade_high_mpic);
294 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
298 static void __init mpc85xx_mds_qe_init(void) { }
299 static void __init mpc85xx_mds_qeic_init(void) { }
300 #endif /* CONFIG_QUICC_ENGINE */
302 static void __init mpc85xx_mds_setup_arch(void)
305 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
309 mpc85xx_mds_qe_init();
311 fsl_pci_assign_primary();
316 #if IS_BUILTIN(CONFIG_PHYLIB)
318 static int __init board_fixups(void)
321 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
322 struct device_node *mdio;
326 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
327 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
329 of_address_to_resource(mdio, 0, &res);
330 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
331 (unsigned long long)res.start, 1);
333 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
334 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
336 /* Register a workaround for errata */
337 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
338 (unsigned long long)res.start, 7);
339 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
347 machine_arch_initcall(mpc8568_mds, board_fixups);
348 machine_arch_initcall(mpc8569_mds, board_fixups);
352 static int __init mpc85xx_publish_devices(void)
354 if (machine_is(mpc8568_mds))
355 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
356 if (machine_is(mpc8569_mds))
357 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
359 return mpc85xx_common_publish_devices();
362 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
363 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
364 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
366 static void __init mpc85xx_mds_pic_init(void)
368 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
369 MPIC_SINGLE_DEST_CPU,
370 0, 256, " OpenPIC ");
371 BUG_ON(mpic == NULL);
374 mpc85xx_mds_qeic_init();
377 static int __init mpc85xx_mds_probe(void)
379 return of_machine_is_compatible("MPC85xxMDS");
382 define_machine(mpc8568_mds) {
383 .name = "MPC8568 MDS",
384 .probe = mpc85xx_mds_probe,
385 .setup_arch = mpc85xx_mds_setup_arch,
386 .init_IRQ = mpc85xx_mds_pic_init,
387 .get_irq = mpic_get_irq,
388 .calibrate_decr = generic_calibrate_decr,
389 .progress = udbg_progress,
391 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
392 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
396 static int __init mpc8569_mds_probe(void)
398 return of_machine_is_compatible("fsl,MPC8569EMDS");
401 define_machine(mpc8569_mds) {
402 .name = "MPC8569 MDS",
403 .probe = mpc8569_mds_probe,
404 .setup_arch = mpc85xx_mds_setup_arch,
405 .init_IRQ = mpc85xx_mds_pic_init,
406 .get_irq = mpic_get_irq,
407 .calibrate_decr = generic_calibrate_decr,
408 .progress = udbg_progress,
410 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
411 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
415 static int __init p1021_mds_probe(void)
417 return of_machine_is_compatible("fsl,P1021MDS");
421 define_machine(p1021_mds) {
423 .probe = p1021_mds_probe,
424 .setup_arch = mpc85xx_mds_setup_arch,
425 .init_IRQ = mpc85xx_mds_pic_init,
426 .get_irq = mpic_get_irq,
427 .calibrate_decr = generic_calibrate_decr,
428 .progress = udbg_progress,
430 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
431 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,