2 * Corenet based SoC DS Setup
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2009-2011 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
21 #include <asm/machdep.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/pgtable.h>
24 #include <asm/ppc-pci.h>
25 #include <mm/mmu_decl.h>
29 #include <asm/ehv_pic.h>
30 #include <soc/fsl/qe/qe_ic.h>
32 #include <linux/of_platform.h>
33 #include <sysdev/fsl_soc.h>
34 #include <sysdev/fsl_pci.h>
38 void __init corenet_gen_pic_init(void)
41 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
44 struct device_node *np;
46 if (ppc_md.get_irq == mpic_get_coreint_irq)
47 flags |= MPIC_ENABLE_COREINT;
49 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
54 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
56 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
57 qe_ic_cascade_high_mpic);
63 * Setup the architecture
65 void __init corenet_gen_setup_arch(void)
71 #if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
73 * Inbound windows don't cover the full lower 4 GiB
74 * due to conflicts with PCICSRBAR and outbound windows,
75 * so limit the DMA32 zone to 2 GiB, to allow consistent
76 * allocations to succeed.
78 limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
81 pr_info("%s board\n", ppc_md.name);
86 static const struct of_device_id of_device_ids[] = {
88 .compatible = "simple-bus"
91 .compatible = "mdio-mux-gpio"
94 .compatible = "fsl,fpga-ngpixis"
97 .compatible = "fsl,fpga-qixis"
100 .compatible = "fsl,srio",
103 .compatible = "fsl,p4080-pcie",
106 .compatible = "fsl,qoriq-pcie-v2.2",
109 .compatible = "fsl,qoriq-pcie-v2.3",
112 .compatible = "fsl,qoriq-pcie-v2.4",
115 .compatible = "fsl,qoriq-pcie-v3.0",
118 .compatible = "fsl,qe",
120 /* The following two are for the Freescale hypervisor */
122 .name = "hypervisor",
130 int __init corenet_gen_publish_devices(void)
132 return of_platform_bus_probe(NULL, of_device_ids, NULL);
135 static const char * const boards[] __initconst = {
167 * Called very early, device-tree isn't unflattened
169 static int __init corenet_generic_probe(void)
174 extern struct smp_ops_t smp_85xx_ops;
177 if (of_device_compatible_match(of_root, boards))
180 /* Check if we're running under the Freescale hypervisor */
181 for (i = 0; boards[i]; i++) {
182 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
183 if (of_machine_is_compatible(hv_compat)) {
184 ppc_md.init_IRQ = ehv_pic_init;
186 ppc_md.get_irq = ehv_pic_get_irq;
187 ppc_md.restart = fsl_hv_restart;
188 pm_power_off = fsl_hv_halt;
189 ppc_md.halt = fsl_hv_halt;
192 * Disable the timebase sync operations because we
193 * can't write to the timebase registers under the
196 smp_85xx_ops.give_timebase = NULL;
197 smp_85xx_ops.take_timebase = NULL;
206 define_machine(corenet_generic) {
207 .name = "CoreNet Generic",
208 .probe = corenet_generic_probe,
209 .setup_arch = corenet_gen_setup_arch,
210 .init_IRQ = corenet_gen_pic_init,
212 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
213 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
216 * Core reset may cause issues if using the proxy mode of MPIC.
217 * So, use the mixed mode of MPIC if enabling CPU hotplug.
219 * Likewise, problems have been seen with kexec when coreint is enabled.
221 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
222 .get_irq = mpic_get_irq,
224 .get_irq = mpic_get_coreint_irq,
226 .calibrate_decr = generic_calibrate_decr,
227 .progress = udbg_progress,
229 .power_save = book3e_idle,
231 .power_save = e500_idle,
235 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
237 #ifdef CONFIG_SWIOTLB
238 machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);