1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Corenet based SoC DS Setup
5 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
7 * Copyright 2009-2011 Freescale Semiconductor Inc.
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/kdev_t.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
17 #include <asm/machdep.h>
18 #include <asm/pci-bridge.h>
19 #include <asm/pgtable.h>
20 #include <asm/ppc-pci.h>
21 #include <mm/mmu_decl.h>
25 #include <asm/ehv_pic.h>
26 #include <asm/swiotlb.h>
27 #include <soc/fsl/qe/qe_ic.h>
29 #include <linux/of_platform.h>
30 #include <sysdev/fsl_soc.h>
31 #include <sysdev/fsl_pci.h>
35 void __init corenet_gen_pic_init(void)
38 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
41 struct device_node *np;
43 if (ppc_md.get_irq == mpic_get_coreint_irq)
44 flags |= MPIC_ENABLE_COREINT;
46 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
51 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
53 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
54 qe_ic_cascade_high_mpic);
60 * Setup the architecture
62 void __init corenet_gen_setup_arch(void)
68 pr_info("%s board\n", ppc_md.name);
73 static const struct of_device_id of_device_ids[] = {
75 .compatible = "simple-bus"
78 .compatible = "mdio-mux-gpio"
81 .compatible = "fsl,fpga-ngpixis"
84 .compatible = "fsl,fpga-qixis"
87 .compatible = "fsl,srio",
90 .compatible = "fsl,p4080-pcie",
93 .compatible = "fsl,qoriq-pcie-v2.2",
96 .compatible = "fsl,qoriq-pcie-v2.3",
99 .compatible = "fsl,qoriq-pcie-v2.4",
102 .compatible = "fsl,qoriq-pcie-v3.0",
105 .compatible = "fsl,qe",
107 /* The following two are for the Freescale hypervisor */
109 .name = "hypervisor",
117 int __init corenet_gen_publish_devices(void)
119 return of_platform_bus_probe(NULL, of_device_ids, NULL);
122 static const char * const boards[] __initconst = {
154 * Called very early, device-tree isn't unflattened
156 static int __init corenet_generic_probe(void)
161 extern struct smp_ops_t smp_85xx_ops;
164 if (of_device_compatible_match(of_root, boards))
167 /* Check if we're running under the Freescale hypervisor */
168 for (i = 0; boards[i]; i++) {
169 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
170 if (of_machine_is_compatible(hv_compat)) {
171 ppc_md.init_IRQ = ehv_pic_init;
173 ppc_md.get_irq = ehv_pic_get_irq;
174 ppc_md.restart = fsl_hv_restart;
175 pm_power_off = fsl_hv_halt;
176 ppc_md.halt = fsl_hv_halt;
179 * Disable the timebase sync operations because we
180 * can't write to the timebase registers under the
183 smp_85xx_ops.give_timebase = NULL;
184 smp_85xx_ops.take_timebase = NULL;
193 define_machine(corenet_generic) {
194 .name = "CoreNet Generic",
195 .probe = corenet_generic_probe,
196 .setup_arch = corenet_gen_setup_arch,
197 .init_IRQ = corenet_gen_pic_init,
199 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
200 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
203 * Core reset may cause issues if using the proxy mode of MPIC.
204 * So, use the mixed mode of MPIC if enabling CPU hotplug.
206 * Likewise, problems have been seen with kexec when coreint is enabled.
208 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
209 .get_irq = mpic_get_irq,
211 .get_irq = mpic_get_coreint_irq,
213 .calibrate_decr = generic_calibrate_decr,
214 .progress = udbg_progress,
216 .power_save = book3e_idle,
218 .power_save = e500_idle,
222 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);