1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Corenet based SoC DS Setup
5 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
7 * Copyright 2009-2011 Freescale Semiconductor Inc.
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/kdev_t.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/pgtable.h>
18 #include <asm/machdep.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/ppc-pci.h>
21 #include <mm/mmu_decl.h>
25 #include <asm/ehv_pic.h>
26 #include <asm/swiotlb.h>
28 #include <linux/of_platform.h>
29 #include <sysdev/fsl_soc.h>
30 #include <sysdev/fsl_pci.h>
34 void __init corenet_gen_pic_init(void)
37 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
40 if (ppc_md.get_irq == mpic_get_coreint_irq)
41 flags |= MPIC_ENABLE_COREINT;
43 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
50 * Setup the architecture
52 void __init corenet_gen_setup_arch(void)
58 pr_info("%s board\n", ppc_md.name);
61 static const struct of_device_id of_device_ids[] = {
63 .compatible = "simple-bus"
66 .compatible = "mdio-mux-gpio"
69 .compatible = "fsl,fpga-ngpixis"
72 .compatible = "fsl,fpga-qixis"
75 .compatible = "fsl,srio",
78 .compatible = "fsl,p4080-pcie",
81 .compatible = "fsl,qoriq-pcie-v2.2",
84 .compatible = "fsl,qoriq-pcie-v2.3",
87 .compatible = "fsl,qoriq-pcie-v2.4",
90 .compatible = "fsl,qoriq-pcie-v3.0",
93 .compatible = "fsl,qe",
95 /* The following two are for the Freescale hypervisor */
105 int __init corenet_gen_publish_devices(void)
107 return of_platform_bus_probe(NULL, of_device_ids, NULL);
110 static const char * const boards[] __initconst = {
142 * Called very early, device-tree isn't unflattened
144 static int __init corenet_generic_probe(void)
149 extern struct smp_ops_t smp_85xx_ops;
152 if (of_device_compatible_match(of_root, boards))
155 /* Check if we're running under the Freescale hypervisor */
156 for (i = 0; boards[i]; i++) {
157 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
158 if (of_machine_is_compatible(hv_compat)) {
159 ppc_md.init_IRQ = ehv_pic_init;
161 ppc_md.get_irq = ehv_pic_get_irq;
162 ppc_md.restart = fsl_hv_restart;
163 pm_power_off = fsl_hv_halt;
164 ppc_md.halt = fsl_hv_halt;
167 * Disable the timebase sync operations because we
168 * can't write to the timebase registers under the
171 smp_85xx_ops.give_timebase = NULL;
172 smp_85xx_ops.take_timebase = NULL;
181 define_machine(corenet_generic) {
182 .name = "CoreNet Generic",
183 .probe = corenet_generic_probe,
184 .setup_arch = corenet_gen_setup_arch,
185 .init_IRQ = corenet_gen_pic_init,
187 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
188 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
191 * Core reset may cause issues if using the proxy mode of MPIC.
192 * So, use the mixed mode of MPIC if enabling CPU hotplug.
194 * Likewise, problems have been seen with kexec when coreint is enabled.
196 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
197 .get_irq = mpic_get_irq,
199 .get_irq = mpic_get_coreint_irq,
201 .calibrate_decr = generic_calibrate_decr,
202 .progress = udbg_progress,
204 .power_save = book3e_idle,
206 .power_save = e500_idle,
210 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);