1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale 83xx USB SOC setup code
5 * Copyright (C) 2007 Freescale Semiconductor, Inc.
10 #include <linux/stddef.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
14 #include <linux/of_address.h>
17 #include <sysdev/fsl_soc.h>
22 #ifdef CONFIG_PPC_MPC834x
23 int __init mpc834x_usb_cfg(void)
25 unsigned long sccr, sicrl, sicrh;
27 struct device_node *np = NULL;
28 int port0_is_dr = 0, port1_is_dr = 0;
29 const void *prop, *dr_mode;
31 immap = ioremap(get_immrbase(), 0x1000);
36 /* Note: DR and MPH must use the same clock setting in SCCR */
37 sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK;
38 sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK;
39 sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI;
41 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
43 sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */
45 prop = of_get_property(np, "phy_type", NULL);
47 if (prop && (!strcmp(prop, "utmi") ||
48 !strcmp(prop, "utmi_wide"))) {
49 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
50 sicrh |= MPC834X_SICRH_USB_UTMI;
52 } else if (prop && !strcmp(prop, "serial")) {
53 dr_mode = of_get_property(np, "dr_mode", NULL);
54 if (dr_mode && !strcmp(dr_mode, "otg")) {
55 sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1;
58 sicrl |= MPC834X_SICRL_USB1;
60 } else if (prop && !strcmp(prop, "ulpi")) {
61 sicrl |= MPC834X_SICRL_USB1;
63 printk(KERN_WARNING "834x USB PHY type not supported\n");
67 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph");
69 sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */
71 prop = of_get_property(np, "port0", NULL);
75 "834x USB port0 can't be used by both DR and MPH!\n");
76 sicrl &= ~MPC834X_SICRL_USB0;
78 prop = of_get_property(np, "port1", NULL);
82 "834x USB port1 can't be used by both DR and MPH!\n");
83 sicrl &= ~MPC834X_SICRL_USB1;
89 out_be32(immap + MPC83XX_SCCR_OFFS, sccr);
90 out_be32(immap + MPC83XX_SICRL_OFFS, sicrl);
91 out_be32(immap + MPC83XX_SICRH_OFFS, sicrh);
96 #endif /* CONFIG_PPC_MPC834x */
98 #ifdef CONFIG_PPC_MPC831x
99 int __init mpc831x_usb_cfg(void)
102 void __iomem *immap, *usb_regs;
103 struct device_node *np = NULL;
104 struct device_node *immr_node = NULL;
108 #ifdef CONFIG_USB_OTG
112 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
115 prop = of_get_property(np, "phy_type", NULL);
117 /* Map IMMR space for pin and clock settings */
118 immap = ioremap(get_immrbase(), 0x1000);
124 /* Configure clock */
125 immr_node = of_get_parent(np);
126 if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") ||
127 of_device_is_compatible(immr_node, "fsl,mpc8308-immr")))
128 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
129 MPC8315_SCCR_USB_MASK,
130 MPC8315_SCCR_USB_DRCM_01);
132 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
133 MPC83XX_SCCR_USB_MASK,
134 MPC83XX_SCCR_USB_DRCM_11);
136 /* Configure pin mux for ULPI. There is no pin mux for UTMI */
137 if (prop && !strcmp(prop, "ulpi")) {
138 if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
139 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
140 MPC8308_SICRH_USB_MASK,
141 MPC8308_SICRH_USB_ULPI);
142 } else if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
143 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
144 MPC8315_SICRL_USB_MASK,
145 MPC8315_SICRL_USB_ULPI);
146 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
147 MPC8315_SICRH_USB_MASK,
148 MPC8315_SICRH_USB_ULPI);
150 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
151 MPC831X_SICRL_USB_MASK,
152 MPC831X_SICRL_USB_ULPI);
153 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
154 MPC831X_SICRH_USB_MASK,
155 MPC831X_SICRH_USB_ULPI);
161 of_node_put(immr_node);
163 /* Map USB SOC space */
164 ret = of_address_to_resource(np, 0, &res);
169 usb_regs = ioremap(res.start, resource_size(&res));
171 /* Using on-chip PHY */
172 if (prop && (!strcmp(prop, "utmi_wide") ||
173 !strcmp(prop, "utmi"))) {
176 if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))
179 if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
180 refsel = CONTROL_REFSEL_24MHZ;
182 refsel = CONTROL_REFSEL_48MHZ;
183 /* Set UTMI_PHY_EN and REFSEL */
184 out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
185 CONTROL_UTMI_PHY_EN | refsel);
186 /* Using external UPLI PHY */
187 } else if (prop && !strcmp(prop, "ulpi")) {
188 /* Set PHY_CLK_SEL to ULPI */
189 temp = CONTROL_PHY_CLK_SEL_ULPI;
190 #ifdef CONFIG_USB_OTG
192 if (!of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
193 dr_mode = of_get_property(np, "dr_mode", NULL);
194 if (dr_mode && !strcmp(dr_mode, "otg"))
195 temp |= CONTROL_OTG_PORT;
197 #endif /* CONFIG_USB_OTG */
198 out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp);
200 printk(KERN_WARNING "831x USB PHY type not supported\n");
209 #endif /* CONFIG_PPC_MPC831x */
211 #ifdef CONFIG_PPC_MPC837x
212 int __init mpc837x_usb_cfg(void)
215 struct device_node *np = NULL;
219 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
220 if (!np || !of_device_is_available(np)) {
224 prop = of_get_property(np, "phy_type", NULL);
226 if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
227 printk(KERN_WARNING "837x USB PHY type not supported\n");
232 /* Map IMMR space for pin and clock settings */
233 immap = ioremap(get_immrbase(), 0x1000);
239 /* Configure clock */
240 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
241 MPC837X_SCCR_USB_DRCM_11);
243 /* Configure pin mux for ULPI/serial */
244 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
245 MPC837X_SICRL_USB_ULPI);
251 #endif /* CONFIG_PPC_MPC837x */