arch/powerpc/platforms/83xx/mpc832x_rdb.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * arch/powerpc/platforms/83xx/mpc832x_rdb.c
   4  *
   5  * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
   6  *
   7  * Description:
   8  * MPC832x RDB board specific routines.
   9  * This file is based on mpc832x_mds.c and mpc8313_rdb.c
  10  * Author: Michael Barkowski <michael.barkowski@freescale.com>
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/spi/mmc_spi.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/fsl_devices.h>
  23
  24 #include <asm/time.h>
  25 #include <asm/ipic.h>
  26 #include <asm/udbg.h>
  27 #include <soc/fsl/qe/qe.h>
  28 #include <sysdev/fsl_soc.h>
  29 #include <sysdev/fsl_pci.h>
  30
  31 #include "mpc83xx.h"
  32
  33 #undef DEBUG
  34 #ifdef DEBUG
  35 #define DBG(fmt...) udbg_printf(fmt)
  36 #else
  37 #define DBG(fmt...)
  38 #endif
  39
  40 #ifdef CONFIG_QUICC_ENGINE
  41 static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
  42                                    struct spi_board_info *board_infos,
  43                                    unsigned int num_board_infos,
  44                                    void (*cs_control)(struct spi_device *dev,
  45                                                       bool on))
  46 {
  47         struct device_node *np;
  48         unsigned int i = 0;
  49
  50         for_each_compatible_node(np, type, compatible) {
  51                 int ret;
  52                 unsigned int j;
  53                 const void *prop;
  54                 struct resource res[2];
  55                 struct platform_device *pdev;
  56                 struct fsl_spi_platform_data pdata = {
  57                         .cs_control = cs_control,
  58                 };
  59
  60                 memset(res, 0, sizeof(res));
  61
  62                 pdata.sysclk = sysclk;
  63
  64                 prop = of_get_property(np, "reg", NULL);
  65                 if (!prop)
  66                         goto err;
  67                 pdata.bus_num = *(u32 *)prop;
  68
  69                 prop = of_get_property(np, "cell-index", NULL);
  70                 if (prop)
  71                         i = *(u32 *)prop;
  72
  73                 prop = of_get_property(np, "mode", NULL);
  74                 if (prop && !strcmp(prop, "cpu-qe"))
  75                         pdata.flags = SPI_QE_CPU_MODE;
  76
  77                 for (j = 0; j < num_board_infos; j++) {
  78                         if (board_infos[j].bus_num == pdata.bus_num)
  79                                 pdata.max_chipselect++;
  80                 }
  81
  82                 if (!pdata.max_chipselect)
  83                         continue;
  84
  85                 ret = of_address_to_resource(np, 0, &res[0]);
  86                 if (ret)
  87                         goto err;
  88
  89                 ret = of_irq_to_resource(np, 0, &res[1]);
  90                 if (ret <= 0)
  91                         goto err;
  92
  93                 pdev = platform_device_alloc("mpc83xx_spi", i);
  94                 if (!pdev)
  95                         goto err;
  96
  97                 ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
  98                 if (ret)
  99                         goto unreg;
 100
 101                 ret = platform_device_add_resources(pdev, res,
 102                                                     ARRAY_SIZE(res));
 103                 if (ret)
 104                         goto unreg;
 105
 106                 ret = platform_device_add(pdev);
 107                 if (ret)
 108                         goto unreg;
 109
 110                 goto next;
 111 unreg:
 112                 platform_device_put(pdev);
 113 err:
 114                 pr_err("%pOF: registration failed\n", np);
 115 next:
 116                 i++;
 117         }
 118
 119         return i;
 120 }
 121
 122 static int __init fsl_spi_init(struct spi_board_info *board_infos,
 123                                unsigned int num_board_infos,
 124                                void (*cs_control)(struct spi_device *spi,
 125                                                   bool on))
 126 {
 127         u32 sysclk = -1;
 128         int ret;
 129
 130         /* SPI controller is either clocked from QE or SoC clock */
 131         sysclk = get_brgfreq();
 132         if (sysclk == -1) {
 133                 sysclk = fsl_get_sys_freq();
 134                 if (sysclk == -1)
 135                         return -ENODEV;
 136         }
 137
 138         ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
 139                                num_board_infos, cs_control);
 140         if (!ret)
 141                 of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
 142                                  num_board_infos, cs_control);
 143
 144         return spi_register_board_info(board_infos, num_board_infos);
 145 }
 146
 147 static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
 148 {
 149         pr_debug("%s %d %d\n", __func__, spi_get_chipselect(spi, 0), on);
 150         par_io_data_set(3, 13, on);
 151 }
 152
 153 static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
 154         .ocr_mask = MMC_VDD_33_34,
 155 };
 156
 157 static struct spi_board_info mpc832x_spi_boardinfo = {
 158         .bus_num = 0x4c0,
 159         .chip_select = 0,
 160         .max_speed_hz = 50000000,
 161         .modalias = "mmc_spi",
 162         .platform_data = &mpc832x_mmc_pdata,
 163 };
 164
 165 static int __init mpc832x_spi_init(void)
 166 {
 167         struct device_node *np;
 168
 169         par_io_config_pin(3,  0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
 170         par_io_config_pin(3,  1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
 171         par_io_config_pin(3,  2, 3, 0, 1, 0); /* SPI1 CLK,  I/O */
 172         par_io_config_pin(3,  3, 2, 0, 1, 0); /* SPI1 SEL,  I   */
 173
 174         par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS,    O */
 175         par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
 176         par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
 177
 178         /*
 179          * Don't bother with legacy stuff when device tree contains
 180          * mmc-spi-slot node.
 181          */
 182         np = of_find_compatible_node(NULL, NULL, "mmc-spi-slot");
 183         of_node_put(np);
 184         if (np)
 185                 return 0;
 186         return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_cs_control);
 187 }
 188 machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
 189 #endif /* CONFIG_QUICC_ENGINE */
 190
 191 /* ************************************************************************
 192  *
 193  * Setup the architecture
 194  *
 195  */
 196 static void __init mpc832x_rdb_setup_arch(void)
 197 {
 198 #if defined(CONFIG_QUICC_ENGINE)
 199         struct device_node *np;
 200 #endif
 201
 202         mpc83xx_setup_arch();
 203
 204 #ifdef CONFIG_QUICC_ENGINE
 205         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 206                 par_io_init(np);
 207                 of_node_put(np);
 208
 209                 for_each_node_by_name(np, "ucc")
 210                         par_io_of_config(np);
 211         }
 212 #endif                          /* CONFIG_QUICC_ENGINE */
 213 }
 214
 215 machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
 216
 217 define_machine(mpc832x_rdb) {
 218         .name           = "MPC832x RDB",
 219         .compatible     = "MPC832xRDB",
 220         .setup_arch     = mpc832x_rdb_setup_arch,
 221         .discover_phbs  = mpc83xx_setup_pci,
 222         .init_IRQ       = mpc83xx_ipic_init_IRQ,
 223         .get_irq        = ipic_get_irq,
 224         .restart        = mpc83xx_restart,
 225         .time_init      = mpc83xx_time_init,
 226         .progress       = udbg_progress,
 227 };