2 * misc setup functions for MPC83xx
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/stddef.h>
13 #include <linux/kernel.h>
14 #include <linux/of_platform.h>
15 #include <linux/pci.h>
17 #include <asm/debug.h>
19 #include <asm/hw_irq.h>
21 #include <soc/fsl/qe/qe_ic.h>
22 #include <sysdev/fsl_soc.h>
23 #include <sysdev/fsl_pci.h>
27 static __be32 __iomem *restart_reg_base;
29 static int __init mpc83xx_restart_init(void)
31 /* map reset restart_reg_baseister space */
32 restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
37 arch_initcall(mpc83xx_restart_init);
39 void __noreturn mpc83xx_restart(char *cmd)
41 #define RST_OFFSET 0x00000900
42 #define RST_PROT_REG 0x00000018
43 #define RST_CTRL_REG 0x0000001c
47 if (restart_reg_base) {
48 /* enable software reset "RSTE" */
49 out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
51 /* set software hard reset */
52 out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
54 printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
60 long __init mpc83xx_time_init(void)
62 #define SPCR_OFFSET 0x00000110
63 #define SPCR_TBEN 0x00400000
64 __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
68 out_be32(spcr, tmp | SPCR_TBEN);
75 void __init mpc83xx_ipic_init_IRQ(void)
77 struct device_node *np;
79 /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
80 np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
82 np = of_find_node_by_type(NULL, "ipic");
90 /* Initialize the default interrupt mapping priorities,
91 * in case the boot rom changed something on us.
93 ipic_set_default_priority();
96 #ifdef CONFIG_QUICC_ENGINE
97 void __init mpc83xx_qe_init_IRQ(void)
99 struct device_node *np;
101 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
103 np = of_find_node_by_type(NULL, "qeic");
107 qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
111 void __init mpc83xx_ipic_and_qe_init_IRQ(void)
113 mpc83xx_ipic_init_IRQ();
114 mpc83xx_qe_init_IRQ();
116 #endif /* CONFIG_QUICC_ENGINE */
118 static const struct of_device_id of_bus_ids[] __initconst = {
120 { .compatible = "soc", },
121 { .compatible = "simple-bus" },
122 { .compatible = "gianfar" },
123 { .compatible = "gpio-leds", },
125 { .compatible = "fsl,qe", },
129 int __init mpc83xx_declare_of_platform_devices(void)
131 of_platform_bus_probe(NULL, of_bus_ids, NULL);
136 void __init mpc83xx_setup_pci(void)
138 struct device_node *np;
140 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
141 mpc83xx_add_bridge(np);
142 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
143 mpc83xx_add_bridge(np);
147 void __init mpc83xx_setup_arch(void)
150 ppc_md.progress("mpc83xx_setup_arch()", 0);
155 int machine_check_83xx(struct pt_regs *regs)
157 u32 mask = 1 << (31 - IPIC_MCP_WDT);
159 if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
160 return machine_check_generic(regs);
161 ipic_clear_mcp_status(mask);
163 if (debugger_fault_handler(regs))
166 die("Watchdog NMI Reset", regs, 0);