1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2008 Harris Corporation
6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7 * Copyright (c) MontaVista Software, Inc. 2008.
9 * Author: Steve Falco <sfalco@harris.com>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
17 #include <linux/gpio/legacy-of-mm-gpiochip.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/types.h>
20 #include <linux/slab.h>
22 #define GPIO_MASK(gpio) (0x80000000 >> (gpio))
23 #define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2))
25 /* Physical GPIO register layout */
47 struct ppc4xx_gpio_chip {
48 struct of_mm_gpio_chip mm_gc;
53 * GPIO LIB API implementation for GPIOs
55 * There are a maximum of 32 gpios in each gpio controller.
58 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
60 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
61 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
63 return !!(in_be32(®s->ir) & GPIO_MASK(gpio));
67 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
69 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
70 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
73 setbits32(®s->or, GPIO_MASK(gpio));
75 clrbits32(®s->or, GPIO_MASK(gpio));
79 ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
81 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
84 spin_lock_irqsave(&chip->lock, flags);
86 __ppc4xx_gpio_set(gc, gpio, val);
88 spin_unlock_irqrestore(&chip->lock, flags);
90 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
93 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
95 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
96 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
97 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
100 spin_lock_irqsave(&chip->lock, flags);
102 /* Disable open-drain function */
103 clrbits32(®s->odr, GPIO_MASK(gpio));
106 clrbits32(®s->tcr, GPIO_MASK(gpio));
108 /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
110 clrbits32(®s->osrl, GPIO_MASK2(gpio));
111 clrbits32(®s->tsrl, GPIO_MASK2(gpio));
113 clrbits32(®s->osrh, GPIO_MASK2(gpio));
114 clrbits32(®s->tsrh, GPIO_MASK2(gpio));
117 spin_unlock_irqrestore(&chip->lock, flags);
123 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
125 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
126 struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
127 struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
130 spin_lock_irqsave(&chip->lock, flags);
132 /* First set initial value */
133 __ppc4xx_gpio_set(gc, gpio, val);
135 /* Disable open-drain function */
136 clrbits32(®s->odr, GPIO_MASK(gpio));
139 setbits32(®s->tcr, GPIO_MASK(gpio));
141 /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
143 clrbits32(®s->osrl, GPIO_MASK2(gpio));
144 clrbits32(®s->tsrl, GPIO_MASK2(gpio));
146 clrbits32(®s->osrh, GPIO_MASK2(gpio));
147 clrbits32(®s->tsrh, GPIO_MASK2(gpio));
150 spin_unlock_irqrestore(&chip->lock, flags);
152 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
157 static int __init ppc4xx_add_gpiochips(void)
159 struct device_node *np;
161 for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
163 struct ppc4xx_gpio_chip *ppc4xx_gc;
164 struct of_mm_gpio_chip *mm_gc;
165 struct gpio_chip *gc;
167 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
173 spin_lock_init(&ppc4xx_gc->lock);
175 mm_gc = &ppc4xx_gc->mm_gc;
179 gc->direction_input = ppc4xx_gpio_dir_in;
180 gc->direction_output = ppc4xx_gpio_dir_out;
181 gc->get = ppc4xx_gpio_get;
182 gc->set = ppc4xx_gpio_set;
184 ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc);
189 pr_err("%pOF: registration failed with status %d\n", np, ret);
191 /* try others anyway */
195 arch_initcall(ppc4xx_add_gpiochips);