GNU Linux-libre 4.14.266-gnu1
[releases.git] / arch / powerpc / perf / power9-pmu.c
1 /*
2  * Performance counter support for POWER9 processors.
3  *
4  * Copyright 2009 Paul Mackerras, IBM Corporation.
5  * Copyright 2013 Michael Ellerman, IBM Corporation.
6  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version
11  * 2 of the License, or later version.
12  */
13
14 #define pr_fmt(fmt)     "power9-pmu: " fmt
15
16 #include "isa207-common.h"
17
18 /*
19  * Raw event encoding for Power9:
20  *
21  *        60        56        52        48        44        40        36        32
22  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
23  *   | | [ ]                       [ ] [      thresh_cmp     ]   [  thresh_ctl   ]
24  *   | |  |                         |                                     |
25  *   | |  *- IFM (Linux)            |                  thresh start/stop -*
26  *   | *- BHRB (Linux)              *sm
27  *   *- EBB (Linux)
28  *
29  *        28        24        20        16        12         8         4         0
30  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
31  *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   []    m   [    pmcxsel    ]
32  *     |        |           |                          |     |
33  *     |        |           |                          |     *- mark
34  *     |        |           *- L1/L2/L3 cache_sel      |
35  *     |        |                                      |
36  *     |        *- sampling mode for marked events     *- combine
37  *     |
38  *     *- thresh_sel
39  *
40  * Below uses IBM bit numbering.
41  *
42  * MMCR1[x:y] = unit    (PMCxUNIT)
43  * MMCR1[24]   = pmc1combine[0]
44  * MMCR1[25]   = pmc1combine[1]
45  * MMCR1[26]   = pmc2combine[0]
46  * MMCR1[27]   = pmc2combine[1]
47  * MMCR1[28]   = pmc3combine[0]
48  * MMCR1[29]   = pmc3combine[1]
49  * MMCR1[30]   = pmc4combine[0]
50  * MMCR1[31]   = pmc4combine[1]
51  *
52  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
53  *      MMCR1[20:27] = thresh_ctl
54  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
55  *      MMCR1[20:27] = thresh_ctl
56  * else
57  *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
58  *
59  * if thresh_sel:
60  *      MMCRA[45:47] = thresh_sel
61  *
62  * if thresh_cmp:
63  *      MMCRA[9:11] = thresh_cmp[0:2]
64  *      MMCRA[12:18] = thresh_cmp[3:9]
65  *
66  * if unit == 6 or unit == 7
67  *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
68  * else if unit == 8 or unit == 9:
69  *      if cache_sel[0] == 0: # L3 bank
70  *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
71  *      else if cache_sel[0] == 1:
72  *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
73  * else if cache_sel[1]: # L1 event
74  *      MMCR1[16] = cache_sel[2]
75  *     MMCR1[17] = cache_sel[3]
76  *
77  * if mark:
78  *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
79  *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
80  *     MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
81  *
82  * if EBB and BHRB:
83  *      MMCRA[32:33] = IFM
84  *
85  * MMCRA[SDAR_MODE]  = sm
86  */
87
88 /*
89  * Some power9 event codes.
90  */
91 #define EVENT(_name, _code)     _name = _code,
92
93 enum {
94 #include "power9-events-list.h"
95 };
96
97 #undef EVENT
98
99 /* MMCRA IFM bits - POWER9 */
100 #define POWER9_MMCRA_IFM1               0x0000000040000000UL
101 #define POWER9_MMCRA_IFM2               0x0000000080000000UL
102 #define POWER9_MMCRA_IFM3               0x00000000C0000000UL
103 #define POWER9_MMCRA_BHRB_MASK          0x00000000C0000000UL
104
105 /* PowerISA v2.07 format attribute structure*/
106 extern struct attribute_group isa207_pmu_format_group;
107
108 /* Table of alternatives, sorted by column 0 */
109 static const unsigned int power9_event_alternatives[][MAX_ALT] = {
110         { PM_INST_DISP,                 PM_INST_DISP_ALT },
111         { PM_RUN_CYC_ALT,               PM_RUN_CYC },
112         { PM_RUN_INST_CMPL_ALT,         PM_RUN_INST_CMPL },
113         { PM_LD_MISS_L1,                PM_LD_MISS_L1_ALT },
114         { PM_BR_2PATH,                  PM_BR_2PATH_ALT },
115 };
116
117 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
118 {
119         int num_alt = 0;
120
121         num_alt = isa207_get_alternatives(event, alt,
122                                           ARRAY_SIZE(power9_event_alternatives), flags,
123                                           power9_event_alternatives);
124
125         return num_alt;
126 }
127
128 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
129 GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_ICT_NOSLOT_CYC);
130 GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
131 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
132 GENERIC_EVENT_ATTR(branch-instructions,         PM_BR_CMPL);
133 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
134 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
135 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1_FIN);
136
137 CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1_FIN);
138 CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
139 CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_L1_PREF);
140 CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
141 CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
142 CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
143 CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_WRITE);
144 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
145 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
146 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
147 CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
148 CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
149 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
150 CACHE_EVENT_ATTR(branch-loads,                  PM_BR_CMPL);
151 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
152 CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
153
154 static struct attribute *power9_events_attr[] = {
155         GENERIC_EVENT_PTR(PM_CYC),
156         GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
157         GENERIC_EVENT_PTR(PM_CMPLU_STALL),
158         GENERIC_EVENT_PTR(PM_INST_CMPL),
159         GENERIC_EVENT_PTR(PM_BR_CMPL),
160         GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
161         GENERIC_EVENT_PTR(PM_LD_REF_L1),
162         GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
163         CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
164         CACHE_EVENT_PTR(PM_LD_REF_L1),
165         CACHE_EVENT_PTR(PM_L1_PREF),
166         CACHE_EVENT_PTR(PM_ST_MISS_L1),
167         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
168         CACHE_EVENT_PTR(PM_INST_FROM_L1),
169         CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
170         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
171         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
172         CACHE_EVENT_PTR(PM_L3_PREF_ALL),
173         CACHE_EVENT_PTR(PM_L2_ST_MISS),
174         CACHE_EVENT_PTR(PM_L2_ST),
175         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
176         CACHE_EVENT_PTR(PM_BR_CMPL),
177         CACHE_EVENT_PTR(PM_DTLB_MISS),
178         CACHE_EVENT_PTR(PM_ITLB_MISS),
179         NULL
180 };
181
182 static struct attribute_group power9_pmu_events_group = {
183         .name = "events",
184         .attrs = power9_events_attr,
185 };
186
187 static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
188         &isa207_pmu_format_group,
189         &power9_pmu_events_group,
190         NULL,
191 };
192
193 PMU_FORMAT_ATTR(event,          "config:0-51");
194 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
195 PMU_FORMAT_ATTR(mark,           "config:8");
196 PMU_FORMAT_ATTR(combine,        "config:10-11");
197 PMU_FORMAT_ATTR(unit,           "config:12-15");
198 PMU_FORMAT_ATTR(pmc,            "config:16-19");
199 PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
200 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
201 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
202 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
203 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
204 PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
205 PMU_FORMAT_ATTR(sdar_mode,      "config:50-51");
206
207 static struct attribute *power9_pmu_format_attr[] = {
208         &format_attr_event.attr,
209         &format_attr_pmcxsel.attr,
210         &format_attr_mark.attr,
211         &format_attr_combine.attr,
212         &format_attr_unit.attr,
213         &format_attr_pmc.attr,
214         &format_attr_cache_sel.attr,
215         &format_attr_sample_mode.attr,
216         &format_attr_thresh_sel.attr,
217         &format_attr_thresh_stop.attr,
218         &format_attr_thresh_start.attr,
219         &format_attr_thresh_cmp.attr,
220         &format_attr_sdar_mode.attr,
221         NULL,
222 };
223
224 static struct attribute_group power9_pmu_format_group = {
225         .name = "format",
226         .attrs = power9_pmu_format_attr,
227 };
228
229 static const struct attribute_group *power9_pmu_attr_groups[] = {
230         &power9_pmu_format_group,
231         &power9_pmu_events_group,
232         NULL,
233 };
234
235 static int power9_generic_events_dd1[] = {
236         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
237         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
238         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
239         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_DISP,
240         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_CMPL_ALT,
241         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
242         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
243         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
244 };
245
246 static int power9_generic_events[] = {
247         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
248         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
249         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
250         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
251         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_CMPL,
252         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
253         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
254         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
255 };
256
257 static u64 power9_bhrb_filter_map(u64 branch_sample_type)
258 {
259         u64 pmu_bhrb_filter = 0;
260
261         /* BHRB and regular PMU events share the same privilege state
262          * filter configuration. BHRB is always recorded along with a
263          * regular PMU event. As the privilege state filter is handled
264          * in the basic PMC configuration of the accompanying regular
265          * PMU event, we ignore any separate BHRB specific request.
266          */
267
268         /* No branch filter requested */
269         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
270                 return pmu_bhrb_filter;
271
272         /* Invalid branch filter options - HW does not support */
273         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
274                 return -1;
275
276         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
277                 return -1;
278
279         if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
280                 return -1;
281
282         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
283                 pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
284                 return pmu_bhrb_filter;
285         }
286
287         /* Every thing else is unsupported */
288         return -1;
289 }
290
291 static void power9_config_bhrb(u64 pmu_bhrb_filter)
292 {
293         pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
294
295         /* Enable BHRB filter in PMU */
296         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
297 }
298
299 #define C(x)    PERF_COUNT_HW_CACHE_##x
300
301 /*
302  * Table of generalized cache-related events.
303  * 0 means not supported, -1 means nonsensical, other values
304  * are event codes.
305  */
306 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
307         [ C(L1D) ] = {
308                 [ C(OP_READ) ] = {
309                         [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
310                         [ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
311                 },
312                 [ C(OP_WRITE) ] = {
313                         [ C(RESULT_ACCESS) ] = 0,
314                         [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
315                 },
316                 [ C(OP_PREFETCH) ] = {
317                         [ C(RESULT_ACCESS) ] = PM_L1_PREF,
318                         [ C(RESULT_MISS)   ] = 0,
319                 },
320         },
321         [ C(L1I) ] = {
322                 [ C(OP_READ) ] = {
323                         [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
324                         [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
325                 },
326                 [ C(OP_WRITE) ] = {
327                         [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
328                         [ C(RESULT_MISS)   ] = -1,
329                 },
330                 [ C(OP_PREFETCH) ] = {
331                         [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
332                         [ C(RESULT_MISS)   ] = 0,
333                 },
334         },
335         [ C(LL) ] = {
336                 [ C(OP_READ) ] = {
337                         [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
338                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
339                 },
340                 [ C(OP_WRITE) ] = {
341                         [ C(RESULT_ACCESS) ] = PM_L2_ST,
342                         [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
343                 },
344                 [ C(OP_PREFETCH) ] = {
345                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
346                         [ C(RESULT_MISS)   ] = 0,
347                 },
348         },
349         [ C(DTLB) ] = {
350                 [ C(OP_READ) ] = {
351                         [ C(RESULT_ACCESS) ] = 0,
352                         [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
353                 },
354                 [ C(OP_WRITE) ] = {
355                         [ C(RESULT_ACCESS) ] = -1,
356                         [ C(RESULT_MISS)   ] = -1,
357                 },
358                 [ C(OP_PREFETCH) ] = {
359                         [ C(RESULT_ACCESS) ] = -1,
360                         [ C(RESULT_MISS)   ] = -1,
361                 },
362         },
363         [ C(ITLB) ] = {
364                 [ C(OP_READ) ] = {
365                         [ C(RESULT_ACCESS) ] = 0,
366                         [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
367                 },
368                 [ C(OP_WRITE) ] = {
369                         [ C(RESULT_ACCESS) ] = -1,
370                         [ C(RESULT_MISS)   ] = -1,
371                 },
372                 [ C(OP_PREFETCH) ] = {
373                         [ C(RESULT_ACCESS) ] = -1,
374                         [ C(RESULT_MISS)   ] = -1,
375                 },
376         },
377         [ C(BPU) ] = {
378                 [ C(OP_READ) ] = {
379                         [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
380                         [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
381                 },
382                 [ C(OP_WRITE) ] = {
383                         [ C(RESULT_ACCESS) ] = -1,
384                         [ C(RESULT_MISS)   ] = -1,
385                 },
386                 [ C(OP_PREFETCH) ] = {
387                         [ C(RESULT_ACCESS) ] = -1,
388                         [ C(RESULT_MISS)   ] = -1,
389                 },
390         },
391         [ C(NODE) ] = {
392                 [ C(OP_READ) ] = {
393                         [ C(RESULT_ACCESS) ] = -1,
394                         [ C(RESULT_MISS)   ] = -1,
395                 },
396                 [ C(OP_WRITE) ] = {
397                         [ C(RESULT_ACCESS) ] = -1,
398                         [ C(RESULT_MISS)   ] = -1,
399                 },
400                 [ C(OP_PREFETCH) ] = {
401                         [ C(RESULT_ACCESS) ] = -1,
402                         [ C(RESULT_MISS)   ] = -1,
403                 },
404         },
405 };
406
407 #undef C
408
409 static struct power_pmu power9_isa207_pmu = {
410         .name                   = "POWER9",
411         .n_counter              = MAX_PMU_COUNTERS,
412         .add_fields             = ISA207_ADD_FIELDS,
413         .test_adder             = P9_DD1_TEST_ADDER,
414         .compute_mmcr           = isa207_compute_mmcr,
415         .config_bhrb            = power9_config_bhrb,
416         .bhrb_filter_map        = power9_bhrb_filter_map,
417         .get_constraint         = isa207_get_constraint,
418         .get_alternatives       = power9_get_alternatives,
419         .disable_pmc            = isa207_disable_pmc,
420         .flags                  = PPMU_NO_SIAR | PPMU_ARCH_207S,
421         .n_generic              = ARRAY_SIZE(power9_generic_events_dd1),
422         .generic_events         = power9_generic_events_dd1,
423         .cache_events           = &power9_cache_events,
424         .attr_groups            = power9_isa207_pmu_attr_groups,
425         .bhrb_nr                = 32,
426 };
427
428 static struct power_pmu power9_pmu = {
429         .name                   = "POWER9",
430         .n_counter              = MAX_PMU_COUNTERS,
431         .add_fields             = ISA207_ADD_FIELDS,
432         .test_adder             = ISA207_TEST_ADDER,
433         .compute_mmcr           = isa207_compute_mmcr,
434         .config_bhrb            = power9_config_bhrb,
435         .bhrb_filter_map        = power9_bhrb_filter_map,
436         .get_constraint         = isa207_get_constraint,
437         .get_alternatives       = power9_get_alternatives,
438         .get_mem_data_src       = isa207_get_mem_data_src,
439         .get_mem_weight         = isa207_get_mem_weight,
440         .disable_pmc            = isa207_disable_pmc,
441         .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S,
442         .n_generic              = ARRAY_SIZE(power9_generic_events),
443         .generic_events         = power9_generic_events,
444         .cache_events           = &power9_cache_events,
445         .attr_groups            = power9_pmu_attr_groups,
446         .bhrb_nr                = 32,
447 };
448
449 static int __init init_power9_pmu(void)
450 {
451         int rc = 0;
452
453         /* Comes from cpu_specs[] */
454         if (!cur_cpu_spec->oprofile_cpu_type ||
455             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
456                 return -ENODEV;
457
458         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
459                 /*
460                  * Since PM_INST_CMPL may not provide right counts in all
461                  * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
462                  */
463                 EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
464                 /*
465                  * Power9 DD1 should use PM_BR_CMPL_ALT event code for
466                  * "branches" to provide correct counter value.
467                  */
468                 EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT;
469                 EVENT_VAR(PM_BR_CMPL, _c).id = PM_BR_CMPL_ALT;
470                 rc = register_power_pmu(&power9_isa207_pmu);
471         } else {
472                 rc = register_power_pmu(&power9_pmu);
473         }
474
475         if (rc)
476                 return rc;
477
478         /* Tell userspace that EBB is supported */
479         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
480
481         return 0;
482 }
483 early_initcall(init_power9_pmu);