arch/powerpc/perf/power9-pmu.c

   1 /*
   2  * Performance counter support for POWER9 processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  * Copyright 2013 Michael Ellerman, IBM Corporation.
   6  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or later version.
  12  */
  13
  14 #define pr_fmt(fmt)     "power9-pmu: " fmt
  15
  16 #include "isa207-common.h"
  17
  18 /*
  19  * Raw event encoding for Power9:
  20  *
  21  *        60        56        52        48        44        40        36        32
  22  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  23  *   | | [ ]                       [ ] [      thresh_cmp     ]   [  thresh_ctl   ]
  24  *   | |  |                         |                                     |
  25  *   | |  *- IFM (Linux)            |                  thresh start/stop -*
  26  *   | *- BHRB (Linux)              *sm
  27  *   *- EBB (Linux)
  28  *
  29  *        28        24        20        16        12         8         4         0
  30  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
  31  *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   []    m   [    pmcxsel    ]
  32  *     |        |           |                          |     |
  33  *     |        |           |                          |     *- mark
  34  *     |        |           *- L1/L2/L3 cache_sel      |
  35  *     |        |                                      |
  36  *     |        *- sampling mode for marked events     *- combine
  37  *     |
  38  *     *- thresh_sel
  39  *
  40  * Below uses IBM bit numbering.
  41  *
  42  * MMCR1[x:y] = unit    (PMCxUNIT)
  43  * MMCR1[24]   = pmc1combine[0]
  44  * MMCR1[25]   = pmc1combine[1]
  45  * MMCR1[26]   = pmc2combine[0]
  46  * MMCR1[27]   = pmc2combine[1]
  47  * MMCR1[28]   = pmc3combine[0]
  48  * MMCR1[29]   = pmc3combine[1]
  49  * MMCR1[30]   = pmc4combine[0]
  50  * MMCR1[31]   = pmc4combine[1]
  51  *
  52  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
  53  *      MMCR1[20:27] = thresh_ctl
  54  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
  55  *      MMCR1[20:27] = thresh_ctl
  56  * else
  57  *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
  58  *
  59  * if thresh_sel:
  60  *      MMCRA[45:47] = thresh_sel
  61  *
  62  * if thresh_cmp:
  63  *      MMCRA[9:11] = thresh_cmp[0:2]
  64  *      MMCRA[12:18] = thresh_cmp[3:9]
  65  *
  66  * if unit == 6 or unit == 7
  67  *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
  68  * else if unit == 8 or unit == 9:
  69  *      if cache_sel[0] == 0: # L3 bank
  70  *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
  71  *      else if cache_sel[0] == 1:
  72  *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
  73  * else if cache_sel[1]: # L1 event
  74  *      MMCR1[16] = cache_sel[2]
  75  *     MMCR1[17] = cache_sel[3]
  76  *
  77  * if mark:
  78  *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
  79  *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
  80  *     MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
  81  *
  82  * if EBB and BHRB:
  83  *      MMCRA[32:33] = IFM
  84  *
  85  * MMCRA[SDAR_MODE]  = sm
  86  */
  87
  88 /*
  89  * Some power9 event codes.
  90  */
  91 #define EVENT(_name, _code)     _name = _code,
  92
  93 enum {
  94 #include "power9-events-list.h"
  95 };
  96
  97 #undef EVENT
  98
  99 /* MMCRA IFM bits - POWER9 */
 100 #define POWER9_MMCRA_IFM1               0x0000000040000000UL
 101 #define POWER9_MMCRA_IFM2               0x0000000080000000UL
 102 #define POWER9_MMCRA_IFM3               0x00000000C0000000UL
 103 #define POWER9_MMCRA_BHRB_MASK          0x00000000C0000000UL
 104
 105 /* Nasty Power9 specific hack */
 106 #define PVR_POWER9_CUMULUS              0x00002000
 107
 108 /* PowerISA v2.07 format attribute structure*/
 109 extern struct attribute_group isa207_pmu_format_group;
 110
 111 int p9_dd21_bl_ev[] = {
 112         PM_MRK_ST_DONE_L2,
 113         PM_RADIX_PWC_L1_HIT,
 114         PM_FLOP_CMPL,
 115         PM_MRK_NTF_FIN,
 116         PM_RADIX_PWC_L2_HIT,
 117         PM_IFETCH_THROTTLE,
 118         PM_MRK_L2_TM_ST_ABORT_SISTER,
 119         PM_RADIX_PWC_L3_HIT,
 120         PM_RUN_CYC_SMT2_MODE,
 121         PM_TM_TX_PASS_RUN_INST,
 122         PM_DISP_HELD_SYNC_HOLD,
 123 };
 124
 125 int p9_dd22_bl_ev[] = {
 126         PM_DTLB_MISS_16G,
 127         PM_DERAT_MISS_2M,
 128         PM_DTLB_MISS_2M,
 129         PM_MRK_DTLB_MISS_1G,
 130         PM_DTLB_MISS_4K,
 131         PM_DERAT_MISS_1G,
 132         PM_MRK_DERAT_MISS_2M,
 133         PM_MRK_DTLB_MISS_4K,
 134         PM_MRK_DTLB_MISS_16G,
 135         PM_DTLB_MISS_64K,
 136         PM_MRK_DERAT_MISS_1G,
 137         PM_MRK_DTLB_MISS_64K,
 138         PM_DISP_HELD_SYNC_HOLD,
 139         PM_DTLB_MISS_16M,
 140         PM_DTLB_MISS_1G,
 141         PM_MRK_DTLB_MISS_16M,
 142 };
 143
 144 /* Table of alternatives, sorted by column 0 */
 145 static const unsigned int power9_event_alternatives[][MAX_ALT] = {
 146         { PM_BR_2PATH,                  PM_BR_2PATH_ALT },
 147         { PM_INST_DISP,                 PM_INST_DISP_ALT },
 148         { PM_RUN_CYC_ALT,               PM_RUN_CYC },
 149         { PM_LD_MISS_L1,                PM_LD_MISS_L1_ALT },
 150         { PM_RUN_INST_CMPL_ALT,         PM_RUN_INST_CMPL },
 151 };
 152
 153 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 154 {
 155         int num_alt = 0;
 156
 157         num_alt = isa207_get_alternatives(event, alt,
 158                                           ARRAY_SIZE(power9_event_alternatives), flags,
 159                                           power9_event_alternatives);
 160
 161         return num_alt;
 162 }
 163
 164 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
 165 GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_ICT_NOSLOT_CYC);
 166 GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
 167 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
 168 GENERIC_EVENT_ATTR(branch-instructions,         PM_BR_CMPL);
 169 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
 170 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
 171 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1_FIN);
 172
 173 CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1_FIN);
 174 CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
 175 CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_L1_PREF);
 176 CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
 177 CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
 178 CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
 179 CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_WRITE);
 180 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
 181 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
 182 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
 183 CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
 184 CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
 185 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
 186 CACHE_EVENT_ATTR(branch-loads,                  PM_BR_CMPL);
 187 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
 188 CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
 189
 190 static struct attribute *power9_events_attr[] = {
 191         GENERIC_EVENT_PTR(PM_CYC),
 192         GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
 193         GENERIC_EVENT_PTR(PM_CMPLU_STALL),
 194         GENERIC_EVENT_PTR(PM_INST_CMPL),
 195         GENERIC_EVENT_PTR(PM_BR_CMPL),
 196         GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
 197         GENERIC_EVENT_PTR(PM_LD_REF_L1),
 198         GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
 199         CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
 200         CACHE_EVENT_PTR(PM_LD_REF_L1),
 201         CACHE_EVENT_PTR(PM_L1_PREF),
 202         CACHE_EVENT_PTR(PM_ST_MISS_L1),
 203         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
 204         CACHE_EVENT_PTR(PM_INST_FROM_L1),
 205         CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
 206         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
 207         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
 208         CACHE_EVENT_PTR(PM_L3_PREF_ALL),
 209         CACHE_EVENT_PTR(PM_L2_ST_MISS),
 210         CACHE_EVENT_PTR(PM_L2_ST),
 211         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
 212         CACHE_EVENT_PTR(PM_BR_CMPL),
 213         CACHE_EVENT_PTR(PM_DTLB_MISS),
 214         CACHE_EVENT_PTR(PM_ITLB_MISS),
 215         NULL
 216 };
 217
 218 static struct attribute_group power9_pmu_events_group = {
 219         .name = "events",
 220         .attrs = power9_events_attr,
 221 };
 222
 223 PMU_FORMAT_ATTR(event,          "config:0-51");
 224 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
 225 PMU_FORMAT_ATTR(mark,           "config:8");
 226 PMU_FORMAT_ATTR(combine,        "config:10-11");
 227 PMU_FORMAT_ATTR(unit,           "config:12-15");
 228 PMU_FORMAT_ATTR(pmc,            "config:16-19");
 229 PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
 230 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
 231 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
 232 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
 233 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
 234 PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
 235 PMU_FORMAT_ATTR(sdar_mode,      "config:50-51");
 236
 237 static struct attribute *power9_pmu_format_attr[] = {
 238         &format_attr_event.attr,
 239         &format_attr_pmcxsel.attr,
 240         &format_attr_mark.attr,
 241         &format_attr_combine.attr,
 242         &format_attr_unit.attr,
 243         &format_attr_pmc.attr,
 244         &format_attr_cache_sel.attr,
 245         &format_attr_sample_mode.attr,
 246         &format_attr_thresh_sel.attr,
 247         &format_attr_thresh_stop.attr,
 248         &format_attr_thresh_start.attr,
 249         &format_attr_thresh_cmp.attr,
 250         &format_attr_sdar_mode.attr,
 251         NULL,
 252 };
 253
 254 static struct attribute_group power9_pmu_format_group = {
 255         .name = "format",
 256         .attrs = power9_pmu_format_attr,
 257 };
 258
 259 static const struct attribute_group *power9_pmu_attr_groups[] = {
 260         &power9_pmu_format_group,
 261         &power9_pmu_events_group,
 262         NULL,
 263 };
 264
 265 static int power9_generic_events[] = {
 266         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 267         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
 268         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 269         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 270         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_CMPL,
 271         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 272         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 273         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
 274 };
 275
 276 static u64 power9_bhrb_filter_map(u64 branch_sample_type)
 277 {
 278         u64 pmu_bhrb_filter = 0;
 279
 280         /* BHRB and regular PMU events share the same privilege state
 281          * filter configuration. BHRB is always recorded along with a
 282          * regular PMU event. As the privilege state filter is handled
 283          * in the basic PMC configuration of the accompanying regular
 284          * PMU event, we ignore any separate BHRB specific request.
 285          */
 286
 287         /* No branch filter requested */
 288         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 289                 return pmu_bhrb_filter;
 290
 291         /* Invalid branch filter options - HW does not support */
 292         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 293                 return -1;
 294
 295         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
 296                 return -1;
 297
 298         if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
 299                 return -1;
 300
 301         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 302                 pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
 303                 return pmu_bhrb_filter;
 304         }
 305
 306         /* Every thing else is unsupported */
 307         return -1;
 308 }
 309
 310 static void power9_config_bhrb(u64 pmu_bhrb_filter)
 311 {
 312         pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
 313
 314         /* Enable BHRB filter in PMU */
 315         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 316 }
 317
 318 #define C(x)    PERF_COUNT_HW_CACHE_##x
 319
 320 /*
 321  * Table of generalized cache-related events.
 322  * 0 means not supported, -1 means nonsensical, other values
 323  * are event codes.
 324  */
 325 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 326         [ C(L1D) ] = {
 327                 [ C(OP_READ) ] = {
 328                         [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
 329                         [ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
 330                 },
 331                 [ C(OP_WRITE) ] = {
 332                         [ C(RESULT_ACCESS) ] = 0,
 333                         [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
 334                 },
 335                 [ C(OP_PREFETCH) ] = {
 336                         [ C(RESULT_ACCESS) ] = PM_L1_PREF,
 337                         [ C(RESULT_MISS)   ] = 0,
 338                 },
 339         },
 340         [ C(L1I) ] = {
 341                 [ C(OP_READ) ] = {
 342                         [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
 343                         [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
 344                 },
 345                 [ C(OP_WRITE) ] = {
 346                         [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
 347                         [ C(RESULT_MISS)   ] = -1,
 348                 },
 349                 [ C(OP_PREFETCH) ] = {
 350                         [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
 351                         [ C(RESULT_MISS)   ] = 0,
 352                 },
 353         },
 354         [ C(LL) ] = {
 355                 [ C(OP_READ) ] = {
 356                         [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
 357                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
 358                 },
 359                 [ C(OP_WRITE) ] = {
 360                         [ C(RESULT_ACCESS) ] = PM_L2_ST,
 361                         [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
 362                 },
 363                 [ C(OP_PREFETCH) ] = {
 364                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
 365                         [ C(RESULT_MISS)   ] = 0,
 366                 },
 367         },
 368         [ C(DTLB) ] = {
 369                 [ C(OP_READ) ] = {
 370                         [ C(RESULT_ACCESS) ] = 0,
 371                         [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
 372                 },
 373                 [ C(OP_WRITE) ] = {
 374                         [ C(RESULT_ACCESS) ] = -1,
 375                         [ C(RESULT_MISS)   ] = -1,
 376                 },
 377                 [ C(OP_PREFETCH) ] = {
 378                         [ C(RESULT_ACCESS) ] = -1,
 379                         [ C(RESULT_MISS)   ] = -1,
 380                 },
 381         },
 382         [ C(ITLB) ] = {
 383                 [ C(OP_READ) ] = {
 384                         [ C(RESULT_ACCESS) ] = 0,
 385                         [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
 386                 },
 387                 [ C(OP_WRITE) ] = {
 388                         [ C(RESULT_ACCESS) ] = -1,
 389                         [ C(RESULT_MISS)   ] = -1,
 390                 },
 391                 [ C(OP_PREFETCH) ] = {
 392                         [ C(RESULT_ACCESS) ] = -1,
 393                         [ C(RESULT_MISS)   ] = -1,
 394                 },
 395         },
 396         [ C(BPU) ] = {
 397                 [ C(OP_READ) ] = {
 398                         [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
 399                         [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
 400                 },
 401                 [ C(OP_WRITE) ] = {
 402                         [ C(RESULT_ACCESS) ] = -1,
 403                         [ C(RESULT_MISS)   ] = -1,
 404                 },
 405                 [ C(OP_PREFETCH) ] = {
 406                         [ C(RESULT_ACCESS) ] = -1,
 407                         [ C(RESULT_MISS)   ] = -1,
 408                 },
 409         },
 410         [ C(NODE) ] = {
 411                 [ C(OP_READ) ] = {
 412                         [ C(RESULT_ACCESS) ] = -1,
 413                         [ C(RESULT_MISS)   ] = -1,
 414                 },
 415                 [ C(OP_WRITE) ] = {
 416                         [ C(RESULT_ACCESS) ] = -1,
 417                         [ C(RESULT_MISS)   ] = -1,
 418                 },
 419                 [ C(OP_PREFETCH) ] = {
 420                         [ C(RESULT_ACCESS) ] = -1,
 421                         [ C(RESULT_MISS)   ] = -1,
 422                 },
 423         },
 424 };
 425
 426 #undef C
 427
 428 static struct power_pmu power9_pmu = {
 429         .name                   = "POWER9",
 430         .n_counter              = MAX_PMU_COUNTERS,
 431         .add_fields             = ISA207_ADD_FIELDS,
 432         .test_adder             = ISA207_TEST_ADDER,
 433         .compute_mmcr           = isa207_compute_mmcr,
 434         .config_bhrb            = power9_config_bhrb,
 435         .bhrb_filter_map        = power9_bhrb_filter_map,
 436         .get_constraint         = isa207_get_constraint,
 437         .get_alternatives       = power9_get_alternatives,
 438         .get_mem_data_src       = isa207_get_mem_data_src,
 439         .get_mem_weight         = isa207_get_mem_weight,
 440         .disable_pmc            = isa207_disable_pmc,
 441         .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S,
 442         .n_generic              = ARRAY_SIZE(power9_generic_events),
 443         .generic_events         = power9_generic_events,
 444         .cache_events           = &power9_cache_events,
 445         .attr_groups            = power9_pmu_attr_groups,
 446         .bhrb_nr                = 32,
 447 };
 448
 449 static int __init init_power9_pmu(void)
 450 {
 451         int rc = 0;
 452         unsigned int pvr = mfspr(SPRN_PVR);
 453
 454         /* Comes from cpu_specs[] */
 455         if (!cur_cpu_spec->oprofile_cpu_type ||
 456             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
 457                 return -ENODEV;
 458
 459         /* Blacklist events */
 460         if (!(pvr & PVR_POWER9_CUMULUS)) {
 461                 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
 462                         power9_pmu.blacklist_ev = p9_dd21_bl_ev;
 463                         power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
 464                 } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
 465                         power9_pmu.blacklist_ev = p9_dd22_bl_ev;
 466                         power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
 467                 }
 468         }
 469
 470         rc = register_power_pmu(&power9_pmu);
 471         if (rc)
 472                 return rc;
 473
 474         /* Tell userspace that EBB is supported */
 475         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 476
 477         return 0;
 478 }
 479 early_initcall(init_power9_pmu);