2 * Performance counter support for POWER8 processors.
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2013 Michael Ellerman, IBM Corporation.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #define pr_fmt(fmt) "power8-pmu: " fmt
15 #include "isa207-common.h"
18 * Some power8 event codes.
20 #define EVENT(_name, _code) _name = _code,
23 #include "power8-events-list.h"
28 /* MMCRA IFM bits - POWER8 */
29 #define POWER8_MMCRA_IFM1 0x0000000040000000UL
30 #define POWER8_MMCRA_IFM2 0x0000000080000000UL
31 #define POWER8_MMCRA_IFM3 0x00000000C0000000UL
32 #define POWER8_MMCRA_BHRB_MASK 0x00000000C0000000UL
34 /* PowerISA v2.07 format attribute structure*/
35 extern struct attribute_group isa207_pmu_format_group;
37 /* Table of alternatives, sorted by column 0 */
38 static const unsigned int event_alternatives[][MAX_ALT] = {
39 { PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT },
40 { PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT },
41 { PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT },
42 { PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT },
43 { PM_CMPLU_STALL_ALT, PM_CMPLU_STALL },
44 { PM_BR_2PATH, PM_BR_2PATH_ALT },
45 { PM_INST_DISP, PM_INST_DISP_ALT },
46 { PM_RUN_CYC_ALT, PM_RUN_CYC },
47 { PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT },
48 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
49 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
52 static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
56 num_alt = isa207_get_alternatives(event, alt,
57 ARRAY_SIZE(event_alternatives), flags,
63 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
64 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
65 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
66 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
67 GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
68 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
69 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
70 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
71 GENERIC_EVENT_ATTR(mem_access, MEM_ACCESS);
73 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
74 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
76 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
77 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
78 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
79 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
80 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
82 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
83 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
84 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
85 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
86 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
88 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
89 CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);
90 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
91 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
93 static struct attribute *power8_events_attr[] = {
94 GENERIC_EVENT_PTR(PM_CYC),
95 GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
96 GENERIC_EVENT_PTR(PM_CMPLU_STALL),
97 GENERIC_EVENT_PTR(PM_INST_CMPL),
98 GENERIC_EVENT_PTR(PM_BRU_FIN),
99 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
100 GENERIC_EVENT_PTR(PM_LD_REF_L1),
101 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
102 GENERIC_EVENT_PTR(MEM_ACCESS),
104 CACHE_EVENT_PTR(PM_LD_MISS_L1),
105 CACHE_EVENT_PTR(PM_LD_REF_L1),
106 CACHE_EVENT_PTR(PM_L1_PREF),
107 CACHE_EVENT_PTR(PM_ST_MISS_L1),
108 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
109 CACHE_EVENT_PTR(PM_INST_FROM_L1),
110 CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
111 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
112 CACHE_EVENT_PTR(PM_DATA_FROM_L3),
113 CACHE_EVENT_PTR(PM_L3_PREF_ALL),
114 CACHE_EVENT_PTR(PM_L2_ST_MISS),
115 CACHE_EVENT_PTR(PM_L2_ST),
117 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
118 CACHE_EVENT_PTR(PM_BRU_FIN),
120 CACHE_EVENT_PTR(PM_DTLB_MISS),
121 CACHE_EVENT_PTR(PM_ITLB_MISS),
125 static struct attribute_group power8_pmu_events_group = {
127 .attrs = power8_events_attr,
130 static const struct attribute_group *power8_pmu_attr_groups[] = {
131 &isa207_pmu_format_group,
132 &power8_pmu_events_group,
136 static int power8_generic_events[] = {
137 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
138 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
139 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
140 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
141 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
142 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
143 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
144 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
147 static u64 power8_bhrb_filter_map(u64 branch_sample_type)
149 u64 pmu_bhrb_filter = 0;
151 /* BHRB and regular PMU events share the same privilege state
152 * filter configuration. BHRB is always recorded along with a
153 * regular PMU event. As the privilege state filter is handled
154 * in the basic PMC configuration of the accompanying regular
155 * PMU event, we ignore any separate BHRB specific request.
158 /* No branch filter requested */
159 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
160 return pmu_bhrb_filter;
162 /* Invalid branch filter options - HW does not support */
163 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
166 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
169 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
172 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
173 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
174 return pmu_bhrb_filter;
177 /* Every thing else is unsupported */
181 static void power8_config_bhrb(u64 pmu_bhrb_filter)
183 pmu_bhrb_filter &= POWER8_MMCRA_BHRB_MASK;
185 /* Enable BHRB filter in PMU */
186 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
189 #define C(x) PERF_COUNT_HW_CACHE_##x
192 * Table of generalized cache-related events.
193 * 0 means not supported, -1 means nonsensical, other values
196 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
199 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
200 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
203 [ C(RESULT_ACCESS) ] = 0,
204 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
206 [ C(OP_PREFETCH) ] = {
207 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
208 [ C(RESULT_MISS) ] = 0,
213 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
214 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
217 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
218 [ C(RESULT_MISS) ] = -1,
220 [ C(OP_PREFETCH) ] = {
221 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
222 [ C(RESULT_MISS) ] = 0,
227 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
228 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
231 [ C(RESULT_ACCESS) ] = PM_L2_ST,
232 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
234 [ C(OP_PREFETCH) ] = {
235 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
236 [ C(RESULT_MISS) ] = 0,
241 [ C(RESULT_ACCESS) ] = 0,
242 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
245 [ C(RESULT_ACCESS) ] = -1,
246 [ C(RESULT_MISS) ] = -1,
248 [ C(OP_PREFETCH) ] = {
249 [ C(RESULT_ACCESS) ] = -1,
250 [ C(RESULT_MISS) ] = -1,
255 [ C(RESULT_ACCESS) ] = 0,
256 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
259 [ C(RESULT_ACCESS) ] = -1,
260 [ C(RESULT_MISS) ] = -1,
262 [ C(OP_PREFETCH) ] = {
263 [ C(RESULT_ACCESS) ] = -1,
264 [ C(RESULT_MISS) ] = -1,
269 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
270 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
273 [ C(RESULT_ACCESS) ] = -1,
274 [ C(RESULT_MISS) ] = -1,
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = -1,
278 [ C(RESULT_MISS) ] = -1,
283 [ C(RESULT_ACCESS) ] = -1,
284 [ C(RESULT_MISS) ] = -1,
287 [ C(RESULT_ACCESS) ] = -1,
288 [ C(RESULT_MISS) ] = -1,
290 [ C(OP_PREFETCH) ] = {
291 [ C(RESULT_ACCESS) ] = -1,
292 [ C(RESULT_MISS) ] = -1,
299 static struct power_pmu power8_pmu = {
301 .n_counter = MAX_PMU_COUNTERS,
302 .max_alternatives = MAX_ALT + 1,
303 .add_fields = ISA207_ADD_FIELDS,
304 .test_adder = ISA207_TEST_ADDER,
305 .compute_mmcr = isa207_compute_mmcr,
306 .config_bhrb = power8_config_bhrb,
307 .bhrb_filter_map = power8_bhrb_filter_map,
308 .get_constraint = isa207_get_constraint,
309 .get_alternatives = power8_get_alternatives,
310 .get_mem_data_src = isa207_get_mem_data_src,
311 .get_mem_weight = isa207_get_mem_weight,
312 .disable_pmc = isa207_disable_pmc,
313 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
314 .n_generic = ARRAY_SIZE(power8_generic_events),
315 .generic_events = power8_generic_events,
316 .cache_events = &power8_cache_events,
317 .attr_groups = power8_pmu_attr_groups,
321 static int __init init_power8_pmu(void)
325 if (!cur_cpu_spec->oprofile_cpu_type ||
326 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
329 rc = register_power_pmu(&power8_pmu);
333 /* Tell userspace that EBB is supported */
334 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
336 if (cpu_has_feature(CPU_FTR_PMAO_BUG))
337 pr_info("PMAO restore workaround active.\n");
341 early_initcall(init_power8_pmu);