1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * In-Memory Collection (IMC) Performance Monitor counter support.
5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
6 * (C) 2017 Anju T Sudhakar, IBM Corporation.
7 * (C) 2017 Hemant K Shaw, IBM Corporation.
9 #include <linux/perf_event.h>
10 #include <linux/slab.h>
12 #include <asm/imc-pmu.h>
13 #include <asm/cputhreads.h>
15 #include <linux/string.h>
17 /* Nest IMC data structures and variables */
20 * Used to avoid races in counting the nest-pmu units during hotplug
21 * register and unregister
23 static DEFINE_MUTEX(nest_init_lock);
24 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
25 static struct imc_pmu **per_nest_pmu_arr;
26 static cpumask_t nest_imc_cpumask;
27 static struct imc_pmu_ref *nest_imc_refc;
30 /* Core IMC data structures and variables */
32 static cpumask_t core_imc_cpumask;
33 static struct imc_pmu_ref *core_imc_refc;
34 static struct imc_pmu *core_imc_pmu;
36 /* Thread IMC data structures and variables */
38 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
39 static struct imc_pmu *thread_imc_pmu;
40 static int thread_imc_mem_size;
42 /* Trace IMC data structures */
43 static DEFINE_PER_CPU(u64 *, trace_imc_mem);
44 static struct imc_pmu_ref *trace_imc_refc;
45 static int trace_imc_mem_size;
48 * Global data structure used to avoid races between thread,
51 static struct imc_pmu_ref imc_global_refc = {
52 .lock = __MUTEX_INITIALIZER(imc_global_refc.lock),
57 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
59 return container_of(event->pmu, struct imc_pmu, pmu);
62 PMU_FORMAT_ATTR(event, "config:0-61");
63 PMU_FORMAT_ATTR(offset, "config:0-31");
64 PMU_FORMAT_ATTR(rvalue, "config:32");
65 PMU_FORMAT_ATTR(mode, "config:33-40");
66 static struct attribute *imc_format_attrs[] = {
67 &format_attr_event.attr,
68 &format_attr_offset.attr,
69 &format_attr_rvalue.attr,
70 &format_attr_mode.attr,
74 static struct attribute_group imc_format_group = {
76 .attrs = imc_format_attrs,
79 /* Format attribute for imc trace-mode */
80 PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
81 PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
82 PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
83 PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
84 static struct attribute *trace_imc_format_attrs[] = {
85 &format_attr_event.attr,
86 &format_attr_cpmc_reserved.attr,
87 &format_attr_cpmc_event.attr,
88 &format_attr_cpmc_samplesel.attr,
89 &format_attr_cpmc_load.attr,
93 static struct attribute_group trace_imc_format_group = {
95 .attrs = trace_imc_format_attrs,
98 /* Get the cpumask printed to a buffer "buf" */
99 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
100 struct device_attribute *attr,
103 struct pmu *pmu = dev_get_drvdata(dev);
104 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
105 cpumask_t *active_mask;
107 switch(imc_pmu->domain){
108 case IMC_DOMAIN_NEST:
109 active_mask = &nest_imc_cpumask;
111 case IMC_DOMAIN_CORE:
112 active_mask = &core_imc_cpumask;
118 return cpumap_print_to_pagebuf(true, buf, active_mask);
121 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
123 static struct attribute *imc_pmu_cpumask_attrs[] = {
124 &dev_attr_cpumask.attr,
128 static struct attribute_group imc_pmu_cpumask_attr_group = {
129 .attrs = imc_pmu_cpumask_attrs,
132 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
133 static struct attribute *device_str_attr_create(const char *name, const char *str)
135 struct perf_pmu_events_attr *attr;
137 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
140 sysfs_attr_init(&attr->attr.attr);
142 attr->event_str = str;
143 attr->attr.attr.name = name;
144 attr->attr.attr.mode = 0444;
145 attr->attr.show = perf_event_sysfs_show;
147 return &attr->attr.attr;
150 static int imc_parse_event(struct device_node *np, const char *scale,
151 const char *unit, const char *prefix,
152 u32 base, struct imc_events *event)
157 if (of_property_read_u32(np, "reg", ®))
159 /* Add the base_reg value to the "reg" */
160 event->value = base + reg;
162 if (of_property_read_string(np, "event-name", &s))
165 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
169 if (of_property_read_string(np, "scale", &s))
173 event->scale = kstrdup(s, GFP_KERNEL);
178 if (of_property_read_string(np, "unit", &s))
182 event->unit = kstrdup(s, GFP_KERNEL);
196 * imc_free_events: Function to cleanup the events list, having
199 static void imc_free_events(struct imc_events *events, int nr_entries)
203 /* Nothing to clean, return */
206 for (i = 0; i < nr_entries; i++) {
207 kfree(events[i].unit);
208 kfree(events[i].scale);
209 kfree(events[i].name);
216 * update_events_in_group: Update the "events" information in an attr_group
217 * and assign the attr_group to the pmu "pmu".
219 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
221 struct attribute_group *attr_group;
222 struct attribute **attrs, *dev_str;
223 struct device_node *np, *pmu_events;
224 u32 handle, base_reg;
225 int i = 0, j = 0, ct, ret;
226 const char *prefix, *g_scale, *g_unit;
227 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
229 if (!of_property_read_u32(node, "events", &handle))
230 pmu_events = of_find_node_by_phandle(handle);
234 /* Did not find any node with a given phandle */
238 /* Get a count of number of child nodes */
239 ct = of_get_child_count(pmu_events);
241 /* Get the event prefix */
242 if (of_property_read_string(node, "events-prefix", &prefix))
245 /* Get a global unit and scale data if available */
246 if (of_property_read_string(node, "scale", &g_scale))
249 if (of_property_read_string(node, "unit", &g_unit))
252 /* "reg" property gives out the base offset of the counters data */
253 of_property_read_u32(node, "reg", &base_reg);
255 /* Allocate memory for the events */
256 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
261 /* Parse the events and update the struct */
262 for_each_child_of_node(pmu_events, np) {
263 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
268 /* Allocate memory for attribute group */
269 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
271 imc_free_events(pmu->events, ct);
276 * Allocate memory for attributes.
277 * Since we have count of events for this pmu, we also allocate
278 * memory for the scale and unit attribute for now.
279 * "ct" has the total event structs added from the events-parent node.
280 * So allocate three times the "ct" (this includes event, event_scale and
283 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
286 imc_free_events(pmu->events, ct);
290 attr_group->name = "events";
291 attr_group->attrs = attrs;
293 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
294 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
298 attrs[j++] = dev_str;
299 if (pmu->events[i].scale) {
300 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
301 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
305 attrs[j++] = dev_str;
308 if (pmu->events[i].unit) {
309 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
310 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
314 attrs[j++] = dev_str;
318 /* Save the event attribute */
319 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
324 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
325 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
327 return per_cpu(local_nest_imc_refc, cpu);
330 static void nest_change_cpu_context(int old_cpu, int new_cpu)
332 struct imc_pmu **pn = per_nest_pmu_arr;
334 if (old_cpu < 0 || new_cpu < 0)
338 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
343 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
345 int nid, target = -1;
346 const struct cpumask *l_cpumask;
347 struct imc_pmu_ref *ref;
350 * Check in the designated list for this cpu. Dont bother
351 * if not one of them.
353 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
357 * Check whether nest_imc is registered. We could end up here if the
358 * cpuhotplug callback registration fails. i.e, callback invokes the
359 * offline path for all successfully registered nodes. At this stage,
360 * nest_imc pmu will not be registered and we should return here.
362 * We return with a zero since this is not an offline failure. And
363 * cpuhp_setup_state() returns the actual failure reason to the caller,
364 * which in turn will call the cleanup routine.
370 * Now that this cpu is one of the designated,
371 * find a next cpu a) which is online and b) in same chip.
373 nid = cpu_to_node(cpu);
374 l_cpumask = cpumask_of_node(nid);
375 target = cpumask_last(l_cpumask);
378 * If this(target) is the last cpu in the cpumask for this chip,
379 * check for any possible online cpu in the chip.
381 if (unlikely(target == cpu))
382 target = cpumask_any_but(l_cpumask, cpu);
385 * Update the cpumask with the target cpu and
386 * migrate the context if needed
388 if (target >= 0 && target < nr_cpu_ids) {
389 cpumask_set_cpu(target, &nest_imc_cpumask);
390 nest_change_cpu_context(cpu, target);
392 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
393 get_hard_smp_processor_id(cpu));
395 * If this is the last cpu in this chip then, skip the reference
396 * count mutex lock and make the reference count on this chip zero.
398 ref = get_nest_pmu_ref(cpu);
407 static int ppc_nest_imc_cpu_online(unsigned int cpu)
409 const struct cpumask *l_cpumask;
410 static struct cpumask tmp_mask;
413 /* Get the cpumask of this node */
414 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
417 * If this is not the first online CPU on this node, then
420 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
424 * If this is the first online cpu on this node
425 * disable the nest counters by making an OPAL call.
427 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
428 get_hard_smp_processor_id(cpu));
432 /* Make this CPU the designated target for counter collection */
433 cpumask_set_cpu(cpu, &nest_imc_cpumask);
437 static int nest_pmu_cpumask_init(void)
439 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
440 "perf/powerpc/imc:online",
441 ppc_nest_imc_cpu_online,
442 ppc_nest_imc_cpu_offline);
445 static void nest_imc_counters_release(struct perf_event *event)
448 struct imc_pmu_ref *ref;
453 node_id = cpu_to_node(event->cpu);
456 * See if we need to disable the nest PMU.
457 * If no events are currently in use, then we have to take a
458 * mutex to ensure that we don't race with another task doing
459 * enable or disable the nest counters.
461 ref = get_nest_pmu_ref(event->cpu);
465 /* Take the mutex lock for this node and then decrement the reference count */
466 mutex_lock(&ref->lock);
467 if (ref->refc == 0) {
469 * The scenario where this is true is, when perf session is
470 * started, followed by offlining of all cpus in a given node.
472 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
473 * function set the ref->count to zero, if the cpu which is
474 * about to offline is the last cpu in a given node and make
475 * an OPAL call to disable the engine in that node.
478 mutex_unlock(&ref->lock);
482 if (ref->refc == 0) {
483 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
484 get_hard_smp_processor_id(event->cpu));
486 mutex_unlock(&ref->lock);
487 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
490 } else if (ref->refc < 0) {
491 WARN(1, "nest-imc: Invalid event reference count\n");
494 mutex_unlock(&ref->lock);
497 static int nest_imc_event_init(struct perf_event *event)
499 int chip_id, rc, node_id;
500 u32 l_config, config = event->attr.config;
501 struct imc_mem_info *pcni;
503 struct imc_pmu_ref *ref;
506 if (event->attr.type != event->pmu->type)
509 /* Sampling not supported */
510 if (event->hw.sample_period)
516 pmu = imc_event_to_pmu(event);
518 /* Sanity check for config (event offset) */
519 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
523 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
524 * Get the base memory addresss for this cpu.
526 chip_id = cpu_to_chip_id(event->cpu);
528 /* Return, if chip_id is not valid */
532 pcni = pmu->mem_info;
534 if (pcni->id == chip_id) {
539 } while (pcni->vbase != 0);
545 * Add the event offset to the base address.
547 l_config = config & IMC_EVENT_OFFSET_MASK;
548 event->hw.event_base = (u64)pcni->vbase + l_config;
549 node_id = cpu_to_node(event->cpu);
552 * Get the imc_pmu_ref struct for this node.
553 * Take the mutex lock and then increment the count of nest pmu events
556 ref = get_nest_pmu_ref(event->cpu);
560 mutex_lock(&ref->lock);
561 if (ref->refc == 0) {
562 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
563 get_hard_smp_processor_id(event->cpu));
565 mutex_unlock(&ref->lock);
566 pr_err("nest-imc: Unable to start the counters for node %d\n",
572 mutex_unlock(&ref->lock);
574 event->destroy = nest_imc_counters_release;
579 * core_imc_mem_init : Initializes memory for the current core.
581 * Uses alloc_pages_node() and uses the returned address as an argument to
582 * an opal call to configure the pdbar. The address sent as an argument is
583 * converted to physical address before the opal call is made. This is the
584 * base address at which the core imc counters are populated.
586 static int core_imc_mem_init(int cpu, int size)
588 int nid, rc = 0, core_id = (cpu / threads_per_core);
589 struct imc_mem_info *mem_info;
593 * alloc_pages_node() will allocate memory for core in the
596 nid = cpu_to_node(cpu);
597 mem_info = &core_imc_pmu->mem_info[core_id];
598 mem_info->id = core_id;
600 /* We need only vbase for core counters */
601 page = alloc_pages_node(nid,
602 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
603 __GFP_NOWARN, get_order(size));
606 mem_info->vbase = page_address(page);
609 core_imc_refc[core_id].id = core_id;
610 mutex_init(&core_imc_refc[core_id].lock);
612 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
613 __pa((void *)mem_info->vbase),
614 get_hard_smp_processor_id(cpu));
616 free_pages((u64)mem_info->vbase, get_order(size));
617 mem_info->vbase = NULL;
623 static bool is_core_imc_mem_inited(int cpu)
625 struct imc_mem_info *mem_info;
626 int core_id = (cpu / threads_per_core);
628 mem_info = &core_imc_pmu->mem_info[core_id];
629 if (!mem_info->vbase)
635 static int ppc_core_imc_cpu_online(unsigned int cpu)
637 const struct cpumask *l_cpumask;
638 static struct cpumask tmp_mask;
641 /* Get the cpumask for this core */
642 l_cpumask = cpu_sibling_mask(cpu);
644 /* If a cpu for this core is already set, then, don't do anything */
645 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
648 if (!is_core_imc_mem_inited(cpu)) {
649 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
651 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
656 /* set the cpu in the mask */
657 cpumask_set_cpu(cpu, &core_imc_cpumask);
661 static int ppc_core_imc_cpu_offline(unsigned int cpu)
663 unsigned int core_id;
665 struct imc_pmu_ref *ref;
668 * clear this cpu out of the mask, if not present in the mask,
669 * don't bother doing anything.
671 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
675 * Check whether core_imc is registered. We could end up here
676 * if the cpuhotplug callback registration fails. i.e, callback
677 * invokes the offline path for all sucessfully registered cpus.
678 * At this stage, core_imc pmu will not be registered and we
679 * should return here.
681 * We return with a zero since this is not an offline failure.
682 * And cpuhp_setup_state() returns the actual failure reason
683 * to the caller, which inturn will call the cleanup routine.
685 if (!core_imc_pmu->pmu.event_init)
688 /* Find any online cpu in that core except the current "cpu" */
689 ncpu = cpumask_last(cpu_sibling_mask(cpu));
691 if (unlikely(ncpu == cpu))
692 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
694 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
695 cpumask_set_cpu(ncpu, &core_imc_cpumask);
696 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
699 * If this is the last cpu in this core then, skip taking refernce
700 * count mutex lock for this core and directly zero "refc" for
703 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
704 get_hard_smp_processor_id(cpu));
705 core_id = cpu / threads_per_core;
706 ref = &core_imc_refc[core_id];
712 * Reduce the global reference count, if this is the
713 * last cpu in this core and core-imc event running
716 mutex_lock(&imc_global_refc.lock);
717 if (imc_global_refc.id == IMC_DOMAIN_CORE)
718 imc_global_refc.refc--;
720 mutex_unlock(&imc_global_refc.lock);
725 static int core_imc_pmu_cpumask_init(void)
727 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
728 "perf/powerpc/imc_core:online",
729 ppc_core_imc_cpu_online,
730 ppc_core_imc_cpu_offline);
733 static void reset_global_refc(struct perf_event *event)
735 mutex_lock(&imc_global_refc.lock);
736 imc_global_refc.refc--;
739 * If no other thread is running any
740 * event for this domain(thread/core/trace),
741 * set the global id to zero.
743 if (imc_global_refc.refc <= 0) {
744 imc_global_refc.refc = 0;
745 imc_global_refc.id = 0;
747 mutex_unlock(&imc_global_refc.lock);
750 static void core_imc_counters_release(struct perf_event *event)
753 struct imc_pmu_ref *ref;
758 * See if we need to disable the IMC PMU.
759 * If no events are currently in use, then we have to take a
760 * mutex to ensure that we don't race with another task doing
761 * enable or disable the core counters.
763 core_id = event->cpu / threads_per_core;
765 /* Take the mutex lock and decrement the refernce count for this core */
766 ref = &core_imc_refc[core_id];
770 mutex_lock(&ref->lock);
771 if (ref->refc == 0) {
773 * The scenario where this is true is, when perf session is
774 * started, followed by offlining of all cpus in a given core.
776 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
777 * function set the ref->count to zero, if the cpu which is
778 * about to offline is the last cpu in a given core and make
779 * an OPAL call to disable the engine in that core.
782 mutex_unlock(&ref->lock);
786 if (ref->refc == 0) {
787 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
788 get_hard_smp_processor_id(event->cpu));
790 mutex_unlock(&ref->lock);
791 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
794 } else if (ref->refc < 0) {
795 WARN(1, "core-imc: Invalid event reference count\n");
798 mutex_unlock(&ref->lock);
800 reset_global_refc(event);
803 static int core_imc_event_init(struct perf_event *event)
806 u64 config = event->attr.config;
807 struct imc_mem_info *pcmi;
809 struct imc_pmu_ref *ref;
811 if (event->attr.type != event->pmu->type)
814 /* Sampling not supported */
815 if (event->hw.sample_period)
822 pmu = imc_event_to_pmu(event);
824 /* Sanity check for config (event offset) */
825 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
828 if (!is_core_imc_mem_inited(event->cpu))
831 core_id = event->cpu / threads_per_core;
832 pcmi = &core_imc_pmu->mem_info[core_id];
836 /* Get the core_imc mutex for this core */
837 ref = &core_imc_refc[core_id];
842 * Core pmu units are enabled only when it is used.
843 * See if this is triggered for the first time.
844 * If yes, take the mutex lock and enable the core counters.
845 * If not, just increment the count in core_imc_refc struct.
847 mutex_lock(&ref->lock);
848 if (ref->refc == 0) {
849 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
850 get_hard_smp_processor_id(event->cpu));
852 mutex_unlock(&ref->lock);
853 pr_err("core-imc: Unable to start the counters for core %d\n",
859 mutex_unlock(&ref->lock);
862 * Since the system can run either in accumulation or trace-mode
863 * of IMC at a time, core-imc events are allowed only if no other
864 * trace/thread imc events are enabled/monitored.
866 * Take the global lock, and check the refc.id
867 * to know whether any other trace/thread imc
868 * events are running.
870 mutex_lock(&imc_global_refc.lock);
871 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
873 * No other trace/thread imc events are running in
874 * the system, so set the refc.id to core-imc.
876 imc_global_refc.id = IMC_DOMAIN_CORE;
877 imc_global_refc.refc++;
879 mutex_unlock(&imc_global_refc.lock);
882 mutex_unlock(&imc_global_refc.lock);
884 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
885 event->destroy = core_imc_counters_release;
890 * Allocates a page of memory for each of the online cpus, and load
892 * The physical base address of the page allocated for a cpu will be
893 * written to the LDBAR for that cpu, when the thread-imc event
896 * LDBAR Register Layout:
898 * 0 4 8 12 16 20 24 28
899 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
900 * | | [ ] [ Counter Address [8:50]
905 * 32 36 40 44 48 52 56 60
906 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
907 * Counter Address [8:50] ]
910 static int thread_imc_mem_alloc(int cpu_id, int size)
912 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
913 int nid = cpu_to_node(cpu_id);
918 * This case could happen only once at start, since we dont
919 * free the memory in cpu offline path.
921 page = alloc_pages_node(nid,
922 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
923 __GFP_NOWARN, get_order(size));
926 local_mem = page_address(page);
928 per_cpu(thread_imc_mem, cpu_id) = local_mem;
931 mtspr(SPRN_LDBAR, 0);
935 static int ppc_thread_imc_cpu_online(unsigned int cpu)
937 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
940 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
943 * Set the bit 0 of LDBAR to zero.
945 * If bit 0 of LDBAR is unset, it will stop posting
946 * the counter data to memory.
947 * For thread-imc, bit 0 of LDBAR will be set to 1 in the
948 * event_add function. So reset this bit here, to stop the updates
949 * to memory in the cpu_offline path.
951 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
953 /* Reduce the refc if thread-imc event running on this cpu */
954 mutex_lock(&imc_global_refc.lock);
955 if (imc_global_refc.id == IMC_DOMAIN_THREAD)
956 imc_global_refc.refc--;
957 mutex_unlock(&imc_global_refc.lock);
962 static int thread_imc_cpu_init(void)
964 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
965 "perf/powerpc/imc_thread:online",
966 ppc_thread_imc_cpu_online,
967 ppc_thread_imc_cpu_offline);
970 static int thread_imc_event_init(struct perf_event *event)
972 u32 config = event->attr.config;
973 struct task_struct *target;
976 if (event->attr.type != event->pmu->type)
979 if (!perfmon_capable())
982 /* Sampling not supported */
983 if (event->hw.sample_period)
987 pmu = imc_event_to_pmu(event);
989 /* Sanity check for config offset */
990 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
993 target = event->hw.target;
997 mutex_lock(&imc_global_refc.lock);
999 * Check if any other trace/core imc events are running in the
1000 * system, if not set the global id to thread-imc.
1002 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1003 imc_global_refc.id = IMC_DOMAIN_THREAD;
1004 imc_global_refc.refc++;
1006 mutex_unlock(&imc_global_refc.lock);
1009 mutex_unlock(&imc_global_refc.lock);
1011 event->pmu->task_ctx_nr = perf_sw_context;
1012 event->destroy = reset_global_refc;
1016 static bool is_thread_imc_pmu(struct perf_event *event)
1018 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1024 static u64 * get_event_base_addr(struct perf_event *event)
1028 if (is_thread_imc_pmu(event)) {
1029 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1030 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1033 return (u64 *)event->hw.event_base;
1036 static void thread_imc_pmu_start_txn(struct pmu *pmu,
1037 unsigned int txn_flags)
1039 if (txn_flags & ~PERF_PMU_TXN_ADD)
1041 perf_pmu_disable(pmu);
1044 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1046 perf_pmu_enable(pmu);
1049 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1051 perf_pmu_enable(pmu);
1055 static u64 imc_read_counter(struct perf_event *event)
1060 * In-Memory Collection (IMC) counters are free flowing counters.
1061 * So we take a snapshot of the counter value on enable and save it
1062 * to calculate the delta at later stage to present the event counter
1065 addr = get_event_base_addr(event);
1066 data = be64_to_cpu(READ_ONCE(*addr));
1067 local64_set(&event->hw.prev_count, data);
1072 static void imc_event_update(struct perf_event *event)
1074 u64 counter_prev, counter_new, final_count;
1076 counter_prev = local64_read(&event->hw.prev_count);
1077 counter_new = imc_read_counter(event);
1078 final_count = counter_new - counter_prev;
1080 /* Update the delta to the event count */
1081 local64_add(final_count, &event->count);
1084 static void imc_event_start(struct perf_event *event, int flags)
1087 * In Memory Counters are free flowing counters. HW or the microcode
1088 * keeps adding to the counter offset in memory. To get event
1089 * counter value, we snapshot the value here and we calculate
1090 * delta at later point.
1092 imc_read_counter(event);
1095 static void imc_event_stop(struct perf_event *event, int flags)
1098 * Take a snapshot and calculate the delta and update
1099 * the event counter values.
1101 imc_event_update(event);
1104 static int imc_event_add(struct perf_event *event, int flags)
1106 if (flags & PERF_EF_START)
1107 imc_event_start(event, flags);
1112 static int thread_imc_event_add(struct perf_event *event, int flags)
1115 struct imc_pmu_ref *ref;
1116 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1118 if (flags & PERF_EF_START)
1119 imc_event_start(event, flags);
1121 if (!is_core_imc_mem_inited(smp_processor_id()))
1124 core_id = smp_processor_id() / threads_per_core;
1125 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1126 mtspr(SPRN_LDBAR, ldbar_value);
1129 * imc pmus are enabled only when it is used.
1130 * See if this is triggered for the first time.
1131 * If yes, take the mutex lock and enable the counters.
1132 * If not, just increment the count in ref count struct.
1134 ref = &core_imc_refc[core_id];
1138 mutex_lock(&ref->lock);
1139 if (ref->refc == 0) {
1140 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1141 get_hard_smp_processor_id(smp_processor_id()))) {
1142 mutex_unlock(&ref->lock);
1143 pr_err("thread-imc: Unable to start the counter\
1144 for core %d\n", core_id);
1149 mutex_unlock(&ref->lock);
1153 static void thread_imc_event_del(struct perf_event *event, int flags)
1157 struct imc_pmu_ref *ref;
1159 core_id = smp_processor_id() / threads_per_core;
1160 ref = &core_imc_refc[core_id];
1162 pr_debug("imc: Failed to get event reference count\n");
1166 mutex_lock(&ref->lock);
1168 if (ref->refc == 0) {
1169 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1170 get_hard_smp_processor_id(smp_processor_id()))) {
1171 mutex_unlock(&ref->lock);
1172 pr_err("thread-imc: Unable to stop the counters\
1173 for core %d\n", core_id);
1176 } else if (ref->refc < 0) {
1179 mutex_unlock(&ref->lock);
1181 /* Set bit 0 of LDBAR to zero, to stop posting updates to memory */
1182 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1185 * Take a snapshot and calculate the delta and update
1186 * the event counter values.
1188 imc_event_update(event);
1192 * Allocate a page of memory for each cpu, and load LDBAR with 0.
1194 static int trace_imc_mem_alloc(int cpu_id, int size)
1196 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1197 int phys_id = cpu_to_node(cpu_id), rc = 0;
1198 int core_id = (cpu_id / threads_per_core);
1203 page = alloc_pages_node(phys_id,
1204 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1205 __GFP_NOWARN, get_order(size));
1208 local_mem = page_address(page);
1209 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1211 /* Initialise the counters for trace mode */
1212 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1213 get_hard_smp_processor_id(cpu_id));
1215 pr_info("IMC:opal init failed for trace imc\n");
1220 /* Init the mutex, if not already */
1221 trace_imc_refc[core_id].id = core_id;
1222 mutex_init(&trace_imc_refc[core_id].lock);
1224 mtspr(SPRN_LDBAR, 0);
1228 static int ppc_trace_imc_cpu_online(unsigned int cpu)
1230 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1233 static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1236 * No need to set bit 0 of LDBAR to zero, as
1237 * it is set to zero for imc trace-mode
1239 * Reduce the refc if any trace-imc event running
1242 mutex_lock(&imc_global_refc.lock);
1243 if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1244 imc_global_refc.refc--;
1245 mutex_unlock(&imc_global_refc.lock);
1250 static int trace_imc_cpu_init(void)
1252 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1253 "perf/powerpc/imc_trace:online",
1254 ppc_trace_imc_cpu_online,
1255 ppc_trace_imc_cpu_offline);
1258 static u64 get_trace_imc_event_base_addr(void)
1260 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1264 * Function to parse trace-imc data obtained
1265 * and to prepare the perf sample.
1267 static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1268 struct perf_sample_data *data,
1270 struct perf_event_header *header,
1271 struct perf_event *event)
1273 /* Sanity checks for a valid record */
1274 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1275 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1279 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1280 be64_to_cpu(READ_ONCE(mem->tb2)))
1283 /* Prepare perf sample */
1284 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1285 data->period = event->hw.last_period;
1287 header->type = PERF_RECORD_SAMPLE;
1288 header->size = sizeof(*header) + event->header_size;
1291 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1292 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1293 case 0:/* when MSR HV and PR not set in the trace-record */
1294 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1296 case 1: /* MSR HV is 0 and PR is 1 */
1297 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1299 case 2: /* MSR HV is 1 and PR is 0 */
1300 header->misc |= PERF_RECORD_MISC_KERNEL;
1302 case 3: /* MSR HV is 1 and PR is 1 */
1303 header->misc |= PERF_RECORD_MISC_USER;
1306 pr_info("IMC: Unable to set the flag based on MSR bits\n");
1310 if (is_kernel_addr(data->ip))
1311 header->misc |= PERF_RECORD_MISC_KERNEL;
1313 header->misc |= PERF_RECORD_MISC_USER;
1315 perf_event_header__init_id(header, data, event);
1320 static void dump_trace_imc_data(struct perf_event *event)
1322 struct trace_imc_data *mem;
1326 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1327 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1329 struct perf_sample_data data;
1330 struct perf_event_header header;
1332 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1333 if (ret) /* Exit, if not a valid record */
1336 /* If this is a valid record, create the sample */
1337 struct perf_output_handle handle;
1339 if (perf_output_begin(&handle, &data, event, header.size))
1342 perf_output_sample(&handle, &header, &data, event);
1343 perf_output_end(&handle);
1348 static int trace_imc_event_add(struct perf_event *event, int flags)
1350 int core_id = smp_processor_id() / threads_per_core;
1351 struct imc_pmu_ref *ref = NULL;
1352 u64 local_mem, ldbar_value;
1354 /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1355 local_mem = get_trace_imc_event_base_addr();
1356 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1358 /* trace-imc reference count */
1360 ref = &trace_imc_refc[core_id];
1362 pr_debug("imc: Failed to get the event reference count\n");
1366 mtspr(SPRN_LDBAR, ldbar_value);
1367 mutex_lock(&ref->lock);
1368 if (ref->refc == 0) {
1369 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1370 get_hard_smp_processor_id(smp_processor_id()))) {
1371 mutex_unlock(&ref->lock);
1372 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1377 mutex_unlock(&ref->lock);
1381 static void trace_imc_event_read(struct perf_event *event)
1386 static void trace_imc_event_stop(struct perf_event *event, int flags)
1388 u64 local_mem = get_trace_imc_event_base_addr();
1389 dump_trace_imc_data(event);
1390 memset((void *)local_mem, 0, sizeof(u64));
1393 static void trace_imc_event_start(struct perf_event *event, int flags)
1398 static void trace_imc_event_del(struct perf_event *event, int flags)
1400 int core_id = smp_processor_id() / threads_per_core;
1401 struct imc_pmu_ref *ref = NULL;
1404 ref = &trace_imc_refc[core_id];
1406 pr_debug("imc: Failed to get event reference count\n");
1410 mutex_lock(&ref->lock);
1412 if (ref->refc == 0) {
1413 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1414 get_hard_smp_processor_id(smp_processor_id()))) {
1415 mutex_unlock(&ref->lock);
1416 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1419 } else if (ref->refc < 0) {
1422 mutex_unlock(&ref->lock);
1424 trace_imc_event_stop(event, flags);
1427 static int trace_imc_event_init(struct perf_event *event)
1429 if (event->attr.type != event->pmu->type)
1432 if (!perfmon_capable())
1435 /* Return if this is a couting event */
1436 if (event->attr.sample_period == 0)
1440 * Take the global lock, and make sure
1441 * no other thread is running any core/thread imc
1444 mutex_lock(&imc_global_refc.lock);
1445 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1447 * No core/thread imc events are running in the
1448 * system, so set the refc.id to trace-imc.
1450 imc_global_refc.id = IMC_DOMAIN_TRACE;
1451 imc_global_refc.refc++;
1453 mutex_unlock(&imc_global_refc.lock);
1456 mutex_unlock(&imc_global_refc.lock);
1461 * There can only be a single PMU for perf_hw_context events which is assigned to
1462 * core PMU. Hence use "perf_sw_context" for trace_imc.
1464 event->pmu->task_ctx_nr = perf_sw_context;
1465 event->destroy = reset_global_refc;
1469 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1470 static int update_pmu_ops(struct imc_pmu *pmu)
1472 pmu->pmu.task_ctx_nr = perf_invalid_context;
1473 pmu->pmu.add = imc_event_add;
1474 pmu->pmu.del = imc_event_stop;
1475 pmu->pmu.start = imc_event_start;
1476 pmu->pmu.stop = imc_event_stop;
1477 pmu->pmu.read = imc_event_update;
1478 pmu->pmu.attr_groups = pmu->attr_groups;
1479 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1480 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1482 switch (pmu->domain) {
1483 case IMC_DOMAIN_NEST:
1484 pmu->pmu.event_init = nest_imc_event_init;
1485 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1487 case IMC_DOMAIN_CORE:
1488 pmu->pmu.event_init = core_imc_event_init;
1489 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1491 case IMC_DOMAIN_THREAD:
1492 pmu->pmu.event_init = thread_imc_event_init;
1493 pmu->pmu.add = thread_imc_event_add;
1494 pmu->pmu.del = thread_imc_event_del;
1495 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1496 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1497 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1499 case IMC_DOMAIN_TRACE:
1500 pmu->pmu.event_init = trace_imc_event_init;
1501 pmu->pmu.add = trace_imc_event_add;
1502 pmu->pmu.del = trace_imc_event_del;
1503 pmu->pmu.start = trace_imc_event_start;
1504 pmu->pmu.stop = trace_imc_event_stop;
1505 pmu->pmu.read = trace_imc_event_read;
1506 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1515 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1516 static int init_nest_pmu_ref(void)
1520 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1527 for_each_node(nid) {
1529 * Mutex lock to avoid races while tracking the number of
1530 * sessions using the chip's nest pmu units.
1532 mutex_init(&nest_imc_refc[i].lock);
1535 * Loop to init the "id" with the node_id. Variable "i" initialized to
1536 * 0 and will be used as index to the array. "i" will not go off the
1537 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1540 nest_imc_refc[i++].id = nid;
1544 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1545 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1547 for_each_possible_cpu(cpu) {
1548 nid = cpu_to_node(cpu);
1549 for (i = 0; i < num_possible_nodes(); i++) {
1550 if (nest_imc_refc[i].id == nid) {
1551 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1559 static void cleanup_all_core_imc_memory(void)
1561 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1562 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1563 int size = core_imc_pmu->counter_mem_size;
1565 /* mem_info will never be NULL */
1566 for (i = 0; i < nr_cores; i++) {
1568 free_pages((u64)ptr[i].vbase, get_order(size));
1572 kfree(core_imc_refc);
1575 static void thread_imc_ldbar_disable(void *dummy)
1578 * By setting 0th bit of LDBAR to zero, we disable thread-imc
1579 * updates to memory.
1581 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1584 void thread_imc_disable(void)
1586 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1589 static void cleanup_all_thread_imc_memory(void)
1591 int i, order = get_order(thread_imc_mem_size);
1593 for_each_online_cpu(i) {
1594 if (per_cpu(thread_imc_mem, i))
1595 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1600 static void cleanup_all_trace_imc_memory(void)
1602 int i, order = get_order(trace_imc_mem_size);
1604 for_each_online_cpu(i) {
1605 if (per_cpu(trace_imc_mem, i))
1606 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1609 kfree(trace_imc_refc);
1612 /* Function to free the attr_groups which are dynamically allocated */
1613 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1615 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1616 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1617 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1621 * Common function to unregister cpu hotplug callback and
1623 * TODO: Need to handle pmu unregistering, which will be
1624 * done in followup series.
1626 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1628 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1629 mutex_lock(&nest_init_lock);
1630 if (nest_pmus == 1) {
1631 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1632 kfree(nest_imc_refc);
1633 kfree(per_nest_pmu_arr);
1634 per_nest_pmu_arr = NULL;
1639 mutex_unlock(&nest_init_lock);
1642 /* Free core_imc memory */
1643 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1644 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1645 cleanup_all_core_imc_memory();
1648 /* Free thread_imc memory */
1649 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1650 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1651 cleanup_all_thread_imc_memory();
1654 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1655 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1656 cleanup_all_trace_imc_memory();
1661 * Function to unregister thread-imc if core-imc
1662 * is not registered.
1664 void unregister_thread_imc(void)
1666 imc_common_cpuhp_mem_free(thread_imc_pmu);
1667 imc_common_mem_free(thread_imc_pmu);
1668 perf_pmu_unregister(&thread_imc_pmu->pmu);
1672 * imc_mem_init : Function to support memory allocation for core imc.
1674 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1678 int nr_cores, cpu, res = -ENOMEM;
1680 if (of_property_read_string(parent, "name", &s))
1683 switch (pmu_ptr->domain) {
1684 case IMC_DOMAIN_NEST:
1685 /* Update the pmu name */
1686 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1687 if (!pmu_ptr->pmu.name)
1690 /* Needed for hotplug/migration */
1691 if (!per_nest_pmu_arr) {
1692 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1693 sizeof(struct imc_pmu *),
1695 if (!per_nest_pmu_arr)
1698 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1700 case IMC_DOMAIN_CORE:
1701 /* Update the pmu name */
1702 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1703 if (!pmu_ptr->pmu.name)
1706 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1707 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1710 if (!pmu_ptr->mem_info)
1713 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1716 if (!core_imc_refc) {
1717 kfree(pmu_ptr->mem_info);
1721 core_imc_pmu = pmu_ptr;
1723 case IMC_DOMAIN_THREAD:
1724 /* Update the pmu name */
1725 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1726 if (!pmu_ptr->pmu.name)
1729 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1730 for_each_online_cpu(cpu) {
1731 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1733 cleanup_all_thread_imc_memory();
1738 thread_imc_pmu = pmu_ptr;
1740 case IMC_DOMAIN_TRACE:
1741 /* Update the pmu name */
1742 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1743 if (!pmu_ptr->pmu.name)
1746 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1747 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1749 if (!trace_imc_refc)
1752 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1753 for_each_online_cpu(cpu) {
1754 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1756 cleanup_all_trace_imc_memory();
1771 * init_imc_pmu : Setup and register the IMC pmu device.
1773 * @parent: Device tree unit node
1774 * @pmu_ptr: memory allocated for this pmu
1775 * @pmu_idx: Count of nest pmc registered
1777 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1778 * Handles failure cases and accordingly frees memory.
1780 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1784 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1788 switch (pmu_ptr->domain) {
1789 case IMC_DOMAIN_NEST:
1791 * Nest imc pmu need only one cpu per chip, we initialize the
1792 * cpumask for the first nest imc pmu and use the same for the
1793 * rest. To handle the cpuhotplug callback unregister, we track
1794 * the number of nest pmus in "nest_pmus".
1796 mutex_lock(&nest_init_lock);
1797 if (nest_pmus == 0) {
1798 ret = init_nest_pmu_ref();
1800 mutex_unlock(&nest_init_lock);
1801 kfree(per_nest_pmu_arr);
1802 per_nest_pmu_arr = NULL;
1805 /* Register for cpu hotplug notification. */
1806 ret = nest_pmu_cpumask_init();
1808 mutex_unlock(&nest_init_lock);
1809 kfree(nest_imc_refc);
1810 kfree(per_nest_pmu_arr);
1811 per_nest_pmu_arr = NULL;
1816 mutex_unlock(&nest_init_lock);
1818 case IMC_DOMAIN_CORE:
1819 ret = core_imc_pmu_cpumask_init();
1821 cleanup_all_core_imc_memory();
1826 case IMC_DOMAIN_THREAD:
1827 ret = thread_imc_cpu_init();
1829 cleanup_all_thread_imc_memory();
1834 case IMC_DOMAIN_TRACE:
1835 ret = trace_imc_cpu_init();
1837 cleanup_all_trace_imc_memory();
1843 return -EINVAL; /* Unknown domain */
1846 ret = update_events_in_group(parent, pmu_ptr);
1848 goto err_free_cpuhp_mem;
1850 ret = update_pmu_ops(pmu_ptr);
1852 goto err_free_cpuhp_mem;
1854 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1856 goto err_free_cpuhp_mem;
1858 pr_debug("%s performance monitor hardware support registered\n",
1864 imc_common_cpuhp_mem_free(pmu_ptr);
1866 imc_common_mem_free(pmu_ptr);