1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * In-Memory Collection (IMC) Performance Monitor counter support.
5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
6 * (C) 2017 Anju T Sudhakar, IBM Corporation.
7 * (C) 2017 Hemant K Shaw, IBM Corporation.
10 #include <linux/perf_event.h>
11 #include <linux/slab.h>
13 #include <asm/imc-pmu.h>
14 #include <asm/cputhreads.h>
16 #include <linux/string.h>
18 /* Nest IMC data structures and variables */
21 * Used to avoid races in counting the nest-pmu units during hotplug
22 * register and unregister
24 static DEFINE_MUTEX(nest_init_lock);
25 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
26 static struct imc_pmu **per_nest_pmu_arr;
27 static cpumask_t nest_imc_cpumask;
28 static struct imc_pmu_ref *nest_imc_refc;
31 /* Core IMC data structures and variables */
33 static cpumask_t core_imc_cpumask;
34 static struct imc_pmu_ref *core_imc_refc;
35 static struct imc_pmu *core_imc_pmu;
37 /* Thread IMC data structures and variables */
39 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
40 static struct imc_pmu *thread_imc_pmu;
41 static int thread_imc_mem_size;
43 /* Trace IMC data structures */
44 static DEFINE_PER_CPU(u64 *, trace_imc_mem);
45 static struct imc_pmu_ref *trace_imc_refc;
46 static int trace_imc_mem_size;
49 * Global data structure used to avoid races between thread,
52 static struct imc_pmu_ref imc_global_refc = {
53 .lock = __MUTEX_INITIALIZER(imc_global_refc.lock),
58 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
60 return container_of(event->pmu, struct imc_pmu, pmu);
63 PMU_FORMAT_ATTR(event, "config:0-61");
64 PMU_FORMAT_ATTR(offset, "config:0-31");
65 PMU_FORMAT_ATTR(rvalue, "config:32");
66 PMU_FORMAT_ATTR(mode, "config:33-40");
67 static struct attribute *imc_format_attrs[] = {
68 &format_attr_event.attr,
69 &format_attr_offset.attr,
70 &format_attr_rvalue.attr,
71 &format_attr_mode.attr,
75 static const struct attribute_group imc_format_group = {
77 .attrs = imc_format_attrs,
80 /* Format attribute for imc trace-mode */
81 PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
82 PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
83 PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
84 PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
85 static struct attribute *trace_imc_format_attrs[] = {
86 &format_attr_event.attr,
87 &format_attr_cpmc_reserved.attr,
88 &format_attr_cpmc_event.attr,
89 &format_attr_cpmc_samplesel.attr,
90 &format_attr_cpmc_load.attr,
94 static const struct attribute_group trace_imc_format_group = {
96 .attrs = trace_imc_format_attrs,
99 /* Get the cpumask printed to a buffer "buf" */
100 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
101 struct device_attribute *attr,
104 struct pmu *pmu = dev_get_drvdata(dev);
105 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
106 cpumask_t *active_mask;
108 switch(imc_pmu->domain){
109 case IMC_DOMAIN_NEST:
110 active_mask = &nest_imc_cpumask;
112 case IMC_DOMAIN_CORE:
113 active_mask = &core_imc_cpumask;
119 return cpumap_print_to_pagebuf(true, buf, active_mask);
122 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
124 static struct attribute *imc_pmu_cpumask_attrs[] = {
125 &dev_attr_cpumask.attr,
129 static const struct attribute_group imc_pmu_cpumask_attr_group = {
130 .attrs = imc_pmu_cpumask_attrs,
133 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
134 static struct attribute *device_str_attr_create(const char *name, const char *str)
136 struct perf_pmu_events_attr *attr;
138 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
141 sysfs_attr_init(&attr->attr.attr);
143 attr->event_str = str;
144 attr->attr.attr.name = name;
145 attr->attr.attr.mode = 0444;
146 attr->attr.show = perf_event_sysfs_show;
148 return &attr->attr.attr;
151 static int imc_parse_event(struct device_node *np, const char *scale,
152 const char *unit, const char *prefix,
153 u32 base, struct imc_events *event)
158 if (of_property_read_u32(np, "reg", ®))
160 /* Add the base_reg value to the "reg" */
161 event->value = base + reg;
163 if (of_property_read_string(np, "event-name", &s))
166 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
170 if (of_property_read_string(np, "scale", &s))
174 event->scale = kstrdup(s, GFP_KERNEL);
179 if (of_property_read_string(np, "unit", &s))
183 event->unit = kstrdup(s, GFP_KERNEL);
197 * imc_free_events: Function to cleanup the events list, having
200 static void imc_free_events(struct imc_events *events, int nr_entries)
204 /* Nothing to clean, return */
207 for (i = 0; i < nr_entries; i++) {
208 kfree(events[i].unit);
209 kfree(events[i].scale);
210 kfree(events[i].name);
217 * update_events_in_group: Update the "events" information in an attr_group
218 * and assign the attr_group to the pmu "pmu".
220 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
222 struct attribute_group *attr_group;
223 struct attribute **attrs, *dev_str;
224 struct device_node *np, *pmu_events;
225 u32 handle, base_reg;
226 int i = 0, j = 0, ct, ret;
227 const char *prefix, *g_scale, *g_unit;
228 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
230 if (!of_property_read_u32(node, "events", &handle))
231 pmu_events = of_find_node_by_phandle(handle);
235 /* Did not find any node with a given phandle */
239 /* Get a count of number of child nodes */
240 ct = of_get_child_count(pmu_events);
242 /* Get the event prefix */
243 if (of_property_read_string(node, "events-prefix", &prefix))
246 /* Get a global unit and scale data if available */
247 if (of_property_read_string(node, "scale", &g_scale))
250 if (of_property_read_string(node, "unit", &g_unit))
253 /* "reg" property gives out the base offset of the counters data */
254 of_property_read_u32(node, "reg", &base_reg);
256 /* Allocate memory for the events */
257 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
262 /* Parse the events and update the struct */
263 for_each_child_of_node(pmu_events, np) {
264 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
269 /* Allocate memory for attribute group */
270 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
272 imc_free_events(pmu->events, ct);
277 * Allocate memory for attributes.
278 * Since we have count of events for this pmu, we also allocate
279 * memory for the scale and unit attribute for now.
280 * "ct" has the total event structs added from the events-parent node.
281 * So allocate three times the "ct" (this includes event, event_scale and
284 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
287 imc_free_events(pmu->events, ct);
291 attr_group->name = "events";
292 attr_group->attrs = attrs;
294 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
295 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
299 attrs[j++] = dev_str;
300 if (pmu->events[i].scale) {
301 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
302 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
306 attrs[j++] = dev_str;
309 if (pmu->events[i].unit) {
310 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
311 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
315 attrs[j++] = dev_str;
319 /* Save the event attribute */
320 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
325 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
326 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
328 return per_cpu(local_nest_imc_refc, cpu);
331 static void nest_change_cpu_context(int old_cpu, int new_cpu)
333 struct imc_pmu **pn = per_nest_pmu_arr;
335 if (old_cpu < 0 || new_cpu < 0)
339 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
344 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
346 int nid, target = -1;
347 const struct cpumask *l_cpumask;
348 struct imc_pmu_ref *ref;
351 * Check in the designated list for this cpu. Dont bother
352 * if not one of them.
354 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
358 * Check whether nest_imc is registered. We could end up here if the
359 * cpuhotplug callback registration fails. i.e, callback invokes the
360 * offline path for all successfully registered nodes. At this stage,
361 * nest_imc pmu will not be registered and we should return here.
363 * We return with a zero since this is not an offline failure. And
364 * cpuhp_setup_state() returns the actual failure reason to the caller,
365 * which in turn will call the cleanup routine.
371 * Now that this cpu is one of the designated,
372 * find a next cpu a) which is online and b) in same chip.
374 nid = cpu_to_node(cpu);
375 l_cpumask = cpumask_of_node(nid);
376 target = cpumask_last(l_cpumask);
379 * If this(target) is the last cpu in the cpumask for this chip,
380 * check for any possible online cpu in the chip.
382 if (unlikely(target == cpu))
383 target = cpumask_any_but(l_cpumask, cpu);
386 * Update the cpumask with the target cpu and
387 * migrate the context if needed
389 if (target >= 0 && target < nr_cpu_ids) {
390 cpumask_set_cpu(target, &nest_imc_cpumask);
391 nest_change_cpu_context(cpu, target);
393 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
394 get_hard_smp_processor_id(cpu));
396 * If this is the last cpu in this chip then, skip the reference
397 * count mutex lock and make the reference count on this chip zero.
399 ref = get_nest_pmu_ref(cpu);
408 static int ppc_nest_imc_cpu_online(unsigned int cpu)
410 const struct cpumask *l_cpumask;
411 static struct cpumask tmp_mask;
414 /* Get the cpumask of this node */
415 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
418 * If this is not the first online CPU on this node, then
421 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
425 * If this is the first online cpu on this node
426 * disable the nest counters by making an OPAL call.
428 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
429 get_hard_smp_processor_id(cpu));
433 /* Make this CPU the designated target for counter collection */
434 cpumask_set_cpu(cpu, &nest_imc_cpumask);
438 static int nest_pmu_cpumask_init(void)
440 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
441 "perf/powerpc/imc:online",
442 ppc_nest_imc_cpu_online,
443 ppc_nest_imc_cpu_offline);
446 static void nest_imc_counters_release(struct perf_event *event)
449 struct imc_pmu_ref *ref;
454 node_id = cpu_to_node(event->cpu);
457 * See if we need to disable the nest PMU.
458 * If no events are currently in use, then we have to take a
459 * mutex to ensure that we don't race with another task doing
460 * enable or disable the nest counters.
462 ref = get_nest_pmu_ref(event->cpu);
466 /* Take the mutex lock for this node and then decrement the reference count */
467 mutex_lock(&ref->lock);
468 if (ref->refc == 0) {
470 * The scenario where this is true is, when perf session is
471 * started, followed by offlining of all cpus in a given node.
473 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
474 * function set the ref->count to zero, if the cpu which is
475 * about to offline is the last cpu in a given node and make
476 * an OPAL call to disable the engine in that node.
479 mutex_unlock(&ref->lock);
483 if (ref->refc == 0) {
484 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
485 get_hard_smp_processor_id(event->cpu));
487 mutex_unlock(&ref->lock);
488 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
491 } else if (ref->refc < 0) {
492 WARN(1, "nest-imc: Invalid event reference count\n");
495 mutex_unlock(&ref->lock);
498 static int nest_imc_event_init(struct perf_event *event)
500 int chip_id, rc, node_id;
501 u32 l_config, config = event->attr.config;
502 struct imc_mem_info *pcni;
504 struct imc_pmu_ref *ref;
507 if (event->attr.type != event->pmu->type)
510 /* Sampling not supported */
511 if (event->hw.sample_period)
517 pmu = imc_event_to_pmu(event);
519 /* Sanity check for config (event offset) */
520 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
524 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
525 * Get the base memory address for this cpu.
527 chip_id = cpu_to_chip_id(event->cpu);
529 /* Return, if chip_id is not valid */
533 pcni = pmu->mem_info;
535 if (pcni->id == chip_id) {
540 } while (pcni->vbase != 0);
546 * Add the event offset to the base address.
548 l_config = config & IMC_EVENT_OFFSET_MASK;
549 event->hw.event_base = (u64)pcni->vbase + l_config;
550 node_id = cpu_to_node(event->cpu);
553 * Get the imc_pmu_ref struct for this node.
554 * Take the mutex lock and then increment the count of nest pmu events
557 ref = get_nest_pmu_ref(event->cpu);
561 mutex_lock(&ref->lock);
562 if (ref->refc == 0) {
563 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
564 get_hard_smp_processor_id(event->cpu));
566 mutex_unlock(&ref->lock);
567 pr_err("nest-imc: Unable to start the counters for node %d\n",
573 mutex_unlock(&ref->lock);
575 event->destroy = nest_imc_counters_release;
580 * core_imc_mem_init : Initializes memory for the current core.
582 * Uses alloc_pages_node() and uses the returned address as an argument to
583 * an opal call to configure the pdbar. The address sent as an argument is
584 * converted to physical address before the opal call is made. This is the
585 * base address at which the core imc counters are populated.
587 static int core_imc_mem_init(int cpu, int size)
589 int nid, rc = 0, core_id = (cpu / threads_per_core);
590 struct imc_mem_info *mem_info;
594 * alloc_pages_node() will allocate memory for core in the
597 nid = cpu_to_node(cpu);
598 mem_info = &core_imc_pmu->mem_info[core_id];
599 mem_info->id = core_id;
601 /* We need only vbase for core counters */
602 page = alloc_pages_node(nid,
603 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
604 __GFP_NOWARN, get_order(size));
607 mem_info->vbase = page_address(page);
610 core_imc_refc[core_id].id = core_id;
611 mutex_init(&core_imc_refc[core_id].lock);
613 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
614 __pa((void *)mem_info->vbase),
615 get_hard_smp_processor_id(cpu));
617 free_pages((u64)mem_info->vbase, get_order(size));
618 mem_info->vbase = NULL;
624 static bool is_core_imc_mem_inited(int cpu)
626 struct imc_mem_info *mem_info;
627 int core_id = (cpu / threads_per_core);
629 mem_info = &core_imc_pmu->mem_info[core_id];
630 if (!mem_info->vbase)
636 static int ppc_core_imc_cpu_online(unsigned int cpu)
638 const struct cpumask *l_cpumask;
639 static struct cpumask tmp_mask;
642 /* Get the cpumask for this core */
643 l_cpumask = cpu_sibling_mask(cpu);
645 /* If a cpu for this core is already set, then, don't do anything */
646 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
649 if (!is_core_imc_mem_inited(cpu)) {
650 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
652 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
657 /* set the cpu in the mask */
658 cpumask_set_cpu(cpu, &core_imc_cpumask);
662 static int ppc_core_imc_cpu_offline(unsigned int cpu)
664 unsigned int core_id;
666 struct imc_pmu_ref *ref;
669 * clear this cpu out of the mask, if not present in the mask,
670 * don't bother doing anything.
672 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
676 * Check whether core_imc is registered. We could end up here
677 * if the cpuhotplug callback registration fails. i.e, callback
678 * invokes the offline path for all successfully registered cpus.
679 * At this stage, core_imc pmu will not be registered and we
680 * should return here.
682 * We return with a zero since this is not an offline failure.
683 * And cpuhp_setup_state() returns the actual failure reason
684 * to the caller, which inturn will call the cleanup routine.
686 if (!core_imc_pmu->pmu.event_init)
689 /* Find any online cpu in that core except the current "cpu" */
690 ncpu = cpumask_last(cpu_sibling_mask(cpu));
692 if (unlikely(ncpu == cpu))
693 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
695 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
696 cpumask_set_cpu(ncpu, &core_imc_cpumask);
697 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
700 * If this is the last cpu in this core then, skip taking refernce
701 * count mutex lock for this core and directly zero "refc" for
704 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
705 get_hard_smp_processor_id(cpu));
706 core_id = cpu / threads_per_core;
707 ref = &core_imc_refc[core_id];
713 * Reduce the global reference count, if this is the
714 * last cpu in this core and core-imc event running
717 mutex_lock(&imc_global_refc.lock);
718 if (imc_global_refc.id == IMC_DOMAIN_CORE)
719 imc_global_refc.refc--;
721 mutex_unlock(&imc_global_refc.lock);
726 static int core_imc_pmu_cpumask_init(void)
728 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
729 "perf/powerpc/imc_core:online",
730 ppc_core_imc_cpu_online,
731 ppc_core_imc_cpu_offline);
734 static void reset_global_refc(struct perf_event *event)
736 mutex_lock(&imc_global_refc.lock);
737 imc_global_refc.refc--;
740 * If no other thread is running any
741 * event for this domain(thread/core/trace),
742 * set the global id to zero.
744 if (imc_global_refc.refc <= 0) {
745 imc_global_refc.refc = 0;
746 imc_global_refc.id = 0;
748 mutex_unlock(&imc_global_refc.lock);
751 static void core_imc_counters_release(struct perf_event *event)
754 struct imc_pmu_ref *ref;
759 * See if we need to disable the IMC PMU.
760 * If no events are currently in use, then we have to take a
761 * mutex to ensure that we don't race with another task doing
762 * enable or disable the core counters.
764 core_id = event->cpu / threads_per_core;
766 /* Take the mutex lock and decrement the refernce count for this core */
767 ref = &core_imc_refc[core_id];
771 mutex_lock(&ref->lock);
772 if (ref->refc == 0) {
774 * The scenario where this is true is, when perf session is
775 * started, followed by offlining of all cpus in a given core.
777 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
778 * function set the ref->count to zero, if the cpu which is
779 * about to offline is the last cpu in a given core and make
780 * an OPAL call to disable the engine in that core.
783 mutex_unlock(&ref->lock);
787 if (ref->refc == 0) {
788 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
789 get_hard_smp_processor_id(event->cpu));
791 mutex_unlock(&ref->lock);
792 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
795 } else if (ref->refc < 0) {
796 WARN(1, "core-imc: Invalid event reference count\n");
799 mutex_unlock(&ref->lock);
801 reset_global_refc(event);
804 static int core_imc_event_init(struct perf_event *event)
807 u64 config = event->attr.config;
808 struct imc_mem_info *pcmi;
810 struct imc_pmu_ref *ref;
812 if (event->attr.type != event->pmu->type)
815 /* Sampling not supported */
816 if (event->hw.sample_period)
823 pmu = imc_event_to_pmu(event);
825 /* Sanity check for config (event offset) */
826 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
829 if (!is_core_imc_mem_inited(event->cpu))
832 core_id = event->cpu / threads_per_core;
833 pcmi = &core_imc_pmu->mem_info[core_id];
837 /* Get the core_imc mutex for this core */
838 ref = &core_imc_refc[core_id];
843 * Core pmu units are enabled only when it is used.
844 * See if this is triggered for the first time.
845 * If yes, take the mutex lock and enable the core counters.
846 * If not, just increment the count in core_imc_refc struct.
848 mutex_lock(&ref->lock);
849 if (ref->refc == 0) {
850 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
851 get_hard_smp_processor_id(event->cpu));
853 mutex_unlock(&ref->lock);
854 pr_err("core-imc: Unable to start the counters for core %d\n",
860 mutex_unlock(&ref->lock);
863 * Since the system can run either in accumulation or trace-mode
864 * of IMC at a time, core-imc events are allowed only if no other
865 * trace/thread imc events are enabled/monitored.
867 * Take the global lock, and check the refc.id
868 * to know whether any other trace/thread imc
869 * events are running.
871 mutex_lock(&imc_global_refc.lock);
872 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
874 * No other trace/thread imc events are running in
875 * the system, so set the refc.id to core-imc.
877 imc_global_refc.id = IMC_DOMAIN_CORE;
878 imc_global_refc.refc++;
880 mutex_unlock(&imc_global_refc.lock);
883 mutex_unlock(&imc_global_refc.lock);
885 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
886 event->destroy = core_imc_counters_release;
891 * Allocates a page of memory for each of the online cpus, and load
893 * The physical base address of the page allocated for a cpu will be
894 * written to the LDBAR for that cpu, when the thread-imc event
897 * LDBAR Register Layout:
899 * 0 4 8 12 16 20 24 28
900 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
901 * | | [ ] [ Counter Address [8:50]
906 * 32 36 40 44 48 52 56 60
907 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
908 * Counter Address [8:50] ]
911 static int thread_imc_mem_alloc(int cpu_id, int size)
913 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
914 int nid = cpu_to_node(cpu_id);
919 * This case could happen only once at start, since we dont
920 * free the memory in cpu offline path.
922 page = alloc_pages_node(nid,
923 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
924 __GFP_NOWARN, get_order(size));
927 local_mem = page_address(page);
929 per_cpu(thread_imc_mem, cpu_id) = local_mem;
932 mtspr(SPRN_LDBAR, 0);
936 static int ppc_thread_imc_cpu_online(unsigned int cpu)
938 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
941 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
944 * Set the bit 0 of LDBAR to zero.
946 * If bit 0 of LDBAR is unset, it will stop posting
947 * the counter data to memory.
948 * For thread-imc, bit 0 of LDBAR will be set to 1 in the
949 * event_add function. So reset this bit here, to stop the updates
950 * to memory in the cpu_offline path.
952 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
954 /* Reduce the refc if thread-imc event running on this cpu */
955 mutex_lock(&imc_global_refc.lock);
956 if (imc_global_refc.id == IMC_DOMAIN_THREAD)
957 imc_global_refc.refc--;
958 mutex_unlock(&imc_global_refc.lock);
963 static int thread_imc_cpu_init(void)
965 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
966 "perf/powerpc/imc_thread:online",
967 ppc_thread_imc_cpu_online,
968 ppc_thread_imc_cpu_offline);
971 static int thread_imc_event_init(struct perf_event *event)
973 u32 config = event->attr.config;
974 struct task_struct *target;
977 if (event->attr.type != event->pmu->type)
980 if (!perfmon_capable())
983 /* Sampling not supported */
984 if (event->hw.sample_period)
988 pmu = imc_event_to_pmu(event);
990 /* Sanity check for config offset */
991 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
994 target = event->hw.target;
998 mutex_lock(&imc_global_refc.lock);
1000 * Check if any other trace/core imc events are running in the
1001 * system, if not set the global id to thread-imc.
1003 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1004 imc_global_refc.id = IMC_DOMAIN_THREAD;
1005 imc_global_refc.refc++;
1007 mutex_unlock(&imc_global_refc.lock);
1010 mutex_unlock(&imc_global_refc.lock);
1012 event->pmu->task_ctx_nr = perf_sw_context;
1013 event->destroy = reset_global_refc;
1017 static bool is_thread_imc_pmu(struct perf_event *event)
1019 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1025 static u64 * get_event_base_addr(struct perf_event *event)
1029 if (is_thread_imc_pmu(event)) {
1030 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1031 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1034 return (u64 *)event->hw.event_base;
1037 static void thread_imc_pmu_start_txn(struct pmu *pmu,
1038 unsigned int txn_flags)
1040 if (txn_flags & ~PERF_PMU_TXN_ADD)
1042 perf_pmu_disable(pmu);
1045 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1047 perf_pmu_enable(pmu);
1050 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1052 perf_pmu_enable(pmu);
1056 static u64 imc_read_counter(struct perf_event *event)
1061 * In-Memory Collection (IMC) counters are free flowing counters.
1062 * So we take a snapshot of the counter value on enable and save it
1063 * to calculate the delta at later stage to present the event counter
1066 addr = get_event_base_addr(event);
1067 data = be64_to_cpu(READ_ONCE(*addr));
1068 local64_set(&event->hw.prev_count, data);
1073 static void imc_event_update(struct perf_event *event)
1075 u64 counter_prev, counter_new, final_count;
1077 counter_prev = local64_read(&event->hw.prev_count);
1078 counter_new = imc_read_counter(event);
1079 final_count = counter_new - counter_prev;
1081 /* Update the delta to the event count */
1082 local64_add(final_count, &event->count);
1085 static void imc_event_start(struct perf_event *event, int flags)
1088 * In Memory Counters are free flowing counters. HW or the microcode
1089 * keeps adding to the counter offset in memory. To get event
1090 * counter value, we snapshot the value here and we calculate
1091 * delta at later point.
1093 imc_read_counter(event);
1096 static void imc_event_stop(struct perf_event *event, int flags)
1099 * Take a snapshot and calculate the delta and update
1100 * the event counter values.
1102 imc_event_update(event);
1105 static int imc_event_add(struct perf_event *event, int flags)
1107 if (flags & PERF_EF_START)
1108 imc_event_start(event, flags);
1113 static int thread_imc_event_add(struct perf_event *event, int flags)
1116 struct imc_pmu_ref *ref;
1117 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1119 if (flags & PERF_EF_START)
1120 imc_event_start(event, flags);
1122 if (!is_core_imc_mem_inited(smp_processor_id()))
1125 core_id = smp_processor_id() / threads_per_core;
1126 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1127 mtspr(SPRN_LDBAR, ldbar_value);
1130 * imc pmus are enabled only when it is used.
1131 * See if this is triggered for the first time.
1132 * If yes, take the mutex lock and enable the counters.
1133 * If not, just increment the count in ref count struct.
1135 ref = &core_imc_refc[core_id];
1139 mutex_lock(&ref->lock);
1140 if (ref->refc == 0) {
1141 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1142 get_hard_smp_processor_id(smp_processor_id()))) {
1143 mutex_unlock(&ref->lock);
1144 pr_err("thread-imc: Unable to start the counter\
1145 for core %d\n", core_id);
1150 mutex_unlock(&ref->lock);
1154 static void thread_imc_event_del(struct perf_event *event, int flags)
1158 struct imc_pmu_ref *ref;
1160 core_id = smp_processor_id() / threads_per_core;
1161 ref = &core_imc_refc[core_id];
1163 pr_debug("imc: Failed to get event reference count\n");
1167 mutex_lock(&ref->lock);
1169 if (ref->refc == 0) {
1170 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1171 get_hard_smp_processor_id(smp_processor_id()))) {
1172 mutex_unlock(&ref->lock);
1173 pr_err("thread-imc: Unable to stop the counters\
1174 for core %d\n", core_id);
1177 } else if (ref->refc < 0) {
1180 mutex_unlock(&ref->lock);
1182 /* Set bit 0 of LDBAR to zero, to stop posting updates to memory */
1183 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1186 * Take a snapshot and calculate the delta and update
1187 * the event counter values.
1189 imc_event_update(event);
1193 * Allocate a page of memory for each cpu, and load LDBAR with 0.
1195 static int trace_imc_mem_alloc(int cpu_id, int size)
1197 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1198 int phys_id = cpu_to_node(cpu_id), rc = 0;
1199 int core_id = (cpu_id / threads_per_core);
1204 page = alloc_pages_node(phys_id,
1205 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1206 __GFP_NOWARN, get_order(size));
1209 local_mem = page_address(page);
1210 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1212 /* Initialise the counters for trace mode */
1213 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1214 get_hard_smp_processor_id(cpu_id));
1216 pr_info("IMC:opal init failed for trace imc\n");
1221 /* Init the mutex, if not already */
1222 trace_imc_refc[core_id].id = core_id;
1223 mutex_init(&trace_imc_refc[core_id].lock);
1225 mtspr(SPRN_LDBAR, 0);
1229 static int ppc_trace_imc_cpu_online(unsigned int cpu)
1231 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1234 static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1237 * No need to set bit 0 of LDBAR to zero, as
1238 * it is set to zero for imc trace-mode
1240 * Reduce the refc if any trace-imc event running
1243 mutex_lock(&imc_global_refc.lock);
1244 if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1245 imc_global_refc.refc--;
1246 mutex_unlock(&imc_global_refc.lock);
1251 static int trace_imc_cpu_init(void)
1253 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1254 "perf/powerpc/imc_trace:online",
1255 ppc_trace_imc_cpu_online,
1256 ppc_trace_imc_cpu_offline);
1259 static u64 get_trace_imc_event_base_addr(void)
1261 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1265 * Function to parse trace-imc data obtained
1266 * and to prepare the perf sample.
1268 static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1269 struct perf_sample_data *data,
1271 struct perf_event_header *header,
1272 struct perf_event *event)
1274 /* Sanity checks for a valid record */
1275 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1276 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1280 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1281 be64_to_cpu(READ_ONCE(mem->tb2)))
1284 /* Prepare perf sample */
1285 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1286 data->period = event->hw.last_period;
1288 header->type = PERF_RECORD_SAMPLE;
1289 header->size = sizeof(*header) + event->header_size;
1292 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1293 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1294 case 0:/* when MSR HV and PR not set in the trace-record */
1295 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1297 case 1: /* MSR HV is 0 and PR is 1 */
1298 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1300 case 2: /* MSR HV is 1 and PR is 0 */
1301 header->misc |= PERF_RECORD_MISC_KERNEL;
1303 case 3: /* MSR HV is 1 and PR is 1 */
1304 header->misc |= PERF_RECORD_MISC_USER;
1307 pr_info("IMC: Unable to set the flag based on MSR bits\n");
1311 if (is_kernel_addr(data->ip))
1312 header->misc |= PERF_RECORD_MISC_KERNEL;
1314 header->misc |= PERF_RECORD_MISC_USER;
1316 perf_event_header__init_id(header, data, event);
1321 static void dump_trace_imc_data(struct perf_event *event)
1323 struct trace_imc_data *mem;
1327 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1328 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1330 struct perf_sample_data data;
1331 struct perf_event_header header;
1333 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1334 if (ret) /* Exit, if not a valid record */
1337 /* If this is a valid record, create the sample */
1338 struct perf_output_handle handle;
1340 if (perf_output_begin(&handle, &data, event, header.size))
1343 perf_output_sample(&handle, &header, &data, event);
1344 perf_output_end(&handle);
1349 static int trace_imc_event_add(struct perf_event *event, int flags)
1351 int core_id = smp_processor_id() / threads_per_core;
1352 struct imc_pmu_ref *ref = NULL;
1353 u64 local_mem, ldbar_value;
1355 /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1356 local_mem = get_trace_imc_event_base_addr();
1357 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1359 /* trace-imc reference count */
1361 ref = &trace_imc_refc[core_id];
1363 pr_debug("imc: Failed to get the event reference count\n");
1367 mtspr(SPRN_LDBAR, ldbar_value);
1368 mutex_lock(&ref->lock);
1369 if (ref->refc == 0) {
1370 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1371 get_hard_smp_processor_id(smp_processor_id()))) {
1372 mutex_unlock(&ref->lock);
1373 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1378 mutex_unlock(&ref->lock);
1382 static void trace_imc_event_read(struct perf_event *event)
1387 static void trace_imc_event_stop(struct perf_event *event, int flags)
1389 u64 local_mem = get_trace_imc_event_base_addr();
1390 dump_trace_imc_data(event);
1391 memset((void *)local_mem, 0, sizeof(u64));
1394 static void trace_imc_event_start(struct perf_event *event, int flags)
1399 static void trace_imc_event_del(struct perf_event *event, int flags)
1401 int core_id = smp_processor_id() / threads_per_core;
1402 struct imc_pmu_ref *ref = NULL;
1405 ref = &trace_imc_refc[core_id];
1407 pr_debug("imc: Failed to get event reference count\n");
1411 mutex_lock(&ref->lock);
1413 if (ref->refc == 0) {
1414 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1415 get_hard_smp_processor_id(smp_processor_id()))) {
1416 mutex_unlock(&ref->lock);
1417 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1420 } else if (ref->refc < 0) {
1423 mutex_unlock(&ref->lock);
1425 trace_imc_event_stop(event, flags);
1428 static int trace_imc_event_init(struct perf_event *event)
1430 if (event->attr.type != event->pmu->type)
1433 if (!perfmon_capable())
1436 /* Return if this is a couting event */
1437 if (event->attr.sample_period == 0)
1441 * Take the global lock, and make sure
1442 * no other thread is running any core/thread imc
1445 mutex_lock(&imc_global_refc.lock);
1446 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1448 * No core/thread imc events are running in the
1449 * system, so set the refc.id to trace-imc.
1451 imc_global_refc.id = IMC_DOMAIN_TRACE;
1452 imc_global_refc.refc++;
1454 mutex_unlock(&imc_global_refc.lock);
1457 mutex_unlock(&imc_global_refc.lock);
1462 * There can only be a single PMU for perf_hw_context events which is assigned to
1463 * core PMU. Hence use "perf_sw_context" for trace_imc.
1465 event->pmu->task_ctx_nr = perf_sw_context;
1466 event->destroy = reset_global_refc;
1470 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1471 static int update_pmu_ops(struct imc_pmu *pmu)
1473 pmu->pmu.task_ctx_nr = perf_invalid_context;
1474 pmu->pmu.add = imc_event_add;
1475 pmu->pmu.del = imc_event_stop;
1476 pmu->pmu.start = imc_event_start;
1477 pmu->pmu.stop = imc_event_stop;
1478 pmu->pmu.read = imc_event_update;
1479 pmu->pmu.attr_groups = pmu->attr_groups;
1480 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1481 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1483 switch (pmu->domain) {
1484 case IMC_DOMAIN_NEST:
1485 pmu->pmu.event_init = nest_imc_event_init;
1486 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1488 case IMC_DOMAIN_CORE:
1489 pmu->pmu.event_init = core_imc_event_init;
1490 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1492 case IMC_DOMAIN_THREAD:
1493 pmu->pmu.event_init = thread_imc_event_init;
1494 pmu->pmu.add = thread_imc_event_add;
1495 pmu->pmu.del = thread_imc_event_del;
1496 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1497 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1498 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1500 case IMC_DOMAIN_TRACE:
1501 pmu->pmu.event_init = trace_imc_event_init;
1502 pmu->pmu.add = trace_imc_event_add;
1503 pmu->pmu.del = trace_imc_event_del;
1504 pmu->pmu.start = trace_imc_event_start;
1505 pmu->pmu.stop = trace_imc_event_stop;
1506 pmu->pmu.read = trace_imc_event_read;
1507 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1516 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1517 static int init_nest_pmu_ref(void)
1521 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1528 for_each_node(nid) {
1530 * Mutex lock to avoid races while tracking the number of
1531 * sessions using the chip's nest pmu units.
1533 mutex_init(&nest_imc_refc[i].lock);
1536 * Loop to init the "id" with the node_id. Variable "i" initialized to
1537 * 0 and will be used as index to the array. "i" will not go off the
1538 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1541 nest_imc_refc[i++].id = nid;
1545 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1546 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1548 for_each_possible_cpu(cpu) {
1549 nid = cpu_to_node(cpu);
1550 for (i = 0; i < num_possible_nodes(); i++) {
1551 if (nest_imc_refc[i].id == nid) {
1552 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1560 static void cleanup_all_core_imc_memory(void)
1562 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1563 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1564 int size = core_imc_pmu->counter_mem_size;
1566 /* mem_info will never be NULL */
1567 for (i = 0; i < nr_cores; i++) {
1569 free_pages((u64)ptr[i].vbase, get_order(size));
1573 kfree(core_imc_refc);
1576 static void thread_imc_ldbar_disable(void *dummy)
1579 * By setting 0th bit of LDBAR to zero, we disable thread-imc
1580 * updates to memory.
1582 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1585 void thread_imc_disable(void)
1587 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1590 static void cleanup_all_thread_imc_memory(void)
1592 int i, order = get_order(thread_imc_mem_size);
1594 for_each_online_cpu(i) {
1595 if (per_cpu(thread_imc_mem, i))
1596 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1601 static void cleanup_all_trace_imc_memory(void)
1603 int i, order = get_order(trace_imc_mem_size);
1605 for_each_online_cpu(i) {
1606 if (per_cpu(trace_imc_mem, i))
1607 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1610 kfree(trace_imc_refc);
1613 /* Function to free the attr_groups which are dynamically allocated */
1614 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1616 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1617 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1618 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1622 * Common function to unregister cpu hotplug callback and
1624 * TODO: Need to handle pmu unregistering, which will be
1625 * done in followup series.
1627 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1629 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1630 mutex_lock(&nest_init_lock);
1631 if (nest_pmus == 1) {
1632 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1633 kfree(nest_imc_refc);
1634 kfree(per_nest_pmu_arr);
1635 per_nest_pmu_arr = NULL;
1640 mutex_unlock(&nest_init_lock);
1643 /* Free core_imc memory */
1644 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1645 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1646 cleanup_all_core_imc_memory();
1649 /* Free thread_imc memory */
1650 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1651 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1652 cleanup_all_thread_imc_memory();
1655 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1656 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1657 cleanup_all_trace_imc_memory();
1662 * Function to unregister thread-imc if core-imc
1663 * is not registered.
1665 void unregister_thread_imc(void)
1667 imc_common_cpuhp_mem_free(thread_imc_pmu);
1668 imc_common_mem_free(thread_imc_pmu);
1669 perf_pmu_unregister(&thread_imc_pmu->pmu);
1673 * imc_mem_init : Function to support memory allocation for core imc.
1675 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1679 int nr_cores, cpu, res = -ENOMEM;
1681 if (of_property_read_string(parent, "name", &s))
1684 switch (pmu_ptr->domain) {
1685 case IMC_DOMAIN_NEST:
1686 /* Update the pmu name */
1687 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1688 if (!pmu_ptr->pmu.name)
1691 /* Needed for hotplug/migration */
1692 if (!per_nest_pmu_arr) {
1693 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1694 sizeof(struct imc_pmu *),
1696 if (!per_nest_pmu_arr)
1699 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1701 case IMC_DOMAIN_CORE:
1702 /* Update the pmu name */
1703 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1704 if (!pmu_ptr->pmu.name)
1707 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1708 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1711 if (!pmu_ptr->mem_info)
1714 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1717 if (!core_imc_refc) {
1718 kfree(pmu_ptr->mem_info);
1722 core_imc_pmu = pmu_ptr;
1724 case IMC_DOMAIN_THREAD:
1725 /* Update the pmu name */
1726 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1727 if (!pmu_ptr->pmu.name)
1730 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1731 for_each_online_cpu(cpu) {
1732 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1734 cleanup_all_thread_imc_memory();
1739 thread_imc_pmu = pmu_ptr;
1741 case IMC_DOMAIN_TRACE:
1742 /* Update the pmu name */
1743 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1744 if (!pmu_ptr->pmu.name)
1747 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1748 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1750 if (!trace_imc_refc)
1753 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1754 for_each_online_cpu(cpu) {
1755 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1757 cleanup_all_trace_imc_memory();
1772 * init_imc_pmu : Setup and register the IMC pmu device.
1774 * @parent: Device tree unit node
1775 * @pmu_ptr: memory allocated for this pmu
1776 * @pmu_idx: Count of nest pmc registered
1778 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1779 * Handles failure cases and accordingly frees memory.
1781 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1785 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1789 switch (pmu_ptr->domain) {
1790 case IMC_DOMAIN_NEST:
1792 * Nest imc pmu need only one cpu per chip, we initialize the
1793 * cpumask for the first nest imc pmu and use the same for the
1794 * rest. To handle the cpuhotplug callback unregister, we track
1795 * the number of nest pmus in "nest_pmus".
1797 mutex_lock(&nest_init_lock);
1798 if (nest_pmus == 0) {
1799 ret = init_nest_pmu_ref();
1801 mutex_unlock(&nest_init_lock);
1802 kfree(per_nest_pmu_arr);
1803 per_nest_pmu_arr = NULL;
1806 /* Register for cpu hotplug notification. */
1807 ret = nest_pmu_cpumask_init();
1809 mutex_unlock(&nest_init_lock);
1810 kfree(nest_imc_refc);
1811 kfree(per_nest_pmu_arr);
1812 per_nest_pmu_arr = NULL;
1817 mutex_unlock(&nest_init_lock);
1819 case IMC_DOMAIN_CORE:
1820 ret = core_imc_pmu_cpumask_init();
1822 cleanup_all_core_imc_memory();
1827 case IMC_DOMAIN_THREAD:
1828 ret = thread_imc_cpu_init();
1830 cleanup_all_thread_imc_memory();
1835 case IMC_DOMAIN_TRACE:
1836 ret = trace_imc_cpu_init();
1838 cleanup_all_trace_imc_memory();
1844 return -EINVAL; /* Unknown domain */
1847 ret = update_events_in_group(parent, pmu_ptr);
1849 goto err_free_cpuhp_mem;
1851 ret = update_pmu_ops(pmu_ptr);
1853 goto err_free_cpuhp_mem;
1855 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1857 goto err_free_cpuhp_mem;
1859 pr_debug("%s performance monitor hardware support registered\n",
1865 imc_common_cpuhp_mem_free(pmu_ptr);
1867 imc_common_mem_free(pmu_ptr);